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axi_ad9361: Split dma data into individual channels for both ADC and DAC

main
Adrian Costina 2014-06-07 17:15:31 +03:00
parent 2837d788a6
commit bef6a9c32c
8 changed files with 656 additions and 330 deletions
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92
library/axi_ad9361/axi_ad9361.v
View File

@ -73,14 +73,33 @@ module axi_ad9361 (
l_clk, l_clk,
clk, clk,
adc_dwr, adc_chan_i1,
adc_ddata, adc_enable_0,
adc_dsync, adc_valid_0,
adc_chan_q1,
adc_enable_1,
adc_valid_1,
adc_chan_i2,
adc_enable_2,
adc_valid_2,
adc_chan_q2,
adc_enable_3,
adc_valid_3,
adc_dovf, adc_dovf,
adc_dunf, adc_dunf,
dac_drd, dac_data_0,
dac_ddata, dac_enable_0,
dac_drd_0,
dac_data_1,
dac_enable_1,
dac_drd_1,
dac_data_2,
dac_enable_2,
dac_drd_2,
dac_data_3,
dac_enable_3,
dac_drd_3,
dac_dovf, dac_dovf,
dac_dunf, dac_dunf,
@ -159,14 +178,34 @@ module axi_ad9361 (
output l_clk; output l_clk;
input clk; input clk;
output adc_dwr;
output [63:0] adc_ddata; output [15:0] adc_chan_i1;
output adc_dsync; output adc_enable_0;
output adc_valid_0;
output [15:0] adc_chan_q1;
output adc_enable_1;
output adc_valid_1;
output [15:0] adc_chan_i2;
output adc_enable_2;
output adc_valid_2;
output [15:0] adc_chan_q2;
output adc_enable_3;
output adc_valid_3;
input adc_dovf; input adc_dovf;
input adc_dunf; input adc_dunf;
output dac_drd; input [15:0] dac_data_0;
input [63:0] dac_ddata; output dac_enable_0;
output dac_drd_0;
input [15:0] dac_data_1;
output dac_enable_1;
output dac_drd_1;
input [15:0] dac_data_2;
output dac_enable_2;
output dac_drd_2;
input [15:0] dac_data_3;
output dac_enable_3;
output dac_drd_3;
input dac_dovf; input dac_dovf;
input dac_dunf; input dac_dunf;
@ -416,11 +455,20 @@ module axi_ad9361 (
.delay_rdata (delay_rdata_s), .delay_rdata (delay_rdata_s),
.delay_ack_t (delay_ack_t_s), .delay_ack_t (delay_ack_t_s),
.delay_locked (delay_locked_s), .delay_locked (delay_locked_s),
.adc_dwr (adc_dwr), .adc_chan_i1 (adc_chan_i1),
.adc_ddata (adc_ddata), .adc_chan_q1 (adc_chan_q1),
.adc_dsync (adc_dsync), .adc_chan_i2 (adc_chan_i2),
.adc_chan_q2 (adc_chan_q2),
.adc_dovf (adc_dovf), .adc_dovf (adc_dovf),
.adc_dunf (adc_dunf), .adc_dunf (adc_dunf),
.adc_enable_0 (adc_enable_0),
.adc_enable_1 (adc_enable_1),
.adc_enable_2 (adc_enable_2),
.adc_enable_3 (adc_enable_3),
.adc_valid_0(adc_valid_0),
.adc_valid_1(adc_valid_1),
.adc_valid_2(adc_valid_2),
.adc_valid_3(adc_valid_3),
.up_rstn (up_rstn), .up_rstn (up_rstn),
.up_clk (up_clk), .up_clk (up_clk),
.up_sel (up_sel_s), .up_sel (up_sel_s),
@ -457,10 +505,20 @@ module axi_ad9361 (
.dac_r1_mode (dac_r1_mode_s), .dac_r1_mode (dac_r1_mode_s),
.dac_enable_in (dac_enable_in), .dac_enable_in (dac_enable_in),
.dac_enable_out (dac_enable_out), .dac_enable_out (dac_enable_out),
.dac_drd (dac_drd), .dac_drd_0(dac_drd_0),
.dac_ddata (dac_ddata), .dac_drd_1(dac_drd_1),
.dac_dovf (dac_dovf), .dac_drd_2(dac_drd_2),
.dac_dunf (dac_dunf), .dac_drd_3(dac_drd_3),
.dac_enable_0(dac_enable_0),
.dac_enable_1(dac_enable_1),
.dac_enable_2(dac_enable_2),
.dac_enable_3(dac_enable_3),
.dac_data_0(dac_data_0),
.dac_data_1(dac_data_1),
.dac_data_2(dac_data_2),
.dac_data_3(dac_data_3),
.dac_dovf(dac_dovf),
.dac_dunf(dac_dunf),
.up_rstn (up_rstn), .up_rstn (up_rstn),
.up_clk (up_clk), .up_clk (up_clk),
.up_sel (up_sel_s), .up_sel (up_sel_s),

323
library/axi_ad9361/axi_ad9361_rx.v
View File

@ -79,9 +79,18 @@ module axi_ad9361_rx (
// dma interface // dma interface
adc_dwr, adc_chan_i1,
adc_ddata, adc_enable_0,
adc_dsync, adc_valid_0,
adc_chan_q1,
adc_enable_1,
adc_valid_1,
adc_chan_i2,
adc_enable_2,
adc_valid_2,
adc_chan_q2,
adc_enable_3,
adc_valid_3,
adc_dovf, adc_dovf,
adc_dunf, adc_dunf,
@ -148,9 +157,18 @@ module axi_ad9361_rx (
// dma interface // dma interface
output adc_dwr; output [15:0] adc_chan_i1;
output [63:0] adc_ddata; output adc_enable_0;
output adc_dsync; output adc_valid_0;
output [15:0] adc_chan_q1;
output adc_enable_1;
output adc_valid_1;
output [15:0] adc_chan_i2;
output adc_enable_2;
output adc_valid_2;
output [15:0] adc_chan_q2;
output adc_enable_3;
output adc_valid_3;
input adc_dovf; input adc_dovf;
input adc_dunf; input adc_dunf;
@ -178,20 +196,7 @@ module axi_ad9361_rx (
// internal registers // internal registers
reg [47:0] adc_iqcor_data_3_1110 = 'd0;
reg [47:0] adc_iqcor_data_3_1101 = 'd0;
reg [47:0] adc_iqcor_data_3_1011 = 'd0;
reg [47:0] adc_iqcor_data_3_0111 = 'd0;
reg adc_iqcor_valid = 'd0; reg adc_iqcor_valid = 'd0;
reg adc_iqcor_valid_3 = 'd0;
reg adc_iqcor_sync = 'd0;
reg adc_iqcor_sync_3 = 'd0;
reg [63:0] adc_iqcor_data = 'd0;
reg [63:0] adc_iqcor_data_1110 = 'd0;
reg [63:0] adc_iqcor_data_1101 = 'd0;
reg [63:0] adc_iqcor_data_1011 = 'd0;
reg [63:0] adc_iqcor_data_0111 = 'd0;
reg [ 1:0] adc_iqcor_data_cnt = 'd0;
reg up_adc_status_pn_err = 'd0; reg up_adc_status_pn_err = 'd0;
reg up_adc_status_pn_oos = 'd0; reg up_adc_status_pn_oos = 'd0;
reg up_adc_status_or = 'd0; reg up_adc_status_or = 'd0;
@ -208,18 +213,12 @@ module axi_ad9361_rx (
wire [15:0] adc_dcfilter_data_out_0_s; wire [15:0] adc_dcfilter_data_out_0_s;
wire adc_pn_oos_out_0_s; wire adc_pn_oos_out_0_s;
wire adc_pn_err_out_0_s; wire adc_pn_err_out_0_s;
wire adc_iqcor_valid_0_s;
wire [15:0] adc_iqcor_data_0_s;
wire adc_enable_0_s;
wire up_adc_pn_err_0_s; wire up_adc_pn_err_0_s;
wire up_adc_pn_oos_0_s; wire up_adc_pn_oos_0_s;
wire up_adc_or_0_s; wire up_adc_or_0_s;
wire [31:0] up_rdata_0_s; wire [31:0] up_rdata_0_s;
wire up_ack_0_s; wire up_ack_0_s;
wire [15:0] adc_dcfilter_data_out_1_s; wire [15:0] adc_dcfilter_data_out_1_s;
wire adc_iqcor_valid_1_s;
wire [15:0] adc_iqcor_data_1_s;
wire adc_enable_1_s;
wire up_adc_pn_err_1_s; wire up_adc_pn_err_1_s;
wire up_adc_pn_oos_1_s; wire up_adc_pn_oos_1_s;
wire up_adc_or_1_s; wire up_adc_or_1_s;
@ -228,18 +227,12 @@ module axi_ad9361_rx (
wire [15:0] adc_dcfilter_data_out_2_s; wire [15:0] adc_dcfilter_data_out_2_s;
wire adc_pn_oos_out_2_s; wire adc_pn_oos_out_2_s;
wire adc_pn_err_out_2_s; wire adc_pn_err_out_2_s;
wire adc_iqcor_valid_2_s;
wire [15:0] adc_iqcor_data_2_s;
wire adc_enable_2_s;
wire up_adc_pn_err_2_s; wire up_adc_pn_err_2_s;
wire up_adc_pn_oos_2_s; wire up_adc_pn_oos_2_s;
wire up_adc_or_2_s; wire up_adc_or_2_s;
wire [31:0] up_rdata_2_s; wire [31:0] up_rdata_2_s;
wire up_ack_2_s; wire up_ack_2_s;
wire [15:0] adc_dcfilter_data_out_3_s; wire [15:0] adc_dcfilter_data_out_3_s;
wire adc_iqcor_valid_3_s;
wire [15:0] adc_iqcor_data_3_s;
wire adc_enable_3_s;
wire up_adc_pn_err_3_s; wire up_adc_pn_err_3_s;
wire up_adc_pn_oos_3_s; wire up_adc_pn_oos_3_s;
wire up_adc_or_3_s; wire up_adc_or_3_s;
@ -261,14 +254,14 @@ module axi_ad9361_rx (
assign adc_dbg_trigger[0] = adc_iqcor_valid_s; assign adc_dbg_trigger[0] = adc_iqcor_valid_s;
assign adc_dbg_trigger[1] = adc_valid; assign adc_dbg_trigger[1] = adc_valid;
assign adc_dbg_data[ 15: 0] = adc_iqcor_data_0_s; assign adc_dbg_data[ 15: 0] = adc_chan_i1;
assign adc_dbg_data[ 31: 16] = adc_iqcor_data_1_s; assign adc_dbg_data[ 31: 16] = adc_chan_q1;
assign adc_dbg_data[ 47: 32] = adc_iqcor_data_2_s; assign adc_dbg_data[ 47: 32] = adc_chan_i2;
assign adc_dbg_data[ 63: 48] = adc_iqcor_data_3_s; assign adc_dbg_data[ 63: 48] = adc_chan_q2;
assign adc_dbg_data[ 64: 64] = adc_iqcor_valid_0_s; assign adc_dbg_data[ 64: 64] = adc_valid_0;
assign adc_dbg_data[ 65: 65] = adc_iqcor_valid_1_s; assign adc_dbg_data[ 65: 65] = adc_valid_1;
assign adc_dbg_data[ 66: 66] = adc_iqcor_valid_2_s; assign adc_dbg_data[ 66: 66] = adc_valid_2;
assign adc_dbg_data[ 67: 67] = adc_iqcor_valid_3_s; assign adc_dbg_data[ 67: 67] = adc_valid_3;
assign adc_dbg_data[ 79: 68] = adc_data_i1; assign adc_dbg_data[ 79: 68] = adc_data_i1;
assign adc_dbg_data[ 91: 80] = adc_data_q1; assign adc_dbg_data[ 91: 80] = adc_data_q1;
assign adc_dbg_data[103: 92] = adc_data_i2; assign adc_dbg_data[103: 92] = adc_data_i2;
@ -277,232 +270,8 @@ module axi_ad9361_rx (
// adc channels - dma interface // adc channels - dma interface
assign adc_dwr = adc_iqcor_valid; assign adc_iqcor_valid_s = adc_valid_0 & adc_valid_1 &
assign adc_dsync = adc_iqcor_sync; adc_valid_2 & adc_valid_3;
assign adc_ddata = adc_iqcor_data;
assign adc_iqcor_valid_s = adc_iqcor_valid_0_s & adc_iqcor_valid_1_s &
adc_iqcor_valid_2_s & adc_iqcor_valid_3_s;
always @(posedge adc_clk) begin
if (adc_iqcor_valid_s == 1'b1) begin
adc_iqcor_valid_3 <= adc_iqcor_data_cnt[0] | adc_iqcor_data_cnt[1];
adc_iqcor_sync_3 <= adc_iqcor_data_cnt[0] & ~adc_iqcor_data_cnt[1];
adc_iqcor_data_3_1110[47:32] <= adc_iqcor_data_3_s;
adc_iqcor_data_3_1110[31:16] <= adc_iqcor_data_2_s;
adc_iqcor_data_3_1110[15: 0] <= adc_iqcor_data_1_s;
adc_iqcor_data_3_1101[47:32] <= adc_iqcor_data_3_s;
adc_iqcor_data_3_1101[31:16] <= adc_iqcor_data_2_s;
adc_iqcor_data_3_1101[15: 0] <= adc_iqcor_data_0_s;
adc_iqcor_data_3_1011[47:32] <= adc_iqcor_data_3_s;
adc_iqcor_data_3_1011[31:16] <= adc_iqcor_data_1_s;
adc_iqcor_data_3_1011[15: 0] <= adc_iqcor_data_0_s;
adc_iqcor_data_3_0111[47:32] <= adc_iqcor_data_2_s;
adc_iqcor_data_3_0111[31:16] <= adc_iqcor_data_1_s;
adc_iqcor_data_3_0111[15: 0] <= adc_iqcor_data_0_s;
case (adc_iqcor_data_cnt)
2'b11: begin
adc_iqcor_data_1110[63:48] <= adc_iqcor_data_3_s;
adc_iqcor_data_1110[47:32] <= adc_iqcor_data_2_s;
adc_iqcor_data_1110[31:16] <= adc_iqcor_data_1_s;
adc_iqcor_data_1110[15: 0] <= adc_iqcor_data_3_1110[47:32];
adc_iqcor_data_1101[63:48] <= adc_iqcor_data_3_s;
adc_iqcor_data_1101[47:32] <= adc_iqcor_data_2_s;
adc_iqcor_data_1101[31:16] <= adc_iqcor_data_0_s;
adc_iqcor_data_1101[15: 0] <= adc_iqcor_data_3_1101[47:32];
adc_iqcor_data_1011[63:48] <= adc_iqcor_data_3_s;
adc_iqcor_data_1011[47:32] <= adc_iqcor_data_1_s;
adc_iqcor_data_1011[31:16] <= adc_iqcor_data_0_s;
adc_iqcor_data_1011[15: 0] <= adc_iqcor_data_3_1011[47:32];
adc_iqcor_data_0111[63:48] <= adc_iqcor_data_2_s;
adc_iqcor_data_0111[47:32] <= adc_iqcor_data_1_s;
adc_iqcor_data_0111[31:16] <= adc_iqcor_data_0_s;
adc_iqcor_data_0111[15: 0] <= adc_iqcor_data_3_0111[47:32];
end
2'b10: begin
adc_iqcor_data_1110[63:48] <= adc_iqcor_data_2_s;
adc_iqcor_data_1110[47:32] <= adc_iqcor_data_1_s;
adc_iqcor_data_1110[31:16] <= adc_iqcor_data_3_1110[47:32];
adc_iqcor_data_1110[15: 0] <= adc_iqcor_data_3_1110[31:16];
adc_iqcor_data_1101[63:48] <= adc_iqcor_data_2_s;
adc_iqcor_data_1101[47:32] <= adc_iqcor_data_0_s;
adc_iqcor_data_1101[31:16] <= adc_iqcor_data_3_1101[47:32];
adc_iqcor_data_1101[15: 0] <= adc_iqcor_data_3_1101[31:16];
adc_iqcor_data_1011[63:48] <= adc_iqcor_data_1_s;
adc_iqcor_data_1011[47:32] <= adc_iqcor_data_0_s;
adc_iqcor_data_1011[31:16] <= adc_iqcor_data_3_1011[47:32];
adc_iqcor_data_1011[15: 0] <= adc_iqcor_data_3_1011[31:16];
adc_iqcor_data_0111[63:48] <= adc_iqcor_data_1_s;
adc_iqcor_data_0111[47:32] <= adc_iqcor_data_0_s;
adc_iqcor_data_0111[31:16] <= adc_iqcor_data_3_0111[47:32];
adc_iqcor_data_0111[15: 0] <= adc_iqcor_data_3_0111[31:16];
end
2'b01: begin
adc_iqcor_data_1110[63:48] <= adc_iqcor_data_1_s;
adc_iqcor_data_1110[47:32] <= adc_iqcor_data_3_1110[47:32];
adc_iqcor_data_1110[31:16] <= adc_iqcor_data_3_1110[31:16];
adc_iqcor_data_1110[15: 0] <= adc_iqcor_data_3_1110[15: 0];
adc_iqcor_data_1101[63:48] <= adc_iqcor_data_0_s;
adc_iqcor_data_1101[47:32] <= adc_iqcor_data_3_1101[47:32];
adc_iqcor_data_1101[31:16] <= adc_iqcor_data_3_1101[31:16];
adc_iqcor_data_1101[15: 0] <= adc_iqcor_data_3_1101[15: 0];
adc_iqcor_data_1011[63:48] <= adc_iqcor_data_0_s;
adc_iqcor_data_1011[47:32] <= adc_iqcor_data_3_1011[47:32];
adc_iqcor_data_1011[31:16] <= adc_iqcor_data_3_1011[31:16];
adc_iqcor_data_1011[15: 0] <= adc_iqcor_data_3_1011[15: 0];
adc_iqcor_data_0111[63:48] <= adc_iqcor_data_0_s;
adc_iqcor_data_0111[47:32] <= adc_iqcor_data_3_0111[47:32];
adc_iqcor_data_0111[31:16] <= adc_iqcor_data_3_0111[31:16];
adc_iqcor_data_0111[15: 0] <= adc_iqcor_data_3_0111[15: 0];
end
default:begin
adc_iqcor_data_1110[63:48] <= 16'hdead;
adc_iqcor_data_1110[47:32] <= 16'hdead;
adc_iqcor_data_1110[31:16] <= 16'hdead;
adc_iqcor_data_1110[15: 0] <= 16'hdead;
adc_iqcor_data_1101[63:48] <= 16'hdead;
adc_iqcor_data_1101[47:32] <= 16'hdead;
adc_iqcor_data_1101[31:16] <= 16'hdead;
adc_iqcor_data_1101[15: 0] <= 16'hdead;
adc_iqcor_data_1011[63:48] <= 16'hdead;
adc_iqcor_data_1011[47:32] <= 16'hdead;
adc_iqcor_data_1011[31:16] <= 16'hdead;
adc_iqcor_data_1011[15: 0] <= 16'hdead;
adc_iqcor_data_0111[63:48] <= 16'hdead;
adc_iqcor_data_0111[47:32] <= 16'hdead;
adc_iqcor_data_0111[31:16] <= 16'hdead;
adc_iqcor_data_0111[15: 0] <= 16'hdead;
end
endcase
end
end
always @(posedge adc_clk) begin
if (adc_iqcor_valid_s == 1'b1) begin
case ({adc_enable_3_s, adc_enable_2_s, adc_enable_1_s, adc_enable_0_s})
4'b1111: begin
adc_iqcor_valid <= 1'b1;
adc_iqcor_sync <= 1'b1;
adc_iqcor_data[63:48] <= adc_iqcor_data_3_s;
adc_iqcor_data[47:32] <= adc_iqcor_data_2_s;
adc_iqcor_data[31:16] <= adc_iqcor_data_1_s;
adc_iqcor_data[15: 0] <= adc_iqcor_data_0_s;
end
4'b1110: begin
adc_iqcor_sync <= adc_iqcor_sync_3;
adc_iqcor_valid <= adc_iqcor_valid_3;
adc_iqcor_data <= adc_iqcor_data_1110;
end
4'b1101: begin
adc_iqcor_sync <= adc_iqcor_sync_3;
adc_iqcor_valid <= adc_iqcor_valid_3;
adc_iqcor_data <= adc_iqcor_data_1101;
end
4'b1100: begin
adc_iqcor_sync <= 1'b1;
adc_iqcor_valid <= adc_iqcor_data_cnt[0];
adc_iqcor_data[63:48] <= adc_iqcor_data_3_s;
adc_iqcor_data[47:32] <= adc_iqcor_data_2_s;
adc_iqcor_data[31:16] <= adc_iqcor_data[63:48];
adc_iqcor_data[15: 0] <= adc_iqcor_data[47:32];
end
4'b1011: begin
adc_iqcor_sync <= adc_iqcor_sync_3;
adc_iqcor_valid <= adc_iqcor_valid_3;
adc_iqcor_data <= adc_iqcor_data_1011;
end
4'b1010: begin
adc_iqcor_sync <= 1'b1;
adc_iqcor_valid <= adc_iqcor_data_cnt[0];
adc_iqcor_data[63:48] <= adc_iqcor_data_3_s;
adc_iqcor_data[47:32] <= adc_iqcor_data_1_s;
adc_iqcor_data[31:16] <= adc_iqcor_data[63:48];
adc_iqcor_data[15: 0] <= adc_iqcor_data[47:32];
end
4'b1001: begin
adc_iqcor_sync <= 1'b1;
adc_iqcor_valid <= adc_iqcor_data_cnt[0];
adc_iqcor_data[63:48] <= adc_iqcor_data_3_s;
adc_iqcor_data[47:32] <= adc_iqcor_data_0_s;
adc_iqcor_data[31:16] <= adc_iqcor_data[63:48];
adc_iqcor_data[15: 0] <= adc_iqcor_data[47:32];
end
4'b1000: begin
adc_iqcor_sync <= 1'b1;
adc_iqcor_valid <= adc_iqcor_data_cnt[1] & adc_iqcor_data_cnt[0];
adc_iqcor_data[63:48] <= adc_iqcor_data_3_s;
adc_iqcor_data[47:32] <= adc_iqcor_data[63:48];
adc_iqcor_data[31:16] <= adc_iqcor_data[47:32];
adc_iqcor_data[15: 0] <= adc_iqcor_data[31:16];
end
4'b0111: begin
adc_iqcor_sync <= adc_iqcor_sync_3;
adc_iqcor_valid <= adc_iqcor_valid_3;
adc_iqcor_data <= adc_iqcor_data_0111;
end
4'b0110: begin
adc_iqcor_sync <= 1'b1;
adc_iqcor_valid <= adc_iqcor_data_cnt[0];
adc_iqcor_data[63:48] <= adc_iqcor_data_2_s;
adc_iqcor_data[47:32] <= adc_iqcor_data_1_s;
adc_iqcor_data[31:16] <= adc_iqcor_data[63:48];
adc_iqcor_data[15: 0] <= adc_iqcor_data[47:32];
end
4'b0101: begin
adc_iqcor_sync <= 1'b1;
adc_iqcor_valid <= adc_iqcor_data_cnt[0];
adc_iqcor_data[63:48] <= adc_iqcor_data_2_s;
adc_iqcor_data[47:32] <= adc_iqcor_data_0_s;
adc_iqcor_data[31:16] <= adc_iqcor_data[63:48];
adc_iqcor_data[15: 0] <= adc_iqcor_data[47:32];
end
4'b0100: begin
adc_iqcor_sync <= 1'b1;
adc_iqcor_valid <= adc_iqcor_data_cnt[1] & adc_iqcor_data_cnt[0];
adc_iqcor_data[63:48] <= adc_iqcor_data_2_s;
adc_iqcor_data[47:32] <= adc_iqcor_data[63:48];
adc_iqcor_data[31:16] <= adc_iqcor_data[47:32];
adc_iqcor_data[15: 0] <= adc_iqcor_data[31:16];
end
4'b0011: begin
adc_iqcor_sync <= 1'b1;
adc_iqcor_valid <= adc_iqcor_data_cnt[0];
adc_iqcor_data[63:48] <= adc_iqcor_data_1_s;
adc_iqcor_data[47:32] <= adc_iqcor_data_0_s;
adc_iqcor_data[31:16] <= adc_iqcor_data[63:48];
adc_iqcor_data[15: 0] <= adc_iqcor_data[47:32];
end
4'b0010: begin
adc_iqcor_sync <= 1'b1;
adc_iqcor_valid <= adc_iqcor_data_cnt[1] & adc_iqcor_data_cnt[0];
adc_iqcor_data[63:48] <= adc_iqcor_data_1_s;
adc_iqcor_data[47:32] <= adc_iqcor_data[63:48];
adc_iqcor_data[31:16] <= adc_iqcor_data[47:32];
adc_iqcor_data[15: 0] <= adc_iqcor_data[31:16];
end
4'b0001: begin
adc_iqcor_sync <= 1'b1;
adc_iqcor_valid <= adc_iqcor_data_cnt[1] & adc_iqcor_data_cnt[0];
adc_iqcor_data[63:48] <= adc_iqcor_data_0_s;
adc_iqcor_data[47:32] <= adc_iqcor_data[63:48];
adc_iqcor_data[31:16] <= adc_iqcor_data[47:32];
adc_iqcor_data[15: 0] <= adc_iqcor_data[31:16];
end
default: begin
adc_iqcor_valid <= 1'b1;
adc_iqcor_data[63:48] <= 16'hdead;
adc_iqcor_data[47:32] <= 16'hdead;
adc_iqcor_data[31:16] <= 16'hdead;
adc_iqcor_data[15: 0] <= 16'hdead;
end
endcase
adc_iqcor_data_cnt <= adc_iqcor_data_cnt + 1'b1;
end else begin
adc_iqcor_valid <= 1'b0;
adc_iqcor_data <= adc_iqcor_data;
adc_iqcor_data_cnt <= adc_iqcor_data_cnt;
end
end
// processor read interface // processor read interface
@ -548,9 +317,9 @@ module axi_ad9361_rx (
.adc_dcfilter_data_in (adc_dcfilter_data_out_1_s), .adc_dcfilter_data_in (adc_dcfilter_data_out_1_s),
.adc_pn_oos_in (1'd0), .adc_pn_oos_in (1'd0),
.adc_pn_err_in (1'd0), .adc_pn_err_in (1'd0),
.adc_iqcor_valid (adc_iqcor_valid_0_s), .adc_iqcor_valid (adc_valid_0),
.adc_iqcor_data (adc_iqcor_data_0_s), .adc_iqcor_data (adc_chan_i1),
.adc_enable (adc_enable_0_s), .adc_enable (adc_enable_0),
.adc_lb_enb (adc_lb_enb_i1), .adc_lb_enb (adc_lb_enb_i1),
.up_adc_pn_err (up_adc_pn_err_0_s), .up_adc_pn_err (up_adc_pn_err_0_s),
.up_adc_pn_oos (up_adc_pn_oos_0_s), .up_adc_pn_oos (up_adc_pn_oos_0_s),
@ -585,9 +354,9 @@ module axi_ad9361_rx (
.adc_dcfilter_data_in (adc_dcfilter_data_out_0_s), .adc_dcfilter_data_in (adc_dcfilter_data_out_0_s),
.adc_pn_oos_in (adc_pn_oos_out_0_s), .adc_pn_oos_in (adc_pn_oos_out_0_s),
.adc_pn_err_in (adc_pn_err_out_0_s), .adc_pn_err_in (adc_pn_err_out_0_s),
.adc_iqcor_valid (adc_iqcor_valid_1_s), .adc_iqcor_valid (adc_valid_1),
.adc_iqcor_data (adc_iqcor_data_1_s), .adc_iqcor_data (adc_chan_q1),
.adc_enable (adc_enable_1_s), .adc_enable (adc_enable_1),
.adc_lb_enb (adc_lb_enb_q1), .adc_lb_enb (adc_lb_enb_q1),
.up_adc_pn_err (up_adc_pn_err_1_s), .up_adc_pn_err (up_adc_pn_err_1_s),
.up_adc_pn_oos (up_adc_pn_oos_1_s), .up_adc_pn_oos (up_adc_pn_oos_1_s),
@ -622,9 +391,9 @@ module axi_ad9361_rx (
.adc_dcfilter_data_in (adc_dcfilter_data_out_3_s), .adc_dcfilter_data_in (adc_dcfilter_data_out_3_s),
.adc_pn_oos_in (1'd0), .adc_pn_oos_in (1'd0),
.adc_pn_err_in (1'd0), .adc_pn_err_in (1'd0),
.adc_iqcor_valid (adc_iqcor_valid_2_s), .adc_iqcor_valid (adc_valid_2),
.adc_iqcor_data (adc_iqcor_data_2_s), .adc_iqcor_data (adc_chan_i2),
.adc_enable (adc_enable_2_s), .adc_enable (adc_enable_2),
.adc_lb_enb (adc_lb_enb_i2), .adc_lb_enb (adc_lb_enb_i2),
.up_adc_pn_err (up_adc_pn_err_2_s), .up_adc_pn_err (up_adc_pn_err_2_s),
.up_adc_pn_oos (up_adc_pn_oos_2_s), .up_adc_pn_oos (up_adc_pn_oos_2_s),
@ -659,9 +428,9 @@ module axi_ad9361_rx (
.adc_dcfilter_data_in (adc_dcfilter_data_out_2_s), .adc_dcfilter_data_in (adc_dcfilter_data_out_2_s),
.adc_pn_oos_in (adc_pn_oos_out_2_s), .adc_pn_oos_in (adc_pn_oos_out_2_s),
.adc_pn_err_in (adc_pn_err_out_2_s), .adc_pn_err_in (adc_pn_err_out_2_s),
.adc_iqcor_valid (adc_iqcor_valid_3_s), .adc_iqcor_valid (adc_valid_3),
.adc_iqcor_data (adc_iqcor_data_3_s), .adc_iqcor_data (adc_chan_q2),
.adc_enable (adc_enable_3_s), .adc_enable (adc_enable_3),
.adc_lb_enb (adc_lb_enb_q2), .adc_lb_enb (adc_lb_enb_q2),
.up_adc_pn_err (up_adc_pn_err_3_s), .up_adc_pn_err (up_adc_pn_err_3_s),
.up_adc_pn_oos (up_adc_pn_oos_3_s), .up_adc_pn_oos (up_adc_pn_oos_3_s),

39
library/axi_ad9361/axi_ad9361_tx.v
View File

@ -66,8 +66,18 @@ module axi_ad9361_tx (
// dma interface // dma interface
dac_drd, dac_data_0,
dac_ddata, dac_enable_0,
dac_drd_0,
dac_data_1,
dac_enable_1,
dac_drd_1,
dac_data_2,
dac_enable_2,
dac_drd_2,
dac_data_3,
dac_enable_3,
dac_drd_3,
dac_dovf, dac_dovf,
dac_dunf, dac_dunf,
@ -112,8 +122,18 @@ module axi_ad9361_tx (
// dma interface // dma interface
output dac_drd; input [15:0] dac_data_0;
input [63:0] dac_ddata; output dac_enable_0;
output dac_drd_0;
input [15:0] dac_data_1;
output dac_enable_1;
output dac_drd_1;
input [15:0] dac_data_2;
output dac_enable_2;
output dac_drd_2;
input [15:0] dac_data_3;
output dac_enable_3;
output dac_drd_3;
input dac_dovf; input dac_dovf;
input dac_dunf; input dac_dunf;
@ -177,6 +197,15 @@ module axi_ad9361_tx (
// master/slave // master/slave
assign dac_enable_s = (PCORE_ID == 0) ? dac_enable_out : dac_enable_in; assign dac_enable_s = (PCORE_ID == 0) ? dac_enable_out : dac_enable_in;
assign dac_drd_0 = dac_drd;
assign dac_drd_1 = dac_drd;
assign dac_drd_2 = dac_drd;
assign dac_drd_3 = dac_drd;
assign dac_enable_0 = dac_enable_s;
assign dac_enable_1 = dac_enable_s;
assign dac_enable_2 = dac_enable_s;
assign dac_enable_3 = dac_enable_s;
always @(posedge dac_clk) begin always @(posedge dac_clk) begin
dac_enable <= dac_enable_s; dac_enable <= dac_enable_s;
@ -210,7 +239,7 @@ module axi_ad9361_tx (
dac_drd <= dac_dds_data_enable & dac_enable; dac_drd <= dac_dds_data_enable & dac_enable;
end end
if (dac_drd == 1'b1) begin if (dac_drd == 1'b1) begin
dac_dma_data <= dac_ddata; dac_dma_data <= {dac_data_3, dac_data_2, dac_data_1, dac_data_0};
end end
if (dac_dds_data_enable == 1'b1) begin if (dac_dds_data_enable == 1'b1) begin
if (dac_r1_mode == 1'b0) begin if (dac_r1_mode == 1'b0) begin

332
library/util_adc_pack/util_adc_pack.v Executable file
View File

@ -0,0 +1,332 @@
// ***************************************************************************
// ***************************************************************************
// Copyright 2014(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module util_adc_pack (
clk,
chan_data_0,
chan_data_1,
chan_data_2,
chan_data_3,
chan_enable_0,
chan_enable_1,
chan_enable_2,
chan_enable_3,
chan_valid_0,
chan_valid_1,
chan_valid_2,
chan_valid_3,
ddata,
dvalid,
dsync
);
// common clock
input clk;
input [15:0] chan_data_0;
input [15:0] chan_data_1;
input [15:0] chan_data_2;
input [15:0] chan_data_3;
input chan_enable_0;
input chan_enable_1;
input chan_enable_2;
input chan_enable_3;
input chan_valid_0;
input chan_valid_1;
input chan_valid_2;
input chan_valid_3;
output [63:0] ddata;
output dvalid;
output dsync;
reg [47:0] adc_data_3_1110 = 'd0;
reg [47:0] adc_data_3_1101 = 'd0;
reg [47:0] adc_data_3_1011 = 'd0;
reg [47:0] adc_data_3_0111 = 'd0;
reg adc_iqcor_valid = 'd0;
reg adc_iqcor_valid_3 = 'd0;
reg adc_iqcor_sync = 'd0;
reg adc_iqcor_sync_3 = 'd0;
reg [63:0] adc_data = 'd0;
reg [63:0] adc_data_1110 = 'd0;
reg [63:0] adc_data_1101 = 'd0;
reg [63:0] adc_data_1011 = 'd0;
reg [63:0] adc_data_0111 = 'd0;
reg [ 1:0] adc_data_cnt = 'd0;
wire valid;
assign dsync = adc_iqcor_sync;
assign dvalid = adc_iqcor_valid;
assign ddata = adc_data;
assign valid = chan_valid_0 & chan_valid_1 & chan_valid_2 & chan_valid_3;
always @(posedge clk) begin
if (valid == 1'b1) begin
adc_iqcor_valid_3 <= adc_data_cnt[0] | adc_data_cnt[1];
adc_iqcor_sync_3 <= adc_data_cnt[0] & ~adc_data_cnt[1];
adc_data_3_1110[47:32] <= chan_data_3;
adc_data_3_1110[31:16] <= chan_data_2;
adc_data_3_1110[15: 0] <= chan_data_1;
adc_data_3_1101[47:32] <= chan_data_3;
adc_data_3_1101[31:16] <= chan_data_2;
adc_data_3_1101[15: 0] <= chan_data_0;
adc_data_3_1011[47:32] <= chan_data_3;
adc_data_3_1011[31:16] <= chan_data_1;
adc_data_3_1011[15: 0] <= chan_data_0;
adc_data_3_0111[47:32] <= chan_data_2;
adc_data_3_0111[31:16] <= chan_data_1;
adc_data_3_0111[15: 0] <= chan_data_0;
case (adc_data_cnt)
2'b11: begin
adc_data_1110[63:48] <= chan_data_3;
adc_data_1110[47:32] <= chan_data_2;
adc_data_1110[31:16] <= chan_data_1;
adc_data_1110[15: 0] <= adc_data_3_1110[47:32];
adc_data_1101[63:48] <= chan_data_3;
adc_data_1101[47:32] <= chan_data_2;
adc_data_1101[31:16] <= chan_data_0;
adc_data_1101[15: 0] <= adc_data_3_1101[47:32];
adc_data_1011[63:48] <= chan_data_3;
adc_data_1011[47:32] <= chan_data_1;
adc_data_1011[31:16] <= chan_data_0;
adc_data_1011[15: 0] <= adc_data_3_1011[47:32];
adc_data_0111[63:48] <= chan_data_2;
adc_data_0111[47:32] <= chan_data_1;
adc_data_0111[31:16] <= chan_data_0;
adc_data_0111[15: 0] <= adc_data_3_0111[47:32];
end
2'b10: begin
adc_data_1110[63:48] <= chan_data_2;
adc_data_1110[47:32] <= chan_data_1;
adc_data_1110[31:16] <= adc_data_3_1110[47:32];
adc_data_1110[15: 0] <= adc_data_3_1110[31:16];
adc_data_1101[63:48] <= chan_data_2;
adc_data_1101[47:32] <= chan_data_0;
adc_data_1101[31:16] <= adc_data_3_1101[47:32];
adc_data_1101[15: 0] <= adc_data_3_1101[31:16];
adc_data_1011[63:48] <= chan_data_1;
adc_data_1011[47:32] <= chan_data_0;
adc_data_1011[31:16] <= adc_data_3_1011[47:32];
adc_data_1011[15: 0] <= adc_data_3_1011[31:16];
adc_data_0111[63:48] <= chan_data_1;
adc_data_0111[47:32] <= chan_data_0;
adc_data_0111[31:16] <= adc_data_3_0111[47:32];
adc_data_0111[15: 0] <= adc_data_3_0111[31:16];
end
2'b01: begin
adc_data_1110[63:48] <= chan_data_1;
adc_data_1110[47:32] <= adc_data_3_1110[47:32];
adc_data_1110[31:16] <= adc_data_3_1110[31:16];
adc_data_1110[15: 0] <= adc_data_3_1110[15: 0];
adc_data_1101[63:48] <= chan_data_0;
adc_data_1101[47:32] <= adc_data_3_1101[47:32];
adc_data_1101[31:16] <= adc_data_3_1101[31:16];
adc_data_1101[15: 0] <= adc_data_3_1101[15: 0];
adc_data_1011[63:48] <= chan_data_0;
adc_data_1011[47:32] <= adc_data_3_1011[47:32];
adc_data_1011[31:16] <= adc_data_3_1011[31:16];
adc_data_1011[15: 0] <= adc_data_3_1011[15: 0];
adc_data_0111[63:48] <= chan_data_0;
adc_data_0111[47:32] <= adc_data_3_0111[47:32];
adc_data_0111[31:16] <= adc_data_3_0111[31:16];
adc_data_0111[15: 0] <= adc_data_3_0111[15: 0];
end
default:begin
adc_data_1110[63:48] <= 16'hdead;
adc_data_1110[47:32] <= 16'hdead;
adc_data_1110[31:16] <= 16'hdead;
adc_data_1110[15: 0] <= 16'hdead;
adc_data_1101[63:48] <= 16'hdead;
adc_data_1101[47:32] <= 16'hdead;
adc_data_1101[31:16] <= 16'hdead;
adc_data_1101[15: 0] <= 16'hdead;
adc_data_1011[63:48] <= 16'hdead;
adc_data_1011[47:32] <= 16'hdead;
adc_data_1011[31:16] <= 16'hdead;
adc_data_1011[15: 0] <= 16'hdead;
adc_data_0111[63:48] <= 16'hdead;
adc_data_0111[47:32] <= 16'hdead;
adc_data_0111[31:16] <= 16'hdead;
adc_data_0111[15: 0] <= 16'hdead;
end
endcase
end
end
always @(posedge clk) begin
if (valid == 1'b1) begin
case ({chan_enable_3, chan_enable_2, chan_enable_1, chan_enable_0})
4'b1111: begin
adc_iqcor_valid <= 1'b1;
adc_iqcor_sync <= 1'b1;
adc_data[63:48] <= chan_data_3;
adc_data[47:32] <= chan_data_2;
adc_data[31:16] <= chan_data_1;
adc_data[15: 0] <= chan_data_0;
end
4'b1110: begin
adc_iqcor_sync <= adc_iqcor_sync_3;
adc_iqcor_valid <= adc_iqcor_valid_3;
adc_data <= adc_data_1110;
end
4'b1101: begin
adc_iqcor_sync <= adc_iqcor_sync_3;
adc_iqcor_valid <= adc_iqcor_valid_3;
adc_data <= adc_data_1101;
end
4'b1100: begin
adc_iqcor_sync <= 1'b1;
adc_iqcor_valid <= adc_data_cnt[0];
adc_data[63:48] <= chan_data_3;
adc_data[47:32] <= chan_data_2;
adc_data[31:16] <= adc_data[63:48];
adc_data[15: 0] <= adc_data[47:32];
end
4'b1011: begin
adc_iqcor_sync <= adc_iqcor_sync_3;
adc_iqcor_valid <= adc_iqcor_valid_3;
adc_data <= adc_data_1011;
end
4'b1010: begin
adc_iqcor_sync <= 1'b1;
adc_iqcor_valid <= adc_data_cnt[0];
adc_data[63:48] <= chan_data_3;
adc_data[47:32] <= chan_data_1;
adc_data[31:16] <= adc_data[63:48];
adc_data[15: 0] <= adc_data[47:32];
end
4'b1001: begin
adc_iqcor_sync <= 1'b1;
adc_iqcor_valid <= adc_data_cnt[0];
adc_data[63:48] <= chan_data_3;
adc_data[47:32] <= chan_data_0;
adc_data[31:16] <= adc_data[63:48];
adc_data[15: 0] <= adc_data[47:32];
end
4'b1000: begin
adc_iqcor_sync <= 1'b1;
adc_iqcor_valid <= adc_data_cnt[1] & adc_data_cnt[0];
adc_data[63:48] <= chan_data_3;
adc_data[47:32] <= adc_data[63:48];
adc_data[31:16] <= adc_data[47:32];
adc_data[15: 0] <= adc_data[31:16];
end
4'b0111: begin
adc_iqcor_sync <= adc_iqcor_sync_3;
adc_iqcor_valid <= adc_iqcor_valid_3;
adc_data <= adc_data_0111;
end
4'b0110: begin
adc_iqcor_sync <= 1'b1;
adc_iqcor_valid <= adc_data_cnt[0];
adc_data[63:48] <= chan_data_2;
adc_data[47:32] <= chan_data_1;
adc_data[31:16] <= adc_data[63:48];
adc_data[15: 0] <= adc_data[47:32];
end
4'b0101: begin
adc_iqcor_sync <= 1'b1;
adc_iqcor_valid <= adc_data_cnt[0];
adc_data[63:48] <= chan_data_2;
adc_data[47:32] <= chan_data_0;
adc_data[31:16] <= adc_data[63:48];
adc_data[15: 0] <= adc_data[47:32];
end
4'b0100: begin
adc_iqcor_sync <= 1'b1;
adc_iqcor_valid <= adc_data_cnt[1] & adc_data_cnt[0];
adc_data[63:48] <= chan_data_2;
adc_data[47:32] <= adc_data[63:48];
adc_data[31:16] <= adc_data[47:32];
adc_data[15: 0] <= adc_data[31:16];
end
4'b0011: begin
adc_iqcor_sync <= 1'b1;
adc_iqcor_valid <= adc_data_cnt[0];
adc_data[63:48] <= chan_data_1;
adc_data[47:32] <= chan_data_0;
adc_data[31:16] <= adc_data[63:48];
adc_data[15: 0] <= adc_data[47:32];
end
4'b0010: begin
adc_iqcor_sync <= 1'b1;
adc_iqcor_valid <= adc_data_cnt[1] & adc_data_cnt[0];
adc_data[63:48] <= chan_data_1;
adc_data[47:32] <= adc_data[63:48];
adc_data[31:16] <= adc_data[47:32];
adc_data[15: 0] <= adc_data[31:16];
end
4'b0001: begin
adc_iqcor_sync <= 1'b1;
adc_iqcor_valid <= adc_data_cnt[1] & adc_data_cnt[0];
adc_data[63:48] <= chan_data_0;
adc_data[47:32] <= adc_data[63:48];
adc_data[31:16] <= adc_data[47:32];
adc_data[15: 0] <= adc_data[31:16];
end
default: begin
adc_iqcor_valid <= 1'b1;
adc_data[63:48] <= 16'hdead;
adc_data[47:32] <= 16'hdead;
adc_data[31:16] <= 16'hdead;
adc_data[15: 0] <= 16'hdead;
end
endcase
adc_data_cnt <= adc_data_cnt + 1'b1;
end else begin
adc_iqcor_valid <= 1'b0;
adc_data <= adc_data;
adc_data_cnt <= adc_data_cnt;
end
end
endmodule
// ***************************************************************************
// ***************************************************************************

23
library/util_adc_pack/util_adc_pack_ip.tcl Executable file
View File

@ -0,0 +1,23 @@
# ip
source ../scripts/adi_env.tcl
source $ad_hdl_dir/library/scripts/adi_ip.tcl
adi_ip_create util_adc_pack
adi_ip_files util_adc_pack [list \
"util_adc_pack.v" ]
adi_ip_properties_lite util_adc_pack
ipx::remove_bus_interface {s} [ipx::current_core]
ipx::remove_bus_interface {m} [ipx::current_core]
ipx::remove_bus_interface {fifo} [ipx::current_core]
ipx::remove_bus_interface {signal_clock} [ipx::current_core]
ipx::remove_memory_map {m} [ipx::current_core]
ipx::remove_address_space {s} [ipx::current_core]
ipx::remove_address_space {fifo} [ipx::current_core]
ipx::save_core [ipx::current_core]

68
library/util_dac_unpack/util_dac_unpack.v Executable file
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@ -0,0 +1,68 @@
// ***************************************************************************
// ***************************************************************************
// Copyright 2014(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module util_dac_unpack (
chan_data_0,
chan_data_1,
chan_data_2,
chan_data_3,
dma_data
);
output [15:0] chan_data_0;
output [15:0] chan_data_1;
output [15:0] chan_data_2;
output [15:0] chan_data_3;
input [63:0] dma_data;
assign chan_data_0 = dma_data[15:0 ];
assign chan_data_1 = dma_data[31:16];
assign chan_data_2 = dma_data[47:32];
assign chan_data_3 = dma_data[63:48];
endmodule
// ***************************************************************************
// ***************************************************************************

23
library/util_dac_unpack/util_dac_unpack_ip.tcl Executable file
View File

@ -0,0 +1,23 @@
# ip
source ../scripts/adi_env.tcl
source $ad_hdl_dir/library/scripts/adi_ip.tcl
adi_ip_create util_dac_unpack
adi_ip_files util_dac_unpack [list \
"util_dac_unpack.v" ]
adi_ip_properties_lite util_dac_unpack
ipx::remove_bus_interface {s} [ipx::current_core]
ipx::remove_bus_interface {m} [ipx::current_core]
ipx::remove_bus_interface {fifo} [ipx::current_core]
ipx::remove_bus_interface {signal_clock} [ipx::current_core]
ipx::remove_memory_map {m} [ipx::current_core]
ipx::remove_address_space {s} [ipx::current_core]
ipx::remove_address_space {fifo} [ipx::current_core]
ipx::save_core [ipx::current_core]

40
projects/fmcomms2/common/fmcomms2_bd.tcl
View File

@ -46,6 +46,11 @@
set_property -dict [list CONFIG.C_CLKS_ASYNC_REQ_SRC {1}] $axi_ad9361_dac_dma set_property -dict [list CONFIG.C_CLKS_ASYNC_REQ_SRC {1}] $axi_ad9361_dac_dma
set_property -dict [list CONFIG.C_2D_TRANSFER {0}] $axi_ad9361_dac_dma set_property -dict [list CONFIG.C_2D_TRANSFER {0}] $axi_ad9361_dac_dma
# channel packing for the ADC
set util_adc_pack [create_bd_cell -type ip -vlnv analog.com:user:util_adc_pack:1.0 util_adc_pack]
set util_dac_unpack [create_bd_cell -type ip -vlnv analog.com:user:util_dac_unpack:1.0 util_dac_unpack]
if {$sys_zynq == 1} { if {$sys_zynq == 1} {
set axi_ad9361_dac_dma_interconnect [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_ad9361_dac_dma_interconnect] set axi_ad9361_dac_dma_interconnect [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_ad9361_dac_dma_interconnect]
set_property -dict [list CONFIG.NUM_MI {1}] $axi_ad9361_dac_dma_interconnect set_property -dict [list CONFIG.NUM_MI {1}] $axi_ad9361_dac_dma_interconnect
@ -160,13 +165,32 @@ if {$sys_zynq == 0} {
connect_bd_net -net axi_ad9361_tx_frame_out_n [get_bd_ports tx_frame_out_n] [get_bd_pins axi_ad9361/tx_frame_out_n] connect_bd_net -net axi_ad9361_tx_frame_out_n [get_bd_ports tx_frame_out_n] [get_bd_pins axi_ad9361/tx_frame_out_n]
connect_bd_net -net axi_ad9361_tx_data_out_p [get_bd_ports tx_data_out_p] [get_bd_pins axi_ad9361/tx_data_out_p] connect_bd_net -net axi_ad9361_tx_data_out_p [get_bd_ports tx_data_out_p] [get_bd_pins axi_ad9361/tx_data_out_p]
connect_bd_net -net axi_ad9361_tx_data_out_n [get_bd_ports tx_data_out_n] [get_bd_pins axi_ad9361/tx_data_out_n] connect_bd_net -net axi_ad9361_tx_data_out_n [get_bd_ports tx_data_out_n] [get_bd_pins axi_ad9361/tx_data_out_n]
connect_bd_net -net axi_ad9361_adc_dwr [get_bd_pins axi_ad9361/adc_dwr] [get_bd_pins axi_ad9361_adc_dma/fifo_wr_en]
connect_bd_net -net axi_ad9361_adc_dsync [get_bd_pins axi_ad9361/adc_dsync] [get_bd_pins axi_ad9361_adc_dma/fifo_wr_sync] connect_bd_net -net axi_ad9361_clk [get_bd_pins util_adc_pack/clk]
connect_bd_net -net axi_ad9361_adc_ddata [get_bd_pins axi_ad9361/adc_ddata] [get_bd_pins axi_ad9361_adc_dma/fifo_wr_din] connect_bd_net -net axi_ad9361_adc_valid_0 [get_bd_pins axi_ad9361/adc_valid_0] [get_bd_pins util_adc_pack/chan_valid_0]
connect_bd_net -net axi_ad9361_adc_dovf [get_bd_pins axi_ad9361/adc_dovf] [get_bd_pins axi_ad9361_adc_dma/fifo_wr_overflow] connect_bd_net -net axi_ad9361_adc_valid_1 [get_bd_pins axi_ad9361/adc_valid_1] [get_bd_pins util_adc_pack/chan_valid_1]
connect_bd_net -net axi_ad9361_dac_drd [get_bd_pins axi_ad9361/dac_drd] [get_bd_pins axi_ad9361_dac_dma/fifo_rd_en] connect_bd_net -net axi_ad9361_adc_valid_2 [get_bd_pins axi_ad9361/adc_valid_2] [get_bd_pins util_adc_pack/chan_valid_2]
connect_bd_net -net axi_ad9361_dac_ddata [get_bd_pins axi_ad9361/dac_ddata] [get_bd_pins axi_ad9361_dac_dma/fifo_rd_dout] connect_bd_net -net axi_ad9361_adc_valid_3 [get_bd_pins axi_ad9361/adc_valid_3] [get_bd_pins util_adc_pack/chan_valid_3]
connect_bd_net -net axi_ad9361_dac_dunf [get_bd_pins axi_ad9361/dac_dunf] [get_bd_pins axi_ad9361_dac_dma/fifo_rd_underflow] connect_bd_net -net axi_ad9361_adc_enable_0 [get_bd_pins axi_ad9361/adc_enable_0] [get_bd_pins util_adc_pack/chan_enable_0]
connect_bd_net -net axi_ad9361_adc_enable_1 [get_bd_pins axi_ad9361/adc_enable_1] [get_bd_pins util_adc_pack/chan_enable_1]
connect_bd_net -net axi_ad9361_adc_enable_2 [get_bd_pins axi_ad9361/adc_enable_2] [get_bd_pins util_adc_pack/chan_enable_2]
connect_bd_net -net axi_ad9361_adc_enable_3 [get_bd_pins axi_ad9361/adc_enable_3] [get_bd_pins util_adc_pack/chan_enable_3]
connect_bd_net -net axi_ad9361_adc_chan_i1 [get_bd_pins axi_ad9361/adc_chan_i1] [get_bd_pins util_adc_pack/chan_data_0]
connect_bd_net -net axi_ad9361_adc_chan_q1 [get_bd_pins axi_ad9361/adc_chan_q1] [get_bd_pins util_adc_pack/chan_data_1]
connect_bd_net -net axi_ad9361_adc_chan_i2 [get_bd_pins axi_ad9361/adc_chan_i2] [get_bd_pins util_adc_pack/chan_data_2]
connect_bd_net -net axi_ad9361_adc_chan_q2 [get_bd_pins axi_ad9361/adc_chan_q2] [get_bd_pins util_adc_pack/chan_data_3]
connect_bd_net -net util_adc_pack_dvalid [get_bd_pins util_adc_pack/dvalid] [get_bd_pins axi_ad9361_adc_dma/fifo_wr_en]
connect_bd_net -net util_adc_pack_dsync [get_bd_pins util_adc_pack/dsync] [get_bd_pins axi_ad9361_adc_dma/fifo_wr_sync]
connect_bd_net -net util_adc_pack_ddata [get_bd_pins util_adc_pack/ddata] [get_bd_pins axi_ad9361_adc_dma/fifo_wr_din]
connect_bd_net -net axi_ad9361_adc_dovf [get_bd_pins axi_ad9361/adc_dovf] [get_bd_pins axi_ad9361_adc_dma/fifo_wr_overflow]
connect_bd_net -net axi_ad9361_dac_data_0 [get_bd_pins util_dac_unpack/chan_data_0] [get_bd_pins axi_ad9361/dac_data_0]
connect_bd_net -net axi_ad9361_dac_data_1 [get_bd_pins util_dac_unpack/chan_data_1] [get_bd_pins axi_ad9361/dac_data_1]
connect_bd_net -net axi_ad9361_dac_data_2 [get_bd_pins util_dac_unpack/chan_data_2] [get_bd_pins axi_ad9361/dac_data_2]
connect_bd_net -net axi_ad9361_dac_data_3 [get_bd_pins util_dac_unpack/chan_data_3] [get_bd_pins axi_ad9361/dac_data_3]
connect_bd_net -net fifo_data [get_bd_pins util_dac_unpack/dma_data] [get_bd_pins axi_ad9361_dac_dma/fifo_rd_dout]
connect_bd_net -net axi_ad9361_dac_drd [get_bd_pins axi_ad9361/dac_drd_0] [get_bd_pins axi_ad9361_dac_dma/fifo_rd_en]
connect_bd_net -net axi_ad9361_dac_dunf [get_bd_pins axi_ad9361/dac_dunf] [get_bd_pins axi_ad9361_dac_dma/fifo_rd_underflow]
if {$sys_zynq == 0} { if {$sys_zynq == 0} {
connect_bd_net -net axi_ad9361_adc_dma_irq [get_bd_pins axi_ad9361_adc_dma/irq] [get_bd_pins sys_concat_intc/In5] connect_bd_net -net axi_ad9361_adc_dma_irq [get_bd_pins axi_ad9361_adc_dma/irq] [get_bd_pins sys_concat_intc/In5]
@ -264,7 +288,7 @@ if {$sys_zynq == 0} {
set_property -dict [list CONFIG.C_PROBE1_WIDTH {48}] $ila_adc set_property -dict [list CONFIG.C_PROBE1_WIDTH {48}] $ila_adc
set_property -dict [list CONFIG.C_TRIGIN_EN {false}] $ila_adc set_property -dict [list CONFIG.C_TRIGIN_EN {false}] $ila_adc
connect_bd_net -net axi_ad9361_clk [get_bd_pins ila_adc/clk] connect_bd_net -net axi_ad9361_clk [get_bd_pins ila_adc/clk]
connect_bd_net -net axi_ad9361_adc_mon_valid [get_bd_pins axi_ad9361/adc_mon_valid] [get_bd_pins ila_adc/probe0] connect_bd_net -net axi_ad9361_adc_mon_valid [get_bd_pins axi_ad9361/adc_mon_valid] [get_bd_pins ila_adc/probe0]
connect_bd_net -net axi_ad9361_adc_mon_data [get_bd_pins axi_ad9361/adc_mon_data] [get_bd_pins ila_adc/probe1] connect_bd_net -net axi_ad9361_adc_mon_data [get_bd_pins axi_ad9361/adc_mon_data] [get_bd_pins ila_adc/probe1]