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adi_ip.tcl: adi_ip_constraints: Add support for VHDL projects 

Match both xilinx_verilogsynthesis and xilinx_vhdlsynthesis when getting the
file group.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
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Lars-Peter Clausen 2015-04-16 11:26:09 +02:00
parent 7c97e192f2
commit bfd84edc46
1 changed files with 1 additions and 1 deletions
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2
library/scripts/adi_ip.tcl
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@ -47,7 +47,7 @@ proc adi_ip_files {ip_name ip_files} {
proc adi_ip_constraints {ip_name ip_constr_files {processing_order early}} {
set proj_filegroup [ipx::get_file_groups xilinx_verilogsynthesis -of_objects [ipx::current_core]]
set proj_filegroup [ipx::get_file_groups xilinx_v*synthesis -of_objects [ipx::current_core]]
set f [ipx::add_file $ip_constr_files $proj_filegroup]
set_property -dict [list \
type xdc \