From c00633d1acb8afa8f5281f78e284f50f33d154f7 Mon Sep 17 00:00:00 2001 From: Istvan Csomortani Date: Mon, 30 Mar 2015 15:23:26 +0300 Subject: [PATCH] adv7511_ac701: Update project and common files to the new framework. --- projects/adv7511/ac701/system_bd.tcl | 4 +- projects/adv7511/ac701/system_constr.xdc | 36 ++ projects/adv7511/ac701/system_project.tcl | 8 +- projects/adv7511/ac701/system_top.v | 69 ++- projects/common/ac701/ac701_system_bd.tcl | 516 ++++++------------ projects/common/ac701/ac701_system_constr.xdc | 60 +- 6 files changed, 238 insertions(+), 455 deletions(-) create mode 100644 projects/adv7511/ac701/system_constr.xdc diff --git a/projects/adv7511/ac701/system_bd.tcl b/projects/adv7511/ac701/system_bd.tcl index 60356edce..ab4519c1d 100644 --- a/projects/adv7511/ac701/system_bd.tcl +++ b/projects/adv7511/ac701/system_bd.tcl @@ -1,6 +1,4 @@ source $ad_hdl_dir/projects/common/ac701/ac701_system_bd.tcl -set_property -dict [list CONFIG.NUM_MI {7}] $axi_cpu_interconnect -set_property -dict [list CONFIG.NUM_SI {8}] $axi_mem_interconnect -set_property -dict [list CONFIG.NUM_MI {1}] $axi_mem_interconnect +source $ad_hdl_dir/projects/adv7511/common/adv7511_bd.tcl diff --git a/projects/adv7511/ac701/system_constr.xdc b/projects/adv7511/ac701/system_constr.xdc new file mode 100644 index 000000000..7bbc40685 --- /dev/null +++ b/projects/adv7511/ac701/system_constr.xdc @@ -0,0 +1,36 @@ + +# hdmi + +set_property -dict {PACKAGE_PIN V21 IOSTANDARD LVCMOS18} [get_ports hdmi_out_clk] +set_property -dict {PACKAGE_PIN AA22 IOSTANDARD LVCMOS18} [get_ports hdmi_hsync] +set_property -dict {PACKAGE_PIN AC26 IOSTANDARD LVCMOS18} [get_ports hdmi_vsync] +set_property -dict {PACKAGE_PIN AB26 IOSTANDARD LVCMOS18} [get_ports hdmi_data_e] +set_property -dict {PACKAGE_PIN AA24 IOSTANDARD LVCMOS18} [get_ports hdmi_data[0]] +set_property -dict {PACKAGE_PIN Y25 IOSTANDARD LVCMOS18} [get_ports hdmi_data[1]] +set_property -dict {PACKAGE_PIN Y26 IOSTANDARD LVCMOS18} [get_ports hdmi_data[2]] +set_property -dict {PACKAGE_PIN V26 IOSTANDARD LVCMOS18} [get_ports hdmi_data[3]] +set_property -dict {PACKAGE_PIN W26 IOSTANDARD LVCMOS18} [get_ports hdmi_data[4]] +set_property -dict {PACKAGE_PIN W25 IOSTANDARD LVCMOS18} [get_ports hdmi_data[5]] +set_property -dict {PACKAGE_PIN W24 IOSTANDARD LVCMOS18} [get_ports hdmi_data[6]] +set_property -dict {PACKAGE_PIN U26 IOSTANDARD LVCMOS18} [get_ports hdmi_data[7]] +set_property -dict {PACKAGE_PIN U25 IOSTANDARD LVCMOS18} [get_ports hdmi_data[8]] +set_property -dict {PACKAGE_PIN V24 IOSTANDARD LVCMOS18} [get_ports hdmi_data[9]] +set_property -dict {PACKAGE_PIN U20 IOSTANDARD LVCMOS18} [get_ports hdmi_data[10]] +set_property -dict {PACKAGE_PIN W23 IOSTANDARD LVCMOS18} [get_ports hdmi_data[11]] +set_property -dict {PACKAGE_PIN W20 IOSTANDARD LVCMOS18} [get_ports hdmi_data[12]] +set_property -dict {PACKAGE_PIN U24 IOSTANDARD LVCMOS18} [get_ports hdmi_data[13]] +set_property -dict {PACKAGE_PIN Y20 IOSTANDARD LVCMOS18} [get_ports hdmi_data[14]] +set_property -dict {PACKAGE_PIN V23 IOSTANDARD LVCMOS18} [get_ports hdmi_data[15]] +set_property -dict {PACKAGE_PIN AA23 IOSTANDARD LVCMOS18} [get_ports hdmi_data[16]] +set_property -dict {PACKAGE_PIN AA25 IOSTANDARD LVCMOS18} [get_ports hdmi_data[17]] +set_property -dict {PACKAGE_PIN AB25 IOSTANDARD LVCMOS18} [get_ports hdmi_data[18]] +set_property -dict {PACKAGE_PIN AC24 IOSTANDARD LVCMOS18} [get_ports hdmi_data[19]] +set_property -dict {PACKAGE_PIN AB24 IOSTANDARD LVCMOS18} [get_ports hdmi_data[20]] +set_property -dict {PACKAGE_PIN Y22 IOSTANDARD LVCMOS18} [get_ports hdmi_data[21]] +set_property -dict {PACKAGE_PIN Y23 IOSTANDARD LVCMOS18} [get_ports hdmi_data[22]] +set_property -dict {PACKAGE_PIN V22 IOSTANDARD LVCMOS18} [get_ports hdmi_data[23]] + +# spdif + +set_property -dict {PACKAGE_PIN Y21 IOSTANDARD LVCMOS18} [get_ports spdif] + diff --git a/projects/adv7511/ac701/system_project.tcl b/projects/adv7511/ac701/system_project.tcl index c5ebc9de3..f678df967 100644 --- a/projects/adv7511/ac701/system_project.tcl +++ b/projects/adv7511/ac701/system_project.tcl @@ -1,14 +1,14 @@ - - source ../../scripts/adi_env.tcl source $ad_hdl_dir/projects/scripts/adi_project.tcl +source $ad_hdl_dir/projects/scripts/adi_board.tcl adi_project_create adv7511_ac701 adi_project_files adv7511_ac701 [list \ "system_top.v" \ - "$ad_hdl_dir/projects/common/ac701/ac701_system_constr.xdc"] + "$ad_hdl_dir/library/common/ad_iobuf.v" \ + "$ad_hdl_dir/projects/common/ac701/ac701_system_constr.xdc" \ + "$ad_hdl_dir/projects/adv7511/ac701/system_constr.xdc"] adi_project_run adv7511_ac701 - diff --git a/projects/adv7511/ac701/system_top.v b/projects/adv7511/ac701/system_top.v index 52bc2bd00..c4a58794a 100644 --- a/projects/adv7511/ac701/system_top.v +++ b/projects/adv7511/ac701/system_top.v @@ -77,8 +77,7 @@ module system_top ( fan_pwm, gpio_lcd, - gpio_led, - gpio_sw, + gpio_bd, iic_rstn, iic_scl, @@ -128,8 +127,7 @@ module system_top ( output fan_pwm; inout [ 6:0] gpio_lcd; - inout [ 3:0] gpio_led; - inout [ 8:0] gpio_sw; + inout [12:0] gpio_bd; output iic_rstn; inout iic_scl; @@ -143,14 +141,26 @@ module system_top ( output spdif; - // assignments + // internal signals + + wire [63:0] gpio_i; + wire [63:0] gpio_o; + wire [63:0] gpio_t; + + // default logic assign mgt_clk_sel = 2'd0; - - wire [31:0] mb_intrs; + assign fan_pwm = 1'b1; + assign iic_rstn = 1'b1; // instantiations + ad_iobuf #(.DATA_WIDTH(21)) i_iobuf_sw_led ( + .dt (gpio_t[12:0]), + .di (gpio_o[12:0]), + .do (gpio_i[12:0]), + .dio(gpio_bd)); + system_wrapper i_system_wrapper ( .ddr3_addr (ddr3_addr), .ddr3_ba (ddr3_ba), @@ -167,40 +177,25 @@ module system_top ( .ddr3_ras_n (ddr3_ras_n), .ddr3_reset_n (ddr3_reset_n), .ddr3_we_n (ddr3_we_n), - .fan_pwm (fan_pwm), .gpio_lcd_tri_io (gpio_lcd), - .gpio_led_tri_io (gpio_led), - .gpio_sw_tri_io (gpio_sw), - .hdmi_data (hdmi_data), - .hdmi_data_e (hdmi_data_e), - .hdmi_hsync (hdmi_hsync), + .gpio0_o (gpio_o[31:0]), + .gpio0_t (gpio_t[31:0]), + .gpio0_i (gpio_i[31:0]), + .gpio1_o (gpio_o[63:32]), + .gpio1_t (gpio_t[63:32]), + .gpio1_i (gpio_i[63:32]), + .hdmi_24_data (hdmi_data), + .hdmi_24_data_e (hdmi_data_e), + .hdmi_24_hsync (hdmi_hsync), .hdmi_out_clk (hdmi_out_clk), - .hdmi_vsync (hdmi_vsync), + .hdmi_24_vsync (hdmi_vsync), .iic_main_scl_io (iic_scl), .iic_main_sda_io (iic_sda), - .iic_rstn (iic_rstn), - .mb_intr_10 (mb_intrs[10]), - .mb_intr_11 (mb_intrs[11]), - .mb_intr_12 (mb_intrs[12]), - .mb_intr_13 (mb_intrs[13]), - .mb_intr_14 (mb_intrs[14]), - .mb_intr_15 (mb_intrs[15]), - .mb_intr_16 (mb_intrs[16]), - .mb_intr_17 (mb_intrs[17]), - .mb_intr_18 (mb_intrs[18]), - .mb_intr_19 (mb_intrs[19]), - .mb_intr_20 (mb_intrs[20]), - .mb_intr_21 (mb_intrs[21]), - .mb_intr_22 (mb_intrs[22]), - .mb_intr_23 (mb_intrs[23]), - .mb_intr_24 (mb_intrs[24]), - .mb_intr_25 (mb_intrs[25]), - .mb_intr_26 (mb_intrs[26]), - .mb_intr_27 (mb_intrs[27]), - .mb_intr_28 (mb_intrs[28]), - .mb_intr_29 (mb_intrs[29]), - .mb_intr_30 (mb_intrs[30]), - .mb_intr_31 (mb_intrs[31]), + .mb_intr_06 (1'b0), + .mb_intr_12 (1'b0), + .mb_intr_13 (1'b0), + .mb_intr_14 (1'b0), + .mb_intr_15 (1'b0), .mdio_io (phy_mdio), .mdio_mdc (phy_mdc), .phy_rst_n (phy_reset_n), diff --git a/projects/common/ac701/ac701_system_bd.tcl b/projects/common/ac701/ac701_system_bd.tcl index 3be137cb8..4621fb536 100644 --- a/projects/common/ac701/ac701_system_bd.tcl +++ b/projects/common/ac701/ac701_system_bd.tcl @@ -1,40 +1,53 @@ -set sys_rst [create_bd_port -dir I -type rst sys_rst] -set sys_clk_p [create_bd_port -dir I sys_clk_p] -set sys_clk_n [create_bd_port -dir I sys_clk_n] -set fan_pwm [create_bd_port -dir O fan_pwm] +# interface ports -set ddr3 [create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 ddr3] +create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 ddr3 +create_bd_intf_port -mode Master -vlnv xilinx.com:interface:mdio_io:1.0 mdio +create_bd_intf_port -mode Master -vlnv xilinx.com:interface:rgmii_rtl:1.0 rgmii +create_bd_intf_port -mode Master -vlnv xilinx.com:interface:iic_rtl:1.0 iic_main +create_bd_intf_port -mode Master -vlnv xilinx.com:interface:gpio_rtl:1.0 gpio_lcd -set phy_rst_n [create_bd_port -dir O -type rst phy_rst_n] -set mdio [create_bd_intf_port -mode Master -vlnv xilinx.com:interface:mdio_io:1.0 mdio] -set rgmii [create_bd_intf_port -mode Master -vlnv xilinx.com:interface:rgmii_rtl:1.0 rgmii] +create_bd_port -dir I uart_sin +create_bd_port -dir O uart_sout -set gpio_sw [create_bd_intf_port -mode Master -vlnv xilinx.com:interface:gpio_rtl:1.0 gpio_sw] -set gpio_led [create_bd_intf_port -mode Master -vlnv xilinx.com:interface:gpio_rtl:1.0 gpio_led] -set gpio_lcd [create_bd_intf_port -mode Master -vlnv xilinx.com:interface:gpio_rtl:1.0 gpio_lcd] +create_bd_port -dir I -type rst sys_rst +create_bd_port -dir I sys_clk_p +create_bd_port -dir I sys_clk_n -set iic_rstn [create_bd_port -dir O iic_rstn] -set iic_main [create_bd_intf_port -mode Master -vlnv xilinx.com:interface:iic_rtl:1.0 iic_main] +create_bd_port -dir O -type rst phy_rst_n -set uart_sin [create_bd_port -dir I uart_sin] -set uart_sout [create_bd_port -dir O uart_sout] +create_bd_port -dir O -from 7 -to 0 spi_csn_o +create_bd_port -dir I -from 7 -to 0 spi_csn_i +create_bd_port -dir I spi_clk_i +create_bd_port -dir O spi_clk_o +create_bd_port -dir I spi_sdo_i +create_bd_port -dir O spi_sdo_o +create_bd_port -dir I spi_sdi_i -set hdmi_out_clk [create_bd_port -dir O hdmi_out_clk] -set hdmi_hsync [create_bd_port -dir O hdmi_hsync] -set hdmi_vsync [create_bd_port -dir O hdmi_vsync] -set hdmi_data_e [create_bd_port -dir O hdmi_data_e] -set hdmi_data [create_bd_port -dir O -from 23 -to 0 hdmi_data] +create_bd_port -dir I -from 31 -to 0 gpio0_i +create_bd_port -dir O -from 31 -to 0 gpio0_o +create_bd_port -dir O -from 31 -to 0 gpio0_t +create_bd_port -dir I -from 31 -to 0 gpio1_i +create_bd_port -dir O -from 31 -to 0 gpio1_o +create_bd_port -dir O -from 31 -to 0 gpio1_t -# spdif audio +# interrupts -set spdif [create_bd_port -dir O spdif] +create_bd_port -dir I -type intr mb_intr_06 +create_bd_port -dir I -type intr mb_intr_07 +create_bd_port -dir I -type intr mb_intr_08 +create_bd_port -dir I -type intr mb_intr_12 +create_bd_port -dir I -type intr mb_intr_13 +create_bd_port -dir I -type intr mb_intr_14 +create_bd_port -dir I -type intr mb_intr_15 -set_property -dict [list CONFIG.POLARITY {ACTIVE_HIGH}] $sys_rst +# io settings + +set_property -dict [list CONFIG.POLARITY {ACTIVE_HIGH}] [get_bd_ports sys_rst] # instance: microblaze - processor -set sys_mb [create_bd_cell -type ip -vlnv xilinx.com:ip:microblaze:9.3 sys_mb] +set sys_mb [create_bd_cell -type ip -vlnv xilinx.com:ip:microblaze:9.4 sys_mb] set_property -dict [list CONFIG.C_FAULT_TOLERANT {0}] $sys_mb set_property -dict [list CONFIG.C_D_AXI {1}] $sys_mb set_property -dict [list CONFIG.C_D_LMB {1}] $sys_mb @@ -70,47 +83,27 @@ set_property -dict [list CONFIG.Memory_Type {True_Dual_Port_RAM} CONFIG.use_bram # instance: microblaze- mdm -set sys_mb_debug [create_bd_cell -type ip -vlnv xilinx.com:ip:mdm:3.1 sys_mb_debug] +set sys_mb_debug [create_bd_cell -type ip -vlnv xilinx.com:ip:mdm:3.2 sys_mb_debug] set_property -dict [list CONFIG.C_USE_UART {1}] $sys_mb_debug # instance: system reset/clocks set sys_rstgen [create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 sys_rstgen] -set sys_const_vcc [create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 sys_const_vcc] - # instance: ddr (mig) -set axi_ddr_cntrl [create_bd_cell -type ip -vlnv xilinx.com:ip:mig_7series:2.1 axi_ddr_cntrl] +set axi_ddr_cntrl [create_bd_cell -type ip -vlnv xilinx.com:ip:mig_7series:2.3 axi_ddr_cntrl] set axi_ddr_cntrl_dir [get_property IP_DIR [get_ips [get_property CONFIG.Component_Name $axi_ddr_cntrl]]] file copy -force $ad_hdl_dir/projects/common/ac701/ac701_system_mig.prj "$axi_ddr_cntrl_dir/" set_property -dict [list CONFIG.XML_INPUT_FILE {ac701_system_mig.prj}] $axi_ddr_cntrl -# instance: axi interconnect (lite) -set axi_cpu_aux_interconnect [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_cpu_aux_interconnect] -set_property -dict [list CONFIG.NUM_MI {8}] $axi_cpu_aux_interconnect -set_property -dict [list CONFIG.STRATEGY {1}] $axi_cpu_aux_interconnect - -set axi_cpu_interconnect [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_cpu_interconnect] -set_property -dict [list CONFIG.NUM_MI {7}] $axi_cpu_interconnect -set_property -dict [list CONFIG.STRATEGY {1}] $axi_cpu_interconnect - -# instance: axi interconnect - -set axi_mem_interconnect [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_mem_interconnect] -set_property -dict [list CONFIG.NUM_SI {8}] $axi_mem_interconnect -set_property -dict [list CONFIG.NUM_MI {1}] $axi_mem_interconnect -set_property -dict [list CONFIG.ENABLE_ADVANCED_OPTIONS {1}] $axi_mem_interconnect -set_property -dict [list CONFIG.XBAR_DATA_WIDTH {512}] $axi_mem_interconnect -set_property -dict [list CONFIG.STRATEGY {2}] $axi_mem_interconnect - # instance: default peripherals set sys_ethernet_clkgen [create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:5.1 sys_ethernet_clkgen] set_property -dict [list CONFIG.PRIM_IN_FREQ {200.000}] $sys_ethernet_clkgen set_property -dict [list CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {125.000}] $sys_ethernet_clkgen -set axi_ethernet [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_ethernet:6.1 axi_ethernet] +set axi_ethernet [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_ethernet:6.2 axi_ethernet] set_property -dict [list CONFIG.PHY_TYPE {RGMII}] $axi_ethernet set axi_ethernet_dma [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_dma:7.1 axi_ethernet_dma] @@ -129,11 +122,16 @@ set axi_gpio_lcd [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_g set_property -dict [list CONFIG.C_GPIO_WIDTH {7}] $axi_gpio_lcd set_property -dict [list CONFIG.C_INTERRUPT_PRESENT {1}] $axi_gpio_lcd -set axi_gpio_sw_led [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_sw_led] -set_property -dict [list CONFIG.C_IS_DUAL {1}] $axi_gpio_sw_led -set_property -dict [list CONFIG.C_GPIO_WIDTH {9}] $axi_gpio_sw_led -set_property -dict [list CONFIG.C_GPIO2_WIDTH {4}] $axi_gpio_sw_led -set_property -dict [list CONFIG.C_INTERRUPT_PRESENT {1}] $axi_gpio_sw_led +set axi_spi [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_quad_spi:3.2 axi_spi] +set_property -dict [list CONFIG.C_USE_STARTUP {0}] $axi_spi +set_property -dict [list CONFIG.C_NUM_SS_BITS {8}] $axi_spi +set_property -dict [list CONFIG.C_SCK_RATIO {8}] $axi_spi + +set axi_gpio [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio] +set_property -dict [list CONFIG.C_IS_DUAL {1}] $axi_gpio +set_property -dict [list CONFIG.C_GPIO_WIDTH {32}] $axi_gpio +set_property -dict [list CONFIG.C_GPIO2_WIDTH {32}] $axi_gpio +set_property -dict [list CONFIG.C_INTERRUPT_PRESENT {1}] $axi_gpio # instance: interrupt @@ -141,347 +139,137 @@ set axi_intc [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_intc:4.1 axi_intc] set_property -dict [list CONFIG.C_HAS_FAST {0}] $axi_intc set sys_concat_intc [create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 sys_concat_intc] -set_property -dict [list CONFIG.NUM_PORTS {32}] $sys_concat_intc - -# hdmi peripherals - -set axi_hdmi_clkgen [create_bd_cell -type ip -vlnv analog.com:user:axi_clkgen:1.0 axi_hdmi_clkgen] -set axi_hdmi_core [create_bd_cell -type ip -vlnv analog.com:user:axi_hdmi_tx:1.0 axi_hdmi_core] - -set axi_hdmi_dma [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_vdma:6.2 axi_hdmi_dma] -set_property -dict [list CONFIG.c_m_axis_mm2s_tdata_width {64}] $axi_hdmi_dma -set_property -dict [list CONFIG.c_use_mm2s_fsync {1}] $axi_hdmi_dma -set_property -dict [list CONFIG.c_include_s2mm {0}] $axi_hdmi_dma - -# audio peripherals - -set sys_audio_clkgen [create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:5.1 sys_audio_clkgen] -set_property -dict [list CONFIG.PRIM_IN_FREQ {200.000}] $sys_audio_clkgen -set_property -dict [list CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {12.288}] $sys_audio_clkgen -set_property -dict [list CONFIG.USE_LOCKED {false}] $sys_audio_clkgen -set_property -dict [list CONFIG.USE_RESET {true} CONFIG.RESET_TYPE {ACTIVE_LOW}] $sys_audio_clkgen - -set axi_spdif_tx_core [create_bd_cell -type ip -vlnv analog.com:user:axi_spdif_tx:1.0 axi_spdif_tx_core] -set_property -dict [list CONFIG.C_DMA_TYPE {0}] $axi_spdif_tx_core -set_property -dict [list CONFIG.C_S_AXI_ADDR_WIDTH {16}] $axi_spdif_tx_core - -set axi_spdif_tx_dma [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_dma:7.1 axi_spdif_tx_dma] -set_property -dict [list CONFIG.c_include_s2mm {0}] $axi_spdif_tx_dma -set_property -dict [list CONFIG.c_sg_include_stscntrl_strm {0}] $axi_spdif_tx_dma +set_property -dict [list CONFIG.NUM_PORTS {16}] $sys_concat_intc # connections -connect_bd_net -net mdm_1_debug_sys_rst [get_bd_pins sys_mb_debug/Debug_SYS_Rst] -connect_bd_net -net mdm_1_debug_sys_rst [get_bd_pins sys_rstgen/mb_debug_sys_rst] - -connect_bd_net -net sys_rstgen_mb_reset [get_bd_pins sys_rstgen/mb_reset] -connect_bd_net -net sys_rstgen_mb_reset [get_bd_pins sys_mb/Reset] - -connect_bd_net -net sys_rstgen_bus_struct_reset [get_bd_pins sys_rstgen/bus_struct_reset] -connect_bd_net -net sys_rstgen_bus_struct_reset [get_bd_pins sys_dlmb/SYS_Rst] -connect_bd_net -net sys_rstgen_bus_struct_reset [get_bd_pins sys_ilmb/SYS_Rst] -connect_bd_net -net sys_rstgen_bus_struct_reset [get_bd_pins sys_dlmb_cntlr/LMB_Rst] -connect_bd_net -net sys_rstgen_bus_struct_reset [get_bd_pins sys_ilmb_cntlr/LMB_Rst] +ad_connect sys_mb_debug/Debug_SYS_Rst sys_rstgen/mb_debug_sys_rst +ad_connect sys_rstgen/mb_reset sys_mb/Reset +ad_connect sys_rstgen/bus_struct_reset sys_dlmb/SYS_Rst +ad_connect sys_rstgen/bus_struct_reset sys_ilmb/SYS_Rst +ad_connect sys_rstgen/bus_struct_reset sys_dlmb_cntlr/LMB_Rst +ad_connect sys_rstgen/bus_struct_reset sys_ilmb_cntlr/LMB_Rst # microblaze local memory -connect_bd_intf_net -intf_net lmb_cntlr_1_dlmb [get_bd_intf_pins sys_dlmb/LMB_Sl_0] [get_bd_intf_pins sys_dlmb_cntlr/SLMB] -connect_bd_intf_net -intf_net lmb_cntlr_1_ilmb [get_bd_intf_pins sys_ilmb/LMB_Sl_0] [get_bd_intf_pins sys_ilmb_cntlr/SLMB] -connect_bd_intf_net -intf_net lmb_cntlr_1_dlmb_bram [get_bd_intf_pins sys_dlmb_cntlr/BRAM_PORT] [get_bd_intf_pins sys_lmb_bram/BRAM_PORTA] -connect_bd_intf_net -intf_net lmb_cntlr_1_ilmb_bram [get_bd_intf_pins sys_ilmb_cntlr/BRAM_PORT] [get_bd_intf_pins sys_lmb_bram/BRAM_PORTB] -connect_bd_intf_net -intf_net sys_mb_dlmb [get_bd_intf_pins sys_mb/DLMB] [get_bd_intf_pins sys_dlmb/LMB_M] -connect_bd_intf_net -intf_net sys_mb_ilmb [get_bd_intf_pins sys_mb/ILMB] [get_bd_intf_pins sys_ilmb/LMB_M] +ad_connect sys_dlmb/LMB_Sl_0 sys_dlmb_cntlr/SLMB +ad_connect sys_ilmb/LMB_Sl_0 sys_ilmb_cntlr/SLMB +ad_connect sys_dlmb_cntlr/BRAM_PORT sys_lmb_bram/BRAM_PORTA +ad_connect sys_ilmb_cntlr/BRAM_PORT sys_lmb_bram/BRAM_PORTB +ad_connect sys_mb/DLMB sys_dlmb/LMB_M +ad_connect sys_mb/ILMB sys_ilmb/LMB_M # microblaze debug & interrupt -connect_bd_intf_net -intf_net sys_mb_debug_intf [get_bd_intf_pins sys_mb_debug/MBDEBUG_0] [get_bd_intf_pins sys_mb/DEBUG] -connect_bd_intf_net -intf_net sys_mb_interrupt [get_bd_intf_pins axi_intc/interrupt] [get_bd_intf_pins sys_mb/INTERRUPT] -connect_bd_net -net sys_concat_intc_intr [get_bd_pins sys_concat_intc/dout] [get_bd_pins axi_intc/intr] +ad_connect sys_mb_debug/MBDEBUG_0 sys_mb/DEBUG +ad_connect axi_intc/interrupt sys_mb/INTERRUPT +ad_connect sys_concat_intc/dout axi_intc/intr # defaults (peripherals) -connect_bd_net -net axi_ddr_cntrl_mmcm_locked [get_bd_pins axi_ddr_cntrl/mmcm_locked] [get_bd_pins sys_rstgen/dcm_locked] +ad_connect axi_ddr_cntrl/mmcm_locked sys_rstgen/dcm_locked -set sys_100m_resetn_source [get_bd_pins sys_rstgen/peripheral_aresetn] -set sys_200m_resetn_source [get_bd_pins sys_rstgen/interconnect_aresetn] -set sys_100m_clk_source [get_bd_pins axi_ddr_cntrl/ui_clk] -set sys_200m_clk_source [get_bd_pins axi_ddr_cntrl/ui_addn_clk_0] +ad_connect sys_cpu_clk axi_ddr_cntrl/ui_clk +ad_connect sys_200m_clk axi_ddr_cntrl/ui_addn_clk_0 +ad_connect sys_cpu_resetn axi_ddr_cntrl/aresetn +ad_connect sys_cpu_reset sys_rstgen/peripheral_reset +ad_connect sys_cpu_resetn sys_rstgen/peripheral_aresetn -connect_bd_net -net sys_100m_resetn $sys_100m_resetn_source -connect_bd_net -net sys_200m_resetn $sys_200m_resetn_source -connect_bd_net -net sys_100m_clk $sys_100m_clk_source -connect_bd_net -net sys_200m_clk $sys_200m_clk_source - -connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M06_ARESETN] $sys_100m_resetn_source -connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_aux_interconnect/ARESETN] $sys_100m_resetn_source -connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/ARESETN] $sys_100m_resetn_source -connect_bd_net -net sys_100m_resetn [get_bd_pins axi_mem_interconnect/ARESETN] $sys_100m_resetn_source -connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M06_ACLK] $sys_100m_clk_source -connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_aux_interconnect/ACLK] $sys_100m_clk_source -connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/ACLK] $sys_100m_clk_source -connect_bd_net -net sys_100m_clk [get_bd_pins axi_mem_interconnect/ACLK] $sys_100m_clk_source - -connect_bd_net -net sys_100m_resetn [get_bd_pins sys_mb_debug/S_AXI_ARESETN] -connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ddr_cntrl/aresetn] -connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ethernet/s_axi_lite_resetn] $sys_100m_resetn_source -connect_bd_net -net sys_100m_resetn [get_bd_pins axi_uart/s_axi_aresetn] -connect_bd_net -net sys_100m_resetn [get_bd_pins axi_timer/s_axi_aresetn] -connect_bd_net -net sys_100m_resetn [get_bd_pins axi_intc/s_axi_aresetn] -connect_bd_net -net sys_100m_resetn [get_bd_pins axi_gpio_lcd/s_axi_aresetn] -connect_bd_net -net sys_100m_resetn [get_bd_pins axi_gpio_sw_led/s_axi_aresetn] -connect_bd_net -net sys_100m_resetn [get_bd_pins axi_iic_main/s_axi_aresetn] -connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ethernet_dma/axi_resetn] - -connect_bd_net -net sys_100m_clk [get_bd_pins sys_rstgen/slowest_sync_clk] -connect_bd_net -net sys_100m_clk [get_bd_pins sys_mb/Clk] -connect_bd_net -net sys_100m_clk [get_bd_pins sys_mb_debug/S_AXI_ACLK] -connect_bd_net -net sys_100m_clk [get_bd_pins sys_dlmb/LMB_Clk] -connect_bd_net -net sys_100m_clk [get_bd_pins sys_ilmb/LMB_Clk] -connect_bd_net -net sys_100m_clk [get_bd_pins sys_dlmb_cntlr/LMB_Clk] -connect_bd_net -net sys_100m_clk [get_bd_pins sys_ilmb_cntlr/LMB_Clk] -connect_bd_net -net sys_100m_clk [get_bd_pins axi_ethernet/s_axi_lite_clk] $sys_100m_clk_source -connect_bd_net -net sys_100m_clk [get_bd_pins axi_ethernet/axis_clk] $sys_100m_clk_source -connect_bd_net -net sys_100m_clk [get_bd_pins axi_ethernet_dma/m_axi_sg_aclk] -connect_bd_net -net sys_100m_clk [get_bd_pins axi_ethernet_dma/m_axi_mm2s_aclk] -connect_bd_net -net sys_100m_clk [get_bd_pins axi_ethernet_dma/m_axi_s2mm_aclk] -connect_bd_net -net sys_100m_clk [get_bd_pins axi_ethernet_dma/s_axi_lite_aclk] -connect_bd_net -net sys_100m_clk [get_bd_pins axi_uart/s_axi_aclk] -connect_bd_net -net sys_100m_clk [get_bd_pins axi_timer/s_axi_aclk] -connect_bd_net -net sys_100m_clk [get_bd_pins axi_intc/s_axi_aclk] -connect_bd_net -net sys_100m_clk [get_bd_pins axi_gpio_lcd/s_axi_aclk] -connect_bd_net -net sys_100m_clk [get_bd_pins axi_gpio_sw_led/s_axi_aclk] -connect_bd_net -net sys_100m_clk [get_bd_pins axi_iic_main/s_axi_aclk] - -connect_bd_net -net sys_200m_clk [get_bd_pins axi_ethernet/ref_clk] $sys_200m_clk_source - -# defaults (interconnect - processor) - -connect_bd_intf_net -intf_net axi_cpu_aux_interconnect_s00 [get_bd_intf_pins axi_cpu_aux_interconnect/S00_AXI] [get_bd_intf_pins axi_cpu_interconnect/M06_AXI] -connect_bd_intf_net -intf_net axi_cpu_aux_interconnect_m00 [get_bd_intf_pins axi_cpu_aux_interconnect/M00_AXI] [get_bd_intf_pins sys_mb_debug/S_AXI] -connect_bd_intf_net -intf_net axi_cpu_aux_interconnect_m01 [get_bd_intf_pins axi_cpu_aux_interconnect/M01_AXI] [get_bd_intf_pins axi_ethernet/s_axi] -connect_bd_intf_net -intf_net axi_cpu_aux_interconnect_m02 [get_bd_intf_pins axi_cpu_aux_interconnect/M02_AXI] [get_bd_intf_pins axi_ethernet_dma/S_AXI_LITE] -connect_bd_intf_net -intf_net axi_cpu_aux_interconnect_m03 [get_bd_intf_pins axi_cpu_aux_interconnect/M03_AXI] [get_bd_intf_pins axi_uart/s_axi] -connect_bd_intf_net -intf_net axi_cpu_aux_interconnect_m04 [get_bd_intf_pins axi_cpu_aux_interconnect/M04_AXI] [get_bd_intf_pins axi_timer/s_axi] -connect_bd_intf_net -intf_net axi_cpu_aux_interconnect_m05 [get_bd_intf_pins axi_cpu_aux_interconnect/M05_AXI] [get_bd_intf_pins axi_intc/s_axi] -connect_bd_intf_net -intf_net axi_cpu_aux_interconnect_m06 [get_bd_intf_pins axi_cpu_aux_interconnect/M06_AXI] [get_bd_intf_pins axi_gpio_lcd/s_axi] -connect_bd_intf_net -intf_net axi_cpu_aux_interconnect_m07 [get_bd_intf_pins axi_cpu_aux_interconnect/M07_AXI] [get_bd_intf_pins axi_gpio_sw_led/s_axi] -connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_aux_interconnect/S00_ARESETN] $sys_100m_resetn_source -connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_aux_interconnect/M00_ARESETN] $sys_100m_resetn_source -connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_aux_interconnect/M01_ARESETN] $sys_100m_resetn_source -connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_aux_interconnect/M02_ARESETN] $sys_100m_resetn_source -connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_aux_interconnect/M03_ARESETN] $sys_100m_resetn_source -connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_aux_interconnect/M04_ARESETN] $sys_100m_resetn_source -connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_aux_interconnect/M05_ARESETN] $sys_100m_resetn_source -connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_aux_interconnect/M06_ARESETN] $sys_100m_resetn_source -connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_aux_interconnect/M07_ARESETN] $sys_100m_resetn_source -connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_aux_interconnect/S00_ACLK] $sys_100m_clk_source -connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_aux_interconnect/M00_ACLK] $sys_100m_clk_source -connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_aux_interconnect/M01_ACLK] $sys_100m_clk_source -connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_aux_interconnect/M02_ACLK] $sys_100m_clk_source -connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_aux_interconnect/M03_ACLK] $sys_100m_clk_source -connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_aux_interconnect/M04_ACLK] $sys_100m_clk_source -connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_aux_interconnect/M05_ACLK] $sys_100m_clk_source -connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_aux_interconnect/M06_ACLK] $sys_100m_clk_source -connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_aux_interconnect/M07_ACLK] $sys_100m_clk_source - -connect_bd_intf_net -intf_net axi_cpu_interconnect_s00 [get_bd_intf_pins axi_cpu_interconnect/S00_AXI] [get_bd_intf_pins sys_mb/M_AXI_DP] -connect_bd_intf_net -intf_net axi_cpu_interconnect_m00 [get_bd_intf_pins axi_cpu_interconnect/M00_AXI] [get_bd_intf_pins axi_iic_main/s_axi] -connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/S00_ARESETN] $sys_100m_resetn_source -connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M00_ARESETN] $sys_100m_resetn_source -connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/S00_ACLK] $sys_100m_clk_source -connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M00_ACLK] $sys_100m_clk_source - -# defaults (interconnect - memory) - -connect_bd_intf_net -intf_net axi_mem_interconnect_m00 [get_bd_intf_pins axi_mem_interconnect/M00_AXI] [get_bd_intf_pins axi_ddr_cntrl/S_AXI] -connect_bd_intf_net -intf_net axi_mem_interconnect_s00 [get_bd_intf_pins axi_mem_interconnect/S00_AXI] [get_bd_intf_pins sys_mb/M_AXI_DC] -connect_bd_intf_net -intf_net axi_mem_interconnect_s01 [get_bd_intf_pins axi_mem_interconnect/S01_AXI] [get_bd_intf_pins sys_mb/M_AXI_IC] -connect_bd_intf_net -intf_net axi_mem_interconnect_s05 [get_bd_intf_pins axi_mem_interconnect/S05_AXI] [get_bd_intf_pins axi_ethernet_dma/M_AXI_SG] -connect_bd_intf_net -intf_net axi_mem_interconnect_s06 [get_bd_intf_pins axi_mem_interconnect/S06_AXI] [get_bd_intf_pins axi_ethernet_dma/M_AXI_MM2S] -connect_bd_intf_net -intf_net axi_mem_interconnect_s07 [get_bd_intf_pins axi_mem_interconnect/S07_AXI] [get_bd_intf_pins axi_ethernet_dma/M_AXI_S2MM] -connect_bd_net -net sys_100m_resetn [get_bd_pins axi_mem_interconnect/M00_ARESETN] $sys_100m_resetn_source -connect_bd_net -net sys_100m_resetn [get_bd_pins axi_mem_interconnect/S00_ARESETN] $sys_100m_resetn_source -connect_bd_net -net sys_100m_resetn [get_bd_pins axi_mem_interconnect/S01_ARESETN] $sys_100m_resetn_source -connect_bd_net -net sys_100m_resetn [get_bd_pins axi_mem_interconnect/S05_ARESETN] $sys_100m_resetn_source -connect_bd_net -net sys_100m_resetn [get_bd_pins axi_mem_interconnect/S06_ARESETN] $sys_100m_resetn_source -connect_bd_net -net sys_100m_resetn [get_bd_pins axi_mem_interconnect/S07_ARESETN] $sys_100m_resetn_source -connect_bd_net -net sys_100m_clk [get_bd_pins axi_mem_interconnect/M00_ACLK] $sys_100m_clk_source -connect_bd_net -net sys_100m_clk [get_bd_pins axi_mem_interconnect/S00_ACLK] $sys_100m_clk_source -connect_bd_net -net sys_100m_clk [get_bd_pins axi_mem_interconnect/S01_ACLK] $sys_100m_clk_source -connect_bd_net -net sys_100m_clk [get_bd_pins axi_mem_interconnect/S05_ACLK] $sys_100m_clk_source -connect_bd_net -net sys_100m_clk [get_bd_pins axi_mem_interconnect/S06_ACLK] $sys_100m_clk_source -connect_bd_net -net sys_100m_clk [get_bd_pins axi_mem_interconnect/S07_ACLK] $sys_100m_clk_source - -# ethernet & ethernet dma - -connect_bd_net -net sys_200m_clk [get_bd_pins sys_ethernet_clkgen/clk_in1] -connect_bd_net -net sys_ethernet_clkgen_clk [get_bd_pins sys_ethernet_clkgen/clk_out1] [get_bd_pins axi_ethernet/gtx_clk] - -connect_bd_net -net axi_ethernet_dma_txd_rstn [get_bd_pins axi_ethernet/axi_txd_arstn] [get_bd_pins axi_ethernet_dma/mm2s_prmry_reset_out_n] -connect_bd_net -net axi_ethernet_dma_txc_rstn [get_bd_pins axi_ethernet/axi_txc_arstn] [get_bd_pins axi_ethernet_dma/mm2s_cntrl_reset_out_n] -connect_bd_net -net axi_ethernet_dma_rxd_rstn [get_bd_pins axi_ethernet/axi_rxd_arstn] [get_bd_pins axi_ethernet_dma/s2mm_prmry_reset_out_n] -connect_bd_net -net axi_ethernet_dma_rxs_rstn [get_bd_pins axi_ethernet/axi_rxs_arstn] [get_bd_pins axi_ethernet_dma/s2mm_sts_reset_out_n] - -connect_bd_intf_net -intf_net axi_ethernet_dma_txd [get_bd_intf_pins axi_ethernet/s_axis_txd] [get_bd_intf_pins axi_ethernet_dma/M_AXIS_MM2S] -connect_bd_intf_net -intf_net axi_ethernet_dma_txc [get_bd_intf_pins axi_ethernet/s_axis_txc] [get_bd_intf_pins axi_ethernet_dma/M_AXIS_CNTRL] -connect_bd_intf_net -intf_net axi_ethernet_dma_rxd [get_bd_intf_pins axi_ethernet/m_axis_rxd] [get_bd_intf_pins axi_ethernet_dma/S_AXIS_S2MM] -connect_bd_intf_net -intf_net axi_ethernet_dma_rxs [get_bd_intf_pins axi_ethernet/m_axis_rxs] [get_bd_intf_pins axi_ethernet_dma/S_AXIS_STS] +ad_connect sys_cpu_clk sys_rstgen/slowest_sync_clk +ad_connect sys_cpu_clk sys_mb/Clk +ad_connect sys_cpu_clk sys_dlmb/LMB_Clk +ad_connect sys_cpu_clk sys_ilmb/LMB_Clk +ad_connect sys_cpu_clk sys_dlmb_cntlr/LMB_Clk +ad_connect sys_cpu_clk sys_ilmb_cntlr/LMB_Clk +ad_connect sys_cpu_clk axi_spi/ext_spi_clk # defaults (interrupts) -connect_bd_net [get_bd_pins sys_concat_intc/In0] [get_bd_pins axi_timer/interrupt] -connect_bd_net [get_bd_pins sys_concat_intc/In1] [get_bd_pins axi_ethernet/interrupt] -connect_bd_net [get_bd_pins sys_concat_intc/In2] [get_bd_pins axi_ethernet_dma/mm2s_introut] -connect_bd_net [get_bd_pins sys_concat_intc/In3] [get_bd_pins axi_ethernet_dma/s2mm_introut] -connect_bd_net [get_bd_pins sys_concat_intc/In4] [get_bd_pins axi_uart/interrupt] -connect_bd_net [get_bd_pins sys_concat_intc/In5] [get_bd_pins axi_gpio_lcd/ip2intc_irpt] -connect_bd_net [get_bd_pins sys_concat_intc/In6] [get_bd_pins axi_gpio_sw_led/ip2intc_irpt] -connect_bd_net [get_bd_pins sys_concat_intc/In7] [get_bd_pins axi_spdif_tx_dma/mm2s_introut] -connect_bd_net [get_bd_pins sys_concat_intc/In8] [get_bd_pins axi_hdmi_dma/mm2s_introut] -connect_bd_net [get_bd_pins sys_concat_intc/In9] [get_bd_pins axi_iic_main/iic2intc_irpt] - -for {set intc_index 10} {$intc_index < 32} {incr intc_index} { - set mb_intr_${intc_index} [create_bd_port -dir I mb_intr_${intc_index}] - connect_bd_net [get_bd_pins sys_concat_intc/In${intc_index}] [get_bd_ports mb_intr_${intc_index}] -} +ad_connect sys_concat_intc/In0 axi_timer/interrupt +ad_connect sys_concat_intc/In1 axi_ethernet/interrupt +ad_connect sys_concat_intc/In2 axi_ethernet_dma/mm2s_introut +ad_connect sys_concat_intc/In3 axi_ethernet_dma/s2mm_introut +ad_connect sys_concat_intc/In4 axi_uart/interrupt +ad_connect sys_concat_intc/In5 axi_gpio_lcd/ip2intc_irpt +ad_connect sys_concat_intc/In6 mb_intr_06 +ad_connect sys_concat_intc/In7 mb_intr_07 +ad_connect sys_concat_intc/In8 mb_intr_08 +ad_connect sys_concat_intc/In9 axi_iic_main/iic2intc_irpt +ad_connect sys_concat_intc/In10 axi_spi/ip2intc_irpt +ad_connect sys_concat_intc/In11 axi_gpio/ip2intc_irpt +ad_connect sys_concat_intc/In12 mb_intr_12 +ad_connect sys_concat_intc/In13 mb_intr_13 +ad_connect sys_concat_intc/In14 mb_intr_14 +ad_connect sys_concat_intc/In15 mb_intr_15 # defaults (external interface) -connect_bd_net -net sys_const_vcc_vcc [get_bd_pins sys_const_vcc/dout] [get_bd_ports fan_pwm] -connect_bd_net -net sys_rst_s [get_bd_ports sys_rst] -connect_bd_net -net sys_rst_s [get_bd_pins sys_rstgen/ext_reset_in] -connect_bd_net -net sys_rst_s [get_bd_pins axi_ddr_cntrl/sys_rst] +ad_connect sys_rst sys_rstgen/ext_reset_in +ad_connect sys_rst axi_ddr_cntrl/sys_rst +ad_connect sys_clk_p axi_ddr_cntrl/sys_clk_p +ad_connect sys_clk_n axi_ddr_cntrl/sys_clk_n +ad_connect ddr3 axi_ddr_cntrl/DDR3 +ad_connect mdio axi_ethernet/mdio_io +ad_connect rgmii axi_ethernet/rgmii +ad_connect uart_sin axi_uart/rx +ad_connect uart_sout axi_uart/tx +ad_connect gpio_lcd axi_gpio_lcd/gpio +ad_connect iic_main axi_iic_main/iic -connect_bd_net -net sys_clk_p_s [get_bd_ports sys_clk_p] [get_bd_pins axi_ddr_cntrl/sys_clk_p] -connect_bd_net -net sys_clk_n_s [get_bd_ports sys_clk_n] [get_bd_pins axi_ddr_cntrl/sys_clk_n] +ad_connect spi_csn_i axi_spi/ss_i +ad_connect spi_csn_o axi_spi/ss_o +ad_connect spi_clk_i axi_spi/sck_i +ad_connect spi_clk_o axi_spi/sck_o +ad_connect spi_sdo_i axi_spi/io0_i +ad_connect spi_sdo_o axi_spi/io0_o +ad_connect spi_sdi_i axi_spi/io1_i +ad_connect gpio0_i axi_gpio/gpio_io_i +ad_connect gpio0_o axi_gpio/gpio_io_o +ad_connect gpio0_t axi_gpio/gpio_io_t +ad_connect gpio1_i axi_gpio/gpio2_io_i +ad_connect gpio1_o axi_gpio/gpio2_io_o +ad_connect gpio1_t axi_gpio/gpio2_io_t -connect_bd_intf_net -intf_net axi_ddr_cntrl_ddr3 [get_bd_intf_ports ddr3] [get_bd_intf_pins axi_ddr_cntrl/DDR3] -connect_bd_intf_net -intf_net axi_ethernet_mdio [get_bd_intf_ports mdio] [get_bd_intf_pins axi_ethernet/mdio] -connect_bd_intf_net -intf_net axi_ethernet_rgmii [get_bd_intf_ports rgmii] [get_bd_intf_pins axi_ethernet/rgmii] -connect_bd_net -net axi_ethernet_phy_rst_n [get_bd_ports phy_rst_n] [get_bd_pins axi_ethernet/phy_rst_n] +# ethernet & ethernet dma -connect_bd_net -net axi_uart_sin [get_bd_ports uart_sin] [get_bd_pins axi_uart/rx] -connect_bd_net -net axi_uart_sout [get_bd_ports uart_sout] [get_bd_pins axi_uart/tx] +ad_connect sys_cpu_clk axi_ethernet/axis_clk +ad_connect sys_200m_clk axi_ethernet/ref_clk +ad_connect sys_200m_clk sys_ethernet_clkgen/clk_in1 +ad_connect sys_ethernet_clkgen/clk_out1 axi_ethernet/gtx_clk -connect_bd_intf_net -intf_net axi_gpio_lcd_gpio [get_bd_intf_ports gpio_lcd] [get_bd_intf_pins axi_gpio_lcd/gpio] -connect_bd_intf_net -intf_net axi_gpio_sw_led_gpio [get_bd_intf_ports gpio_sw] [get_bd_intf_pins axi_gpio_sw_led/gpio] -connect_bd_intf_net -intf_net axi_gpio_sw_led_gpio2 [get_bd_intf_ports gpio_led] [get_bd_intf_pins axi_gpio_sw_led/gpio2] +ad_connect axi_ethernet/axi_txd_arstn axi_ethernet_dma/mm2s_prmry_reset_out_n +ad_connect axi_ethernet/axi_txc_arstn axi_ethernet_dma/mm2s_cntrl_reset_out_n +ad_connect axi_ethernet/axi_rxd_arstn axi_ethernet_dma/s2mm_prmry_reset_out_n +ad_connect axi_ethernet/axi_rxs_arstn axi_ethernet_dma/s2mm_sts_reset_out_n -connect_bd_net -net sys_const_vcc_vcc [get_bd_ports iic_rstn] [get_bd_pins sys_const_vcc/dout] -connect_bd_intf_net -intf_net axi_iic_main_iic [get_bd_intf_ports iic_main] [get_bd_intf_pins axi_iic_main/iic] - -# hdmi peripherals - -connect_bd_net -net sys_100m_resetn [get_bd_pins axi_hdmi_clkgen/s_axi_aresetn] -connect_bd_net -net sys_100m_resetn [get_bd_pins axi_hdmi_dma/axi_resetn] -connect_bd_net -net sys_100m_resetn [get_bd_pins axi_hdmi_core/s_axi_aresetn] -connect_bd_net -net sys_100m_clk [get_bd_pins axi_hdmi_clkgen/s_axi_aclk] -connect_bd_net -net sys_100m_clk [get_bd_pins axi_hdmi_clkgen/drp_clk] -connect_bd_net -net sys_100m_clk [get_bd_pins axi_hdmi_dma/s_axi_lite_aclk] -connect_bd_net -net sys_100m_clk [get_bd_pins axi_hdmi_dma/m_axi_mm2s_aclk] -connect_bd_net -net sys_100m_clk [get_bd_pins axi_hdmi_dma/m_axis_mm2s_aclk] -connect_bd_net -net sys_100m_clk [get_bd_pins axi_hdmi_core/s_axi_aclk] -connect_bd_net -net sys_100m_clk [get_bd_pins axi_hdmi_core/m_axis_mm2s_clk] -connect_bd_net -net sys_200m_clk [get_bd_pins axi_hdmi_clkgen/clk] - -connect_bd_intf_net -intf_net axi_cpu_interconnect_m01 [get_bd_intf_pins axi_cpu_interconnect/M01_AXI] [get_bd_intf_pins axi_hdmi_clkgen/s_axi] -connect_bd_intf_net -intf_net axi_cpu_interconnect_m02 [get_bd_intf_pins axi_cpu_interconnect/M02_AXI] [get_bd_intf_pins axi_hdmi_dma/S_AXI_LITE] -connect_bd_intf_net -intf_net axi_cpu_interconnect_m03 [get_bd_intf_pins axi_cpu_interconnect/M03_AXI] [get_bd_intf_pins axi_hdmi_core/s_axi] -connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M01_ARESETN] $sys_100m_resetn_source -connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M02_ARESETN] $sys_100m_resetn_source -connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M03_ARESETN] $sys_100m_resetn_source -connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M01_ACLK] $sys_100m_clk_source -connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M02_ACLK] $sys_100m_clk_source -connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M03_ACLK] $sys_100m_clk_source - -connect_bd_intf_net -intf_net axi_mem_interconnect_s02 [get_bd_intf_pins axi_mem_interconnect/S02_AXI] [get_bd_intf_pins axi_hdmi_dma/M_AXI_MM2S] -connect_bd_net -net sys_100m_resetn [get_bd_pins axi_mem_interconnect/S02_ARESETN] $sys_100m_resetn_source -connect_bd_net -net sys_100m_clk [get_bd_pins axi_mem_interconnect/S02_ACLK] $sys_100m_clk_source - -connect_bd_net -net axi_hdmi_core_hdmi_out_clk [get_bd_ports hdmi_out_clk] [get_bd_pins axi_hdmi_core/hdmi_out_clk] -connect_bd_net -net axi_hdmi_core_hdmi_hsync [get_bd_ports hdmi_hsync] [get_bd_pins axi_hdmi_core/hdmi_24_hsync] -connect_bd_net -net axi_hdmi_core_hdmi_vsync [get_bd_ports hdmi_vsync] [get_bd_pins axi_hdmi_core/hdmi_24_vsync] -connect_bd_net -net axi_hdmi_core_hdmi_data_e [get_bd_ports hdmi_data_e] [get_bd_pins axi_hdmi_core/hdmi_24_data_e] -connect_bd_net -net axi_hdmi_core_hdmi_data [get_bd_ports hdmi_data] [get_bd_pins axi_hdmi_core/hdmi_24_data] - -connect_bd_net -net axi_hdmi_clkgen_clk [get_bd_pins axi_hdmi_clkgen/clk_0] [get_bd_pins axi_hdmi_core/hdmi_clk] -connect_bd_net -net axi_hdmi_core_valid [get_bd_pins axi_hdmi_dma/m_axis_mm2s_tvalid] [get_bd_pins axi_hdmi_core/m_axis_mm2s_tvalid] -connect_bd_net -net axi_hdmi_core_data [get_bd_pins axi_hdmi_dma/m_axis_mm2s_tdata] [get_bd_pins axi_hdmi_core/m_axis_mm2s_tdata] -connect_bd_net -net axi_hdmi_core_keep [get_bd_pins axi_hdmi_dma/m_axis_mm2s_tkeep] [get_bd_pins axi_hdmi_core/m_axis_mm2s_tkeep] -connect_bd_net -net axi_hdmi_core_last [get_bd_pins axi_hdmi_dma/m_axis_mm2s_tlast] [get_bd_pins axi_hdmi_core/m_axis_mm2s_tlast] -connect_bd_net -net axi_hdmi_core_ready [get_bd_pins axi_hdmi_dma/m_axis_mm2s_tready] [get_bd_pins axi_hdmi_core/m_axis_mm2s_tready] -connect_bd_net -net axi_hdmi_core_fsync [get_bd_pins axi_hdmi_dma/mm2s_fsync] [get_bd_pins axi_hdmi_core/m_axis_mm2s_fsync] -connect_bd_net -net axi_hdmi_core_fsync [get_bd_pins axi_hdmi_core/m_axis_mm2s_fsync_ret] - -# spdif audio - -connect_bd_net -net sys_100m_resetn [get_bd_pins axi_spdif_tx_core/S_AXI_ARESETN] -connect_bd_net -net sys_100m_resetn [get_bd_pins axi_spdif_tx_core/S_AXIS_ARESETN] -connect_bd_net -net sys_100m_resetn [get_bd_pins axi_spdif_tx_dma/axi_resetn] -connect_bd_net -net sys_100m_clk [get_bd_pins axi_spdif_tx_core/S_AXI_ACLK] -connect_bd_net -net sys_100m_clk [get_bd_pins axi_spdif_tx_dma/s_axi_lite_aclk] -connect_bd_net -net sys_100m_clk [get_bd_pins axi_spdif_tx_core/S_AXIS_ACLK] -connect_bd_net -net sys_100m_clk [get_bd_pins axi_spdif_tx_dma/m_axi_mm2s_aclk] -connect_bd_net -net sys_100m_clk [get_bd_pins axi_spdif_tx_dma/m_axi_sg_aclk] -connect_bd_intf_net -intf_net axi_cpu_interconnect_m04 [get_bd_intf_pins axi_cpu_interconnect/M04_AXI] [get_bd_intf_pins axi_spdif_tx_core/s_axi] -connect_bd_intf_net -intf_net axi_cpu_interconnect_m05 [get_bd_intf_pins axi_cpu_interconnect/M05_AXI] [get_bd_intf_pins axi_spdif_tx_dma/S_AXI_LITE] -connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M04_ARESETN] $sys_100m_resetn_source -connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M05_ARESETN] $sys_100m_resetn_source -connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M04_ACLK] $sys_100m_clk_source -connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M05_ACLK] $sys_100m_clk_source - -connect_bd_intf_net -intf_net axi_mem_interconnect_s03 [get_bd_intf_pins axi_mem_interconnect/S03_AXI] [get_bd_intf_pins axi_spdif_tx_dma/M_AXI_SG] -connect_bd_intf_net -intf_net axi_mem_interconnect_s04 [get_bd_intf_pins axi_mem_interconnect/S04_AXI] [get_bd_intf_pins axi_spdif_tx_dma/M_AXI_MM2S] -connect_bd_net -net sys_100m_resetn [get_bd_pins axi_mem_interconnect/S03_ARESETN] $sys_100m_resetn_source -connect_bd_net -net sys_100m_resetn [get_bd_pins axi_mem_interconnect/S04_ARESETN] $sys_100m_resetn_source -connect_bd_net -net sys_100m_clk [get_bd_pins axi_mem_interconnect/S03_ACLK] $sys_100m_clk_source -connect_bd_net -net sys_100m_clk [get_bd_pins axi_mem_interconnect/S04_ACLK] $sys_100m_clk_source - -connect_bd_net -net axi_spdif_tx_dma_mm2s_valid [get_bd_pins axi_spdif_tx_core/S_AXIS_TVALID] [get_bd_pins axi_spdif_tx_dma/m_axis_mm2s_tvalid] -connect_bd_net -net axi_spdif_tx_dma_mm2s_data [get_bd_pins axi_spdif_tx_core/S_AXIS_TDATA] [get_bd_pins axi_spdif_tx_dma/m_axis_mm2s_tdata] -connect_bd_net -net axi_spdif_tx_dma_mm2s_last [get_bd_pins axi_spdif_tx_core/S_AXIS_TLAST] [get_bd_pins axi_spdif_tx_dma/m_axis_mm2s_tlast] -connect_bd_net -net axi_spdif_tx_dma_mm2s_ready [get_bd_pins axi_spdif_tx_core/S_AXIS_TREADY] [get_bd_pins axi_spdif_tx_dma/m_axis_mm2s_tready] - - - -connect_bd_net -net sys_200m_clk [get_bd_pins sys_audio_clkgen/clk_in1] -connect_bd_net -net sys_100m_resetn [get_bd_pins sys_audio_clkgen/resetn] $sys_100m_resetn_source -connect_bd_net -net sys_audio_clkgen_clk [get_bd_pins sys_audio_clkgen/clk_out1] [get_bd_pins axi_spdif_tx_core/spdif_data_clk] -connect_bd_net -net spdif_s [get_bd_ports spdif] [get_bd_pins axi_spdif_tx_core/spdif_tx_o] +ad_connect axi_ethernet/s_axis_txd axi_ethernet_dma/M_AXIS_MM2S +ad_connect axi_ethernet/s_axis_txc axi_ethernet_dma/M_AXIS_CNTRL +ad_connect axi_ethernet/m_axis_rxd axi_ethernet_dma/S_AXIS_S2MM +ad_connect axi_ethernet/m_axis_rxs axi_ethernet_dma/S_AXIS_STS # address mapping -set sys_zynq 0 -set sys_mem_size 0x40000000 -set sys_addr_cntrl_space [get_bd_addr_spaces sys_mb/Data] +ad_cpu_interconnect 0x41400000 sys_mb_debug +ad_cpu_interconnect 0x40E00000 axi_ethernet +ad_cpu_interconnect 0x40010000 axi_gpio_lcd +ad_cpu_interconnect 0x41E10000 axi_ethernet_dma +ad_cpu_interconnect 0x41200000 axi_intc +ad_cpu_interconnect 0x41C00000 axi_timer +ad_cpu_interconnect 0x40600000 axi_uart +ad_cpu_interconnect 0x41600000 axi_iic_main +ad_cpu_interconnect 0x40000000 axi_gpio +ad_cpu_interconnect 0x44A70000 axi_spi -create_bd_addr_seg -range 0x00002000 -offset 0x00000000 [get_bd_addr_spaces sys_mb/Data] [get_bd_addr_segs sys_dlmb_cntlr/SLMB/Mem] SEG_data_dlmb_cntlr -create_bd_addr_seg -range 0x00001000 -offset 0x41400000 [get_bd_addr_spaces sys_mb/Data] [get_bd_addr_segs sys_mb_debug/S_AXI/Reg] SEG_data_mb_debug -create_bd_addr_seg -range 0x40000000 -offset 0x80000000 [get_bd_addr_spaces sys_mb/Data] [get_bd_addr_segs axi_ddr_cntrl/memmap/memaddr] SEG_data_ddr_cntrl -create_bd_addr_seg -range 0x00040000 -offset 0x40E00000 [get_bd_addr_spaces sys_mb/Data] [get_bd_addr_segs axi_ethernet/eth_buf/S_AXI/REG] SEG_data_ethernetlite -create_bd_addr_seg -range 0x00010000 -offset 0x41E10000 [get_bd_addr_spaces sys_mb/Data] [get_bd_addr_segs axi_ethernet_dma/S_AXI_LITE/Reg] SEG_data_ethernet_dma -create_bd_addr_seg -range 0x00010000 -offset 0x40010000 [get_bd_addr_spaces sys_mb/Data] [get_bd_addr_segs axi_gpio_lcd/s_axi/Reg] SEG_data_gpio_lcd -create_bd_addr_seg -range 0x00010000 -offset 0x40020000 [get_bd_addr_spaces sys_mb/Data] [get_bd_addr_segs axi_gpio_sw_led/s_axi/Reg] SEG_data_gpio_sw_led -create_bd_addr_seg -range 0x00010000 -offset 0x41200000 [get_bd_addr_spaces sys_mb/Data] [get_bd_addr_segs axi_intc/s_axi/Reg] SEG_data_intc -create_bd_addr_seg -range 0x00010000 -offset 0x41C00000 [get_bd_addr_spaces sys_mb/Data] [get_bd_addr_segs axi_timer/s_axi/Reg] SEG_data_timer -create_bd_addr_seg -range 0x00010000 -offset 0x40600000 [get_bd_addr_spaces sys_mb/Data] [get_bd_addr_segs axi_uart/s_axi/Reg] SEG_data_uart +ad_mem_hp0_interconnect sys_cpu_clk axi_ddr_cntrl/S_AXI +ad_mem_hp0_interconnect sys_cpu_clk sys_mb/M_AXI_DC +ad_mem_hp0_interconnect sys_cpu_clk sys_mb/M_AXI_IC +ad_mem_hp0_interconnect sys_cpu_clk axi_ethernet_dma/M_AXI_SG +ad_mem_hp0_interconnect sys_cpu_clk axi_ethernet_dma/M_AXI_MM2S +ad_mem_hp0_interconnect sys_cpu_clk axi_ethernet_dma/M_AXI_S2MM -create_bd_addr_seg -range 0x00010000 -offset 0x41600000 [get_bd_addr_spaces sys_mb/Data] [get_bd_addr_segs axi_iic_main/s_axi/Reg] SEG_data_iic -create_bd_addr_seg -range 0x00010000 -offset 0x79000000 [get_bd_addr_spaces sys_mb/Data] [get_bd_addr_segs axi_hdmi_clkgen/s_axi/axi_lite] SEG_data_hdmi_clkgen -create_bd_addr_seg -range 0x00010000 -offset 0x43000000 [get_bd_addr_spaces sys_mb/Data] [get_bd_addr_segs axi_hdmi_dma/S_AXI_LITE/Reg] SEG_data_hdmi_dma -create_bd_addr_seg -range 0x00010000 -offset 0x70e00000 [get_bd_addr_spaces sys_mb/Data] [get_bd_addr_segs axi_hdmi_core/s_axi/axi_lite] SEG_data_hdmi_core -create_bd_addr_seg -range 0x00010000 -offset 0x75c00000 [get_bd_addr_spaces sys_mb/Data] [get_bd_addr_segs axi_spdif_tx_core/S_AXI/reg0] SEG_data_spdif_tx_core -create_bd_addr_seg -range 0x00010000 -offset 0x41E00000 [get_bd_addr_spaces sys_mb/Data] [get_bd_addr_segs axi_spdif_tx_dma/S_AXI_LITE/Reg] SEG_data_spdif_tx_dma +create_bd_addr_seg -range 0x80000 -offset 0x0 [get_bd_addr_spaces sys_mb/Data] \ + [get_bd_addr_segs sys_dlmb_cntlr/SLMB/Mem] SEG_dlmb_cntlr +create_bd_addr_seg -range 0x80000 -offset 0x0 [get_bd_addr_spaces sys_mb/Instruction] \ + [get_bd_addr_segs sys_ilmb_cntlr/SLMB/Mem] SEG_ilmb_cntlr -create_bd_addr_seg -range 0x00002000 -offset 0x00000000 [get_bd_addr_spaces sys_mb/Instruction] [get_bd_addr_segs sys_ilmb_cntlr/SLMB/Mem] SEG_instr_ilmb_cntlr -create_bd_addr_seg -range 0x40000000 -offset 0x80000000 [get_bd_addr_spaces sys_mb/Instruction] [get_bd_addr_segs axi_ddr_cntrl/memmap/memaddr] SEG_instr_ddr_cntrl - -create_bd_addr_seg -range $sys_mem_size -offset 0x80000000 [get_bd_addr_spaces axi_hdmi_dma/Data_MM2S] [get_bd_addr_segs axi_ddr_cntrl/memmap/memaddr] SEG_axi_ddr_cntrl -create_bd_addr_seg -range $sys_mem_size -offset 0x80000000 [get_bd_addr_spaces axi_spdif_tx_dma/Data_SG] [get_bd_addr_segs axi_ddr_cntrl/memmap/memaddr] SEG_axi_ddr_cntrl -create_bd_addr_seg -range $sys_mem_size -offset 0x80000000 [get_bd_addr_spaces axi_spdif_tx_dma/Data_MM2S] [get_bd_addr_segs axi_ddr_cntrl/memmap/memaddr] SEG_axi_ddr_cntrl -create_bd_addr_seg -range $sys_mem_size -offset 0x80000000 [get_bd_addr_spaces axi_ethernet_dma/Data_SG] [get_bd_addr_segs axi_ddr_cntrl/memmap/memaddr] SEG_axi_ddr_cntrl -create_bd_addr_seg -range $sys_mem_size -offset 0x80000000 [get_bd_addr_spaces axi_ethernet_dma/Data_MM2S] [get_bd_addr_segs axi_ddr_cntrl/memmap/memaddr] SEG_axi_ddr_cntrl -create_bd_addr_seg -range $sys_mem_size -offset 0x80000000 [get_bd_addr_spaces axi_ethernet_dma/Data_S2MM] [get_bd_addr_segs axi_ddr_cntrl/memmap/memaddr] SEG_axi_ddr_cntrl - -create_bd_addr_seg -range 0x00001000 -offset 0x00000000 [get_bd_addr_spaces axi_ethernet/eth_buf/S_AXI_2TEMAC] [get_bd_addr_segs axi_ethernet/eth_mac/s_axi/Reg] SEG_eth_mac_reg diff --git a/projects/common/ac701/ac701_system_constr.xdc b/projects/common/ac701/ac701_system_constr.xdc index b192ff3b9..503e0ee30 100644 --- a/projects/common/ac701/ac701_system_constr.xdc +++ b/projects/common/ac701/ac701_system_constr.xdc @@ -49,19 +49,19 @@ set_property -dict {PACKAGE_PIN L22 IOSTANDARD LVCMOS33} [get_ports gpio_lc set_property -dict {PACKAGE_PIN M25 IOSTANDARD LVCMOS33} [get_ports gpio_lcd[2]] ; ## lcd_db[6] set_property -dict {PACKAGE_PIN M24 IOSTANDARD LVCMOS33} [get_ports gpio_lcd[1]] ; ## lcd_db[5] set_property -dict {PACKAGE_PIN L25 IOSTANDARD LVCMOS33} [get_ports gpio_lcd[0]] ; ## lcd_db[4] -set_property -dict {PACKAGE_PIN R8 IOSTANDARD SSTL15} [get_ports gpio_sw[0]] ; ## GPIO_DIP_SW0 -set_property -dict {PACKAGE_PIN P8 IOSTANDARD SSTL15} [get_ports gpio_sw[1]] ; ## GPIO_DIP_SW1 -set_property -dict {PACKAGE_PIN R7 IOSTANDARD SSTL15} [get_ports gpio_sw[2]] ; ## GPIO_DIP_SW2 -set_property -dict {PACKAGE_PIN R6 IOSTANDARD SSTL15} [get_ports gpio_sw[3]] ; ## GPIO_DIP_SW3 -set_property -dict {PACKAGE_PIN P6 IOSTANDARD LVCMOS15} [get_ports gpio_sw[4]] ; ## GPIO_SW_N -set_property -dict {PACKAGE_PIN U5 IOSTANDARD SSTL15} [get_ports gpio_sw[5]] ; ## GPIO_SW_E -set_property -dict {PACKAGE_PIN T5 IOSTANDARD SSTL15} [get_ports gpio_sw[6]] ; ## GPIO_SW_S -set_property -dict {PACKAGE_PIN R5 IOSTANDARD SSTL15} [get_ports gpio_sw[7]] ; ## GPIO_SW_W -set_property -dict {PACKAGE_PIN U6 IOSTANDARD SSTL15} [get_ports gpio_sw[8]] ; ## GPIO_SW_C -set_property -dict {PACKAGE_PIN M26 IOSTANDARD LVCMOS33} [get_ports gpio_led[0]] ; ## GPIO_LED_0_LS -set_property -dict {PACKAGE_PIN T24 IOSTANDARD LVCMOS33} [get_ports gpio_led[1]] ; ## GPIO_LED_1_LS -set_property -dict {PACKAGE_PIN T25 IOSTANDARD LVCMOS33} [get_ports gpio_led[2]] ; ## GPIO_LED_2_LS -set_property -dict {PACKAGE_PIN R26 IOSTANDARD LVCMOS33} [get_ports gpio_led[3]] ; ## GPIO_LED_3_LS +set_property -dict {PACKAGE_PIN R8 IOSTANDARD SSTL15} [get_ports gpio_bd[0]] ; ## GPIO_DIP_SW0 +set_property -dict {PACKAGE_PIN P8 IOSTANDARD SSTL15} [get_ports gpio_bd[1]] ; ## GPIO_DIP_SW1 +set_property -dict {PACKAGE_PIN R7 IOSTANDARD SSTL15} [get_ports gpio_bd[2]] ; ## GPIO_DIP_SW2 +set_property -dict {PACKAGE_PIN R6 IOSTANDARD SSTL15} [get_ports gpio_bd[3]] ; ## GPIO_DIP_SW3 +set_property -dict {PACKAGE_PIN P6 IOSTANDARD LVCMOS15} [get_ports gpio_bd[4]] ; ## GPIO_SW_N +set_property -dict {PACKAGE_PIN U5 IOSTANDARD SSTL15} [get_ports gpio_bd[5]] ; ## GPIO_SW_E +set_property -dict {PACKAGE_PIN T5 IOSTANDARD SSTL15} [get_ports gpio_bd[6]] ; ## GPIO_SW_S +set_property -dict {PACKAGE_PIN R5 IOSTANDARD SSTL15} [get_ports gpio_bd[7]] ; ## GPIO_SW_W +set_property -dict {PACKAGE_PIN U6 IOSTANDARD SSTL15} [get_ports gpio_bd[8]] ; ## GPIO_SW_C +set_property -dict {PACKAGE_PIN M26 IOSTANDARD LVCMOS33} [get_ports gpio_bd[9]] ; ## GPIO_LED_0_LS +set_property -dict {PACKAGE_PIN T24 IOSTANDARD LVCMOS33} [get_ports gpio_bd[10]] ; ## GPIO_LED_1_LS +set_property -dict {PACKAGE_PIN T25 IOSTANDARD LVCMOS33} [get_ports gpio_bd[11]] ; ## GPIO_LED_2_LS +set_property -dict {PACKAGE_PIN R26 IOSTANDARD LVCMOS33} [get_ports gpio_bd[12]] ; ## GPIO_LED_3_LS # iic @@ -69,37 +69,3 @@ set_property -dict {PACKAGE_PIN R17 IOSTANDARD LVCMOS33} [get_ports iic_rst set_property -dict {PACKAGE_PIN N18 IOSTANDARD LVCMOS33 DRIVE 8 SLEW SLOW} [get_ports iic_scl] set_property -dict {PACKAGE_PIN K25 IOSTANDARD LVCMOS33 DRIVE 8 SLEW SLOW} [get_ports iic_sda] -# hdmi - -set_property -dict {PACKAGE_PIN V21 IOSTANDARD LVCMOS18} [get_ports hdmi_out_clk] -set_property -dict {PACKAGE_PIN AA22 IOSTANDARD LVCMOS18} [get_ports hdmi_hsync] -set_property -dict {PACKAGE_PIN AC26 IOSTANDARD LVCMOS18} [get_ports hdmi_vsync] -set_property -dict {PACKAGE_PIN AB26 IOSTANDARD LVCMOS18} [get_ports hdmi_data_e] -set_property -dict {PACKAGE_PIN AA24 IOSTANDARD LVCMOS18} [get_ports hdmi_data[0]] -set_property -dict {PACKAGE_PIN Y25 IOSTANDARD LVCMOS18} [get_ports hdmi_data[1]] -set_property -dict {PACKAGE_PIN Y26 IOSTANDARD LVCMOS18} [get_ports hdmi_data[2]] -set_property -dict {PACKAGE_PIN V26 IOSTANDARD LVCMOS18} [get_ports hdmi_data[3]] -set_property -dict {PACKAGE_PIN W26 IOSTANDARD LVCMOS18} [get_ports hdmi_data[4]] -set_property -dict {PACKAGE_PIN W25 IOSTANDARD LVCMOS18} [get_ports hdmi_data[5]] -set_property -dict {PACKAGE_PIN W24 IOSTANDARD LVCMOS18} [get_ports hdmi_data[6]] -set_property -dict {PACKAGE_PIN U26 IOSTANDARD LVCMOS18} [get_ports hdmi_data[7]] -set_property -dict {PACKAGE_PIN U25 IOSTANDARD LVCMOS18} [get_ports hdmi_data[8]] -set_property -dict {PACKAGE_PIN V24 IOSTANDARD LVCMOS18} [get_ports hdmi_data[9]] -set_property -dict {PACKAGE_PIN U20 IOSTANDARD LVCMOS18} [get_ports hdmi_data[10]] -set_property -dict {PACKAGE_PIN W23 IOSTANDARD LVCMOS18} [get_ports hdmi_data[11]] -set_property -dict {PACKAGE_PIN W20 IOSTANDARD LVCMOS18} [get_ports hdmi_data[12]] -set_property -dict {PACKAGE_PIN U24 IOSTANDARD LVCMOS18} [get_ports hdmi_data[13]] -set_property -dict {PACKAGE_PIN Y20 IOSTANDARD LVCMOS18} [get_ports hdmi_data[14]] -set_property -dict {PACKAGE_PIN V23 IOSTANDARD LVCMOS18} [get_ports hdmi_data[15]] -set_property -dict {PACKAGE_PIN AA23 IOSTANDARD LVCMOS18} [get_ports hdmi_data[16]] -set_property -dict {PACKAGE_PIN AA25 IOSTANDARD LVCMOS18} [get_ports hdmi_data[17]] -set_property -dict {PACKAGE_PIN AB25 IOSTANDARD LVCMOS18} [get_ports hdmi_data[18]] -set_property -dict {PACKAGE_PIN AC24 IOSTANDARD LVCMOS18} [get_ports hdmi_data[19]] -set_property -dict {PACKAGE_PIN AB24 IOSTANDARD LVCMOS18} [get_ports hdmi_data[20]] -set_property -dict {PACKAGE_PIN Y22 IOSTANDARD LVCMOS18} [get_ports hdmi_data[21]] -set_property -dict {PACKAGE_PIN Y23 IOSTANDARD LVCMOS18} [get_ports hdmi_data[22]] -set_property -dict {PACKAGE_PIN V22 IOSTANDARD LVCMOS18} [get_ports hdmi_data[23]] - -# spdif - -set_property -dict {PACKAGE_PIN Y21 IOSTANDARD LVCMOS18} [get_ports spdif]