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usdrx1: Add DDR FIFO 

The converters on the usdrx1 generate 2.5GB/s. This more than we can
transport over the HP interconnects to the system memory.

Add a dedicated DDR FIFO to design which can be used to buffer the data
before it is transferred to the main memory.

Also increase the interconnect clock rate from 100MHz to 200MHz and the DMA
FIFO size from 4 to 8, so we can transfer the captured data faster to the
main memory.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
main
Lars-Peter Clausen 2015-09-01 10:42:06 +02:00
parent b73430d7ee
commit c00a6af4db
4 changed files with 99 additions and 10 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

30
projects/usdrx1/common/usdrx1_bd.tcl
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@ -80,18 +80,21 @@ set_property -dict [list CONFIG.PCORE_PMA_RSV {0x00018480}] $axi_usdrx1_gt
set_property -dict [list CONFIG.PCORE_RX_CDR_CFG {0x03000023ff20400020}] $axi_usdrx1_gt
set axi_usdrx1_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_usdrx1_dma]
set_property -dict [list CONFIG.C_DMA_TYPE_SRC {2}] $axi_usdrx1_dma
set_property -dict [list CONFIG.C_DMA_TYPE_SRC {1}] $axi_usdrx1_dma
set_property -dict [list CONFIG.C_DMA_TYPE_DEST {0}] $axi_usdrx1_dma
set_property -dict [list CONFIG.PCORE_ID {0}] $axi_usdrx1_dma
set_property -dict [list CONFIG.C_AXI_SLICE_SRC {0}] $axi_usdrx1_dma
set_property -dict [list CONFIG.C_AXI_SLICE_DEST {0}] $axi_usdrx1_dma
set_property -dict [list CONFIG.C_CLKS_ASYNC_DEST_REQ {1}] $axi_usdrx1_dma
set_property -dict [list CONFIG.C_CLKS_ASYNC_REQ_SRC {1}] $axi_usdrx1_dma
set_property -dict [list CONFIG.C_CLKS_ASYNC_SRC_DEST {0}] $axi_usdrx1_dma
set_property -dict [list CONFIG.C_SYNC_TRANSFER_START {0}] $axi_usdrx1_dma
set_property -dict [list CONFIG.C_DMA_LENGTH_WIDTH {24}] $axi_usdrx1_dma
set_property -dict [list CONFIG.C_2D_TRANSFER {0}] $axi_usdrx1_dma
set_property -dict [list CONFIG.C_CYCLIC {0}] $axi_usdrx1_dma
set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_SRC {512}] $axi_usdrx1_dma
set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_SRC {64}] $axi_usdrx1_dma
set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_DEST {64}] $axi_usdrx1_dma
set_property -dict [list CONFIG.C_FIFO_SIZE {8}] $axi_usdrx1_dma
set axi_usdrx1_spi [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_quad_spi:3.2 axi_usdrx1_spi]
set_property -dict [list CONFIG.C_USE_STARTUP {0}] $axi_usdrx1_spi
@ -201,7 +204,7 @@ ad_connect gt_rx_data_2 axi_ad9671_core_2/rx_data
ad_connect gt_rx_sof_2 axi_ad9671_core_2/rx_sof
ad_connect gt_rx_data_3 axi_ad9671_core_3/rx_data
ad_connect gt_rx_sof_3 axi_ad9671_core_3/rx_sof
ad_connect axi_ad9671_core_0/adc_clk axi_usdrx1_dma/fifo_wr_clk
ad_connect axi_ad9671_core_0/adc_clk usdrx1_fifo/adc_clk
ad_connect adc_data_0 axi_ad9671_core_0/adc_data
ad_connect adc_data_1 axi_ad9671_core_1/adc_data
ad_connect adc_data_2 axi_ad9671_core_2/adc_data
@ -218,9 +221,8 @@ ad_connect adc_dovf_0 axi_ad9671_core_0/adc_dovf
ad_connect adc_dovf_1 axi_ad9671_core_1/adc_dovf
ad_connect adc_dovf_2 axi_ad9671_core_2/adc_dovf
ad_connect adc_dovf_3 axi_ad9671_core_3/adc_dovf
ad_connect adc_wr_en axi_usdrx1_dma/fifo_wr_en
ad_connect adc_data axi_usdrx1_dma/fifo_wr_din
ad_connect adc_dovf axi_usdrx1_dma/fifo_wr_overflow
ad_connect adc_wr_en usdrx1_fifo/adc_wr
ad_connect adc_data usdrx1_fifo/adc_wdata
ad_connect axi_ad9671_adc_raddr axi_ad9671_core_0/adc_raddr_out
ad_connect axi_ad9671_adc_raddr axi_ad9671_core_1/adc_raddr_in
ad_connect axi_ad9671_adc_raddr axi_ad9671_core_2/adc_raddr_in
@ -230,6 +232,16 @@ ad_connect axi_ad9671_adc_sync axi_ad9671_core_1/adc_sync_in
ad_connect axi_ad9671_adc_sync axi_ad9671_core_2/adc_sync_in
ad_connect axi_ad9671_adc_sync axi_ad9671_core_3/adc_sync_in
ad_connect axi_usdrx1_gt/rx_rst usdrx1_fifo/adc_rst
ad_connect adc_dovf usdrx1_fifo/adc_wovf
ad_connect usdrx1_fifo/dma_wdata axi_usdrx1_dma/s_axis_data
ad_connect usdrx1_fifo/dma_wr axi_usdrx1_dma/s_axis_valid
ad_connect usdrx1_fifo/dma_wready axi_usdrx1_dma/s_axis_ready
ad_connect usdrx1_fifo/dma_xfer_req axi_usdrx1_dma/s_axis_xfer_req
ad_connect sys_200m_clk axi_usdrx1_dma/s_axis_aclk
ad_connect sys_200m_clk usdrx1_fifo/dma_clk
# address map
ad_cpu_interconnect 0x44A00000 axi_ad9671_core_0
@ -242,9 +254,9 @@ ad_cpu_interconnect 0x44A91000 axi_usdrx1_jesd
ad_cpu_interconnect 0x7c400000 axi_usdrx1_dma
ad_cpu_interconnect 0x7c420000 axi_usdrx1_spi
ad_mem_hp1_interconnect sys_cpu_clk sys_ps7/S_AXI_HP1
ad_mem_hp1_interconnect sys_cpu_clk axi_usdrx1_dma/m_dest_axi
ad_connect sys_cpu_resetn axi_usdrx1_dma/m_dest_axi_aresetn
ad_mem_hp2_interconnect sys_200m_clk sys_ps7/S_AXI_HP2
ad_mem_hp2_interconnect sys_200m_clk axi_usdrx1_dma/m_dest_axi
ad_connect sys_cpu_resetn axi_usdrx1_dma/m_dest_axi_aresetn
ad_mem_hp3_interconnect sys_cpu_clk sys_ps7/S_AXI_HP3
ad_mem_hp3_interconnect sys_cpu_clk axi_usdrx1_gt/m_axi

20
projects/usdrx1/zc706/system_bd.tcl
View File

@ -1,4 +1,22 @@
source $ad_hdl_dir/projects/common/zc706/zc706_system_bd.tcl
source ../common/usdrx1_bd.tcl
source $ad_hdl_dir/projects/common/zc706/zc706_system_plddr3.tcl
p_plddr3_fifo [current_bd_instance .] usdrx1_fifo 512
create_bd_port -dir I -type rst sys_rst
create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 ddr3
create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 sys_clk
set_property CONFIG.POLARITY ACTIVE_HIGH [get_bd_ports sys_rst]
ad_connect sys_rst usdrx1_fifo/sys_rst
ad_connect sys_clk usdrx1_fifo/sys_clk
ad_connect ddr3 usdrx1_fifo/ddr3
create_bd_addr_seg -range 0x40000000 -offset 0x80000000 \
[get_bd_addr_spaces usdrx1_fifo/axi_adcfifo/axi] \
[get_bd_addr_segs usdrx1_fifo/axi_ddr_cntrl/memmap/memaddr] \
SEG_axi_ddr_cntrl_memaddr
source ../common/usdrx1_bd.tcl

1
projects/usdrx1/zc706/system_project.tcl
View File

@ -10,6 +10,7 @@ adi_project_files usdrx1_zc706 [list \
"system_top.v" \
"system_constr.xdc" \
"../common/usdrx1_spi.v" \
"$ad_hdl_dir/projects/common/zc706/zc706_system_mig_constr.xdc" \
"$ad_hdl_dir/projects/common/zc706/zc706_system_constr.xdc" ]
adi_project_run usdrx1_zc706

58
projects/usdrx1/zc706/system_top.v
View File

@ -74,6 +74,26 @@ module system_top (
spdif,
sys_rst,
sys_clk_p,
sys_clk_n,
ddr3_addr,
ddr3_ba,
ddr3_cas_n,
ddr3_ck_n,
ddr3_ck_p,
ddr3_cke,
ddr3_cs_n,
ddr3_dm,
ddr3_dq,
ddr3_dqs_n,
ddr3_dqs_p,
ddr3_odt,
ddr3_ras_n,
ddr3_reset_n,
ddr3_we_n,
iic_scl,
iic_sda,
@ -152,6 +172,26 @@ module system_top (
output spdif;
input sys_rst;
input sys_clk_p;
input sys_clk_n;
output [13:0] ddr3_addr;
output [ 2:0] ddr3_ba;
output ddr3_cas_n;
output [ 0:0] ddr3_ck_n;
output [ 0:0] ddr3_ck_p;
output [ 0:0] ddr3_cke;
output [ 0:0] ddr3_cs_n;
output [ 7:0] ddr3_dm;
inout [63:0] ddr3_dq;
inout [ 7:0] ddr3_dqs_n;
inout [ 7:0] ddr3_dqs_p;
output [ 0:0] ddr3_odt;
output ddr3_ras_n;
output ddr3_reset_n;
output ddr3_we_n;
inout iic_scl;
inout iic_sda;
@ -360,6 +400,24 @@ module system_top (
endgenerate
system_wrapper i_system_wrapper (
.sys_clk_clk_n (sys_clk_n),
.sys_clk_clk_p (sys_clk_p),
.sys_rst (sys_rst),
.ddr3_addr (ddr3_addr),
.ddr3_ba (ddr3_ba),
.ddr3_cas_n (ddr3_cas_n),
.ddr3_ck_n (ddr3_ck_n),
.ddr3_ck_p (ddr3_ck_p),
.ddr3_cke (ddr3_cke),
.ddr3_cs_n (ddr3_cs_n),
.ddr3_dm (ddr3_dm),
.ddr3_dq (ddr3_dq),
.ddr3_dqs_n (ddr3_dqs_n),
.ddr3_dqs_p (ddr3_dqs_p),
.ddr3_odt (ddr3_odt),
.ddr3_ras_n (ddr3_ras_n),
.ddr3_reset_n (ddr3_reset_n),
.ddr3_we_n (ddr3_we_n),
.ddr_addr (ddr_addr),
.ddr_ba (ddr_ba),
.ddr_cas_n (ddr_cas_n),