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ad_tdd_sync/control: Update TDD logic 

+ Redesign the TDD counter FSM
+ Make the sync logic independent from the tdd control
main
Istvan Csomortani 2015-09-25 18:33:35 +03:00
parent 07e2d281c0
commit c03983ca54
3 changed files with 185 additions and 250 deletions
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17
library/axi_ad9361/axi_ad9361_tdd.v
View File

@ -196,8 +196,7 @@ module axi_ad9361_tdd (
wire [23:0] tdd_tx_off_2_s;
wire [23:0] tdd_tx_dp_on_2_s;
wire [23:0] tdd_tx_dp_off_2_s;
wire tdd_resync_s;
wire tdd_endof_frame_s;
wire tdd_sync_s;
wire [23:0] tdd_counter_status;
@ -293,8 +292,7 @@ module axi_ad9361_tdd (
.tdd_burst_count(tdd_burst_count_s),
.tdd_rx_only(tdd_rx_only_s),
.tdd_tx_only(tdd_tx_only_s),
.tdd_resync (tdd_resync_s),
.tdd_endof_frame (tdd_endof_frame_s),
.tdd_sync (tdd_sync_s),
.tdd_vco_rx_on_1(tdd_vco_rx_on_1_s),
.tdd_vco_rx_off_1(tdd_vco_rx_off_1_s),
.tdd_vco_tx_on_1(tdd_vco_tx_on_1_s),
@ -322,19 +320,16 @@ module axi_ad9361_tdd (
.tdd_tx_rf_en(tdd_tx_rf_en),
.tdd_counter_status(tdd_counter_status));
assign tdd_sync_t = ~tdd_terminal_type_s;
assign tdd_sync_s = (tdd_terminal_type_s) ? tdd_sync_o : tdd_sync_i;
ad_tdd_sync i_tdd_sync (
.clk(clk),
.rst(rst),
.sync_en(tdd_sync_enable_s),
.device_type(tdd_terminal_type_s),
.sync_period(tdd_sync_period_s),
.enable_in(tdd_enable_s),
.enable_out(tdd_enable_synced_s),
.sync_o(tdd_sync_o),
.sync_i(tdd_sync_i),
.sync_t(tdd_sync_t),
.resync(tdd_resync_s),
.endof_frame (tdd_endof_frame_s)
.sync(tdd_sync_o)
);
endmodule

322
library/common/ad_tdd_control.v
View File

@ -75,8 +75,7 @@ module ad_tdd_control(
tdd_tx_off_2,
tdd_tx_dp_on_2,
tdd_tx_dp_off_2,
tdd_resync,
tdd_endof_frame,
tdd_sync,
// TDD control signals
@ -128,8 +127,7 @@ module ad_tdd_control(
input [23:0] tdd_tx_off_2;
input [23:0] tdd_tx_dp_on_2;
input [23:0] tdd_tx_dp_off_2;
input tdd_resync;
output tdd_endof_frame;
input tdd_sync;
output tdd_tx_dp_en; // initiate vco tx2rx switch
output tdd_rx_vco_en; // initiate vco rx2tx switch
@ -152,7 +150,8 @@ module ad_tdd_control(
reg [23:0] tdd_counter = 24'h0;
reg [ 5:0] tdd_burst_counter = 6'h0;
reg tdd_counter_state = OFF;
reg tdd_cstate = OFF;
reg tdd_cstate_next = OFF;
reg counter_at_tdd_vco_rx_on_1 = 1'b0;
reg counter_at_tdd_vco_rx_off_1 = 1'b0;
@ -174,9 +173,15 @@ module ad_tdd_control(
reg counter_at_tdd_tx_off_2 = 1'b0;
reg counter_at_tdd_tx_dp_on_2 = 1'b0;
reg counter_at_tdd_tx_dp_off_2 = 1'b0;
reg tdd_endof_frame = 1'h0;
reg tdd_enable_d = 1'h0;
reg tdd_last_burst = 1'b0;
reg tdd_sync_d1 = 1'b0;
reg tdd_sync_d2 = 1'b0;
reg tdd_sync_d3 = 1'b0;
reg tdd_sync_pulse = 1'b00;
// internal signals
@ -201,61 +206,98 @@ module ad_tdd_control(
wire [23:0] tdd_tx_off_2_s;
wire [23:0] tdd_tx_dp_on_2_s;
wire [23:0] tdd_tx_dp_off_2_s;
wire tdd_endof_frame;
wire tdd_endof_burst;
wire tdd_txrx_only_en_s;
assign tdd_counter_status = tdd_counter;
// synchronization of tdd_sync
always @(posedge clk) begin
if (rst == 1'b1) begin
tdd_sync_d1 = 1'b0;
tdd_sync_d2 = 1'b0;
end else begin
tdd_sync_d1 <= tdd_sync;
tdd_sync_d2 <= tdd_sync_d1;
end
end
// edge detection circuit
always @(posedge clk) begin
if (rst == 1'b1) begin
tdd_sync_d3 <= 1'b1;
tdd_sync_pulse <= 1'b0;
end else begin
tdd_sync_d3 <= tdd_sync_d2;
tdd_sync_pulse <= (~tdd_sync_d3 & tdd_sync_d2) ? 1'b1 : 1'b0;
end
end
// ***************************************************************************
// tdd counter (state machine)
// ***************************************************************************
always @(posedge clk) begin
// sync reset
if (rst == 1'b1) begin
tdd_counter <= 24'h0;
tdd_counter_state <= OFF;
tdd_cstate <= OFF;
tdd_enable_d <= 0;
end else begin
tdd_cstate <= tdd_cstate_next;
tdd_enable_d <= tdd_enable;
end
end
// counter reset
if (tdd_enable == 1'b0) begin
tdd_counter_state <= OFF;
end else
always @* begin
tdd_cstate_next <= tdd_cstate;
// start counter on the positive edge of the tdd_enable
if ((tdd_enable == 1'b1) && (tdd_enable_d == 1'b0)) begin
tdd_counter <= tdd_counter_init;
tdd_burst_counter <= tdd_burst_count;
tdd_counter_state <= ON;
end else
// free running counter
if (tdd_counter_state == ON) begin
if (tdd_counter == tdd_frame_length) begin
tdd_endof_frame <= 1'b1;
tdd_counter <= 24'h0;
if (tdd_burst_counter > 1) begin // inside a burst
tdd_burst_counter <= tdd_burst_counter - 1;
tdd_counter_state <= ON;
end
else
if ( tdd_burst_counter == 1) begin // end of burst
tdd_burst_counter <= 6'h0;
tdd_counter_state <= OFF;
end
else begin // contiuous mode
tdd_burst_counter <= 6'h0;
tdd_counter_state <= ON;
end
end
else begin
tdd_endof_frame <= 1'b0;
tdd_counter <= (tdd_resync == 1'b1) ? 24'h0 : tdd_counter + 1;
case (tdd_cstate)
ON : begin
if ((tdd_enable == 1'b0) || (tdd_endof_burst == 1'b1)) begin
tdd_cstate_next <= OFF;
end
end
OFF : begin
if((tdd_enable == 1'b1) && (tdd_enable_d == 1'b0)) begin
tdd_cstate_next <= ON;
end
end
endcase
end
assign tdd_endof_frame = (tdd_counter == tdd_frame_length) ? 1'b1 : 1'b0;
assign tdd_endof_burst = ((tdd_last_burst == 1'b1) && (tdd_counter == tdd_frame_length)) ? 1'b1 : 1'b0;
// tdd free running counter
always @(posedge clk) begin
if (rst == 1'b1) begin
tdd_counter <= tdd_counter_init;
end else begin
if (tdd_cstate == ON) begin
if (tdd_sync_pulse == 1'b1) begin
tdd_counter <= 24'b0;
end else begin
tdd_counter <= (tdd_counter < tdd_frame_length) ? tdd_counter + 1 : 24'b0;
end
end else begin
tdd_counter <= tdd_counter_init;
end
end
end
// tdd burst counter
always @(posedge clk) begin
if (rst == 1'b1) begin
tdd_burst_counter <= tdd_burst_count;
end else begin
if (tdd_cstate == ON) begin
tdd_burst_counter <= ((tdd_burst_counter > 0) && (tdd_endof_frame == 1'b1)) ? tdd_burst_counter - 1 : tdd_burst_counter;
end else begin
tdd_burst_counter <= tdd_burst_count;
end
tdd_last_burst <= (tdd_burst_counter == 6'b1) ? 1'b1 : 1'b0;
end
end
@ -267,11 +309,9 @@ module ad_tdd_control(
always @(posedge clk) begin
if(rst == 1'b1) begin
counter_at_tdd_vco_rx_on_1 <= 1'b0;
end else
if(tdd_counter == tdd_vco_rx_on_1_s) begin
end else if(tdd_counter == tdd_vco_rx_on_1_s) begin
counter_at_tdd_vco_rx_on_1 <= 1'b1;
end
else begin
end else begin
counter_at_tdd_vco_rx_on_1 <= 1'b0;
end
end
@ -279,11 +319,9 @@ module ad_tdd_control(
always @(posedge clk) begin
if(rst == 1'b1) begin
counter_at_tdd_vco_rx_on_2 <= 1'b0;
end else
if((tdd_secondary == 1'b1) && (tdd_counter == tdd_vco_rx_on_2_s)) begin
end else if((tdd_secondary == 1'b1) && (tdd_counter == tdd_vco_rx_on_2_s)) begin
counter_at_tdd_vco_rx_on_2 <= 1'b1;
end
else begin
end else begin
counter_at_tdd_vco_rx_on_2 <= 1'b0;
end
end
@ -291,11 +329,9 @@ module ad_tdd_control(
always @(posedge clk) begin
if(rst == 1'b1) begin
counter_at_tdd_vco_rx_off_1 <= 1'b0;
end else
if(tdd_counter == tdd_vco_rx_off_1_s) begin
end else if(tdd_counter == tdd_vco_rx_off_1_s) begin
counter_at_tdd_vco_rx_off_1 <= 1'b1;
end
else begin
end else begin
counter_at_tdd_vco_rx_off_1 <= 1'b0;
end
end
@ -303,11 +339,9 @@ module ad_tdd_control(
always @(posedge clk) begin
if(rst == 1'b1) begin
counter_at_tdd_vco_rx_off_2 <= 1'b0;
end else
if((tdd_secondary == 1'b1) && (tdd_counter == tdd_vco_rx_off_2_s)) begin
end else if((tdd_secondary == 1'b1) && (tdd_counter == tdd_vco_rx_off_2_s)) begin
counter_at_tdd_vco_rx_off_2 <= 1'b1;
end
else begin
end else begin
counter_at_tdd_vco_rx_off_2 <= 1'b0;
end
end
@ -316,11 +350,9 @@ module ad_tdd_control(
always @(posedge clk) begin
if(rst == 1'b1) begin
counter_at_tdd_vco_tx_on_1 <= 1'b0;
end else
if(tdd_counter == tdd_vco_tx_on_1_s) begin
end else if(tdd_counter == tdd_vco_tx_on_1_s) begin
counter_at_tdd_vco_tx_on_1 <= 1'b1;
end
else begin
end else begin
counter_at_tdd_vco_tx_on_1 <= 1'b0;
end
end
@ -328,11 +360,9 @@ module ad_tdd_control(
always @(posedge clk) begin
if(rst == 1'b1) begin
counter_at_tdd_vco_tx_on_2 <= 1'b0;
end else
if((tdd_secondary == 1'b1) && (tdd_counter == tdd_vco_tx_on_2_s)) begin
end else if((tdd_secondary == 1'b1) && (tdd_counter == tdd_vco_tx_on_2_s)) begin
counter_at_tdd_vco_tx_on_2 <= 1'b1;
end
else begin
end else begin
counter_at_tdd_vco_tx_on_2 <= 1'b0;
end
end
@ -340,11 +370,9 @@ module ad_tdd_control(
always @(posedge clk) begin
if(rst == 1'b1) begin
counter_at_tdd_vco_tx_off_1 <= 1'b0;
end else
if(tdd_counter == tdd_vco_tx_off_1_s) begin
end else if(tdd_counter == tdd_vco_tx_off_1_s) begin
counter_at_tdd_vco_tx_off_1 <= 1'b1;
end
else begin
end else begin
counter_at_tdd_vco_tx_off_1 <= 1'b0;
end
end
@ -352,11 +380,9 @@ module ad_tdd_control(
always @(posedge clk) begin
if(rst == 1'b1) begin
counter_at_tdd_vco_tx_off_2 <= 1'b0;
end else
if((tdd_secondary == 1'b1) && (tdd_counter == tdd_vco_tx_off_2_s)) begin
end else if((tdd_secondary == 1'b1) && (tdd_counter == tdd_vco_tx_off_2_s)) begin
counter_at_tdd_vco_tx_off_2 <= 1'b1;
end
else begin
end else begin
counter_at_tdd_vco_tx_off_2 <= 1'b0;
end
end
@ -365,11 +391,9 @@ module ad_tdd_control(
always @(posedge clk) begin
if(rst == 1'b1) begin
counter_at_tdd_rx_on_1 <= 1'b0;
end else
if(tdd_counter == tdd_rx_on_1_s) begin
end else if(tdd_counter == tdd_rx_on_1_s) begin
counter_at_tdd_rx_on_1 <= 1'b1;
end
else begin
end else begin
counter_at_tdd_rx_on_1 <= 1'b0;
end
end
@ -377,11 +401,9 @@ module ad_tdd_control(
always @(posedge clk) begin
if(rst == 1'b1) begin
counter_at_tdd_rx_on_2 <= 1'b0;
end else
if((tdd_secondary == 1'b1) && (tdd_counter == tdd_rx_on_2_s)) begin
end else if((tdd_secondary == 1'b1) && (tdd_counter == tdd_rx_on_2_s)) begin
counter_at_tdd_rx_on_2 <= 1'b1;
end
else begin
end else begin
counter_at_tdd_rx_on_2 <= 1'b0;
end
end
@ -389,11 +411,9 @@ module ad_tdd_control(
always @(posedge clk) begin
if(rst == 1'b1) begin
counter_at_tdd_rx_off_1 <= 1'b0;
end else
if(tdd_counter == tdd_rx_off_1_s) begin
end else if(tdd_counter == tdd_rx_off_1_s) begin
counter_at_tdd_rx_off_1 <= 1'b1;
end
else begin
end else begin
counter_at_tdd_rx_off_1 <= 1'b0;
end
end
@ -401,11 +421,9 @@ module ad_tdd_control(
always @(posedge clk) begin
if(rst == 1'b1) begin
counter_at_tdd_rx_off_2 <= 1'b0;
end else
if((tdd_secondary == 1'b1) && (tdd_counter == tdd_rx_off_2_s)) begin
end else if((tdd_secondary == 1'b1) && (tdd_counter == tdd_rx_off_2_s)) begin
counter_at_tdd_rx_off_2 <= 1'b1;
end
else begin
end else begin
counter_at_tdd_rx_off_2 <= 1'b0;
end
end
@ -414,11 +432,9 @@ module ad_tdd_control(
always @(posedge clk) begin
if(rst == 1'b1) begin
counter_at_tdd_tx_on_1 <= 1'b0;
end else
if(tdd_counter == tdd_tx_on_1_s) begin
end else if(tdd_counter == tdd_tx_on_1_s) begin
counter_at_tdd_tx_on_1 <= 1'b1;
end
else begin
end else begin
counter_at_tdd_tx_on_1 <= 1'b0;
end
end
@ -426,11 +442,9 @@ module ad_tdd_control(
always @(posedge clk) begin
if(rst == 1'b1) begin
counter_at_tdd_tx_on_2 <= 1'b0;
end else
if((tdd_secondary == 1'b1) && (tdd_counter == tdd_tx_on_2_s)) begin
end else if((tdd_secondary == 1'b1) && (tdd_counter == tdd_tx_on_2_s)) begin
counter_at_tdd_tx_on_2 <= 1'b1;
end
else begin
end else begin
counter_at_tdd_tx_on_2 <= 1'b0;
end
end
@ -438,11 +452,9 @@ module ad_tdd_control(
always @(posedge clk) begin
if(rst == 1'b1) begin
counter_at_tdd_tx_off_1 <= 1'b0;
end else
if(tdd_counter == tdd_tx_off_1_s) begin
end else if(tdd_counter == tdd_tx_off_1_s) begin
counter_at_tdd_tx_off_1 <= 1'b1;
end
else begin
end else begin
counter_at_tdd_tx_off_1 <= 1'b0;
end
end
@ -450,11 +462,9 @@ module ad_tdd_control(
always @(posedge clk) begin
if(rst == 1'b1) begin
counter_at_tdd_tx_off_2 <= 1'b0;
end else
if((tdd_secondary == 1'b1) && (tdd_counter == tdd_tx_off_2_s)) begin
end else if((tdd_secondary == 1'b1) && (tdd_counter == tdd_tx_off_2_s)) begin
counter_at_tdd_tx_off_2 <= 1'b1;
end
else begin
end else begin
counter_at_tdd_tx_off_2 <= 1'b0;
end
end
@ -463,11 +473,9 @@ module ad_tdd_control(
always @(posedge clk) begin
if(rst == 1'b1) begin
counter_at_tdd_tx_dp_on_1 <= 1'b0;
end else
if(tdd_counter == tdd_tx_dp_on_1_s) begin
end else if(tdd_counter == tdd_tx_dp_on_1_s) begin
counter_at_tdd_tx_dp_on_1 <= 1'b1;
end
else begin
end else begin
counter_at_tdd_tx_dp_on_1 <= 1'b0;
end
end
@ -475,11 +483,9 @@ module ad_tdd_control(
always @(posedge clk) begin
if(rst == 1'b1) begin
counter_at_tdd_tx_dp_on_2 <= 1'b0;
end else
if((tdd_secondary == 1'b1) && (tdd_counter == tdd_tx_dp_on_2_s)) begin
end else if((tdd_secondary == 1'b1) && (tdd_counter == tdd_tx_dp_on_2_s)) begin
counter_at_tdd_tx_dp_on_2 <= 1'b1;
end
else begin
end else begin
counter_at_tdd_tx_dp_on_2 <= 1'b0;
end
end
@ -487,11 +493,9 @@ module ad_tdd_control(
always @(posedge clk) begin
if(rst == 1'b1) begin
counter_at_tdd_tx_dp_off_1 <= 1'b0;
end else
if(tdd_counter == tdd_tx_dp_off_1_s) begin
end else if(tdd_counter == tdd_tx_dp_off_1_s) begin
counter_at_tdd_tx_dp_off_1 <= 1'b1;
end
else begin
end else begin
counter_at_tdd_tx_dp_off_1 <= 1'b0;
end
end
@ -499,11 +503,9 @@ module ad_tdd_control(
always @(posedge clk) begin
if(rst == 1'b1) begin
counter_at_tdd_tx_dp_off_2 <= 1'b0;
end else
if((tdd_secondary == 1'b1) && (tdd_counter == tdd_tx_dp_off_2_s)) begin
end else if((tdd_secondary == 1'b1) && (tdd_counter == tdd_tx_dp_off_2_s)) begin
counter_at_tdd_tx_dp_off_2 <= 1'b1;
end
else begin
end else begin
counter_at_tdd_tx_dp_off_2 <= 1'b0;
end
end
@ -757,91 +759,71 @@ module ad_tdd_control(
assign tdd_txrx_only_en_s = tdd_tx_only ^ tdd_rx_only;
always @(posedge clk) begin
if((rst == 1'b1) && (tdd_resync == 1'b1)) begin
if((rst == 1'b1) || (tdd_sync_pulse == 1'b1)) begin
tdd_rx_vco_en <= 1'b0;
end
else if((tdd_counter_state == OFF) || (counter_at_tdd_vco_rx_off_1 == 1'b1) || (counter_at_tdd_vco_rx_off_2 == 1'b1)) begin
end else if((tdd_cstate == OFF) || (counter_at_tdd_vco_rx_off_1 == 1'b1) || (counter_at_tdd_vco_rx_off_2 == 1'b1)) begin
tdd_rx_vco_en <= 1'b0;
end
else if((tdd_counter_state == ON) && ((counter_at_tdd_vco_rx_on_1 == 1'b1) || (counter_at_tdd_vco_rx_on_2 == 1'b1))) begin
end else if((tdd_cstate == ON) && ((counter_at_tdd_vco_rx_on_1 == 1'b1) || (counter_at_tdd_vco_rx_on_2 == 1'b1))) begin
tdd_rx_vco_en <= 1'b1;
end
else if((tdd_counter_state == ON) && (tdd_txrx_only_en_s == 1'b1)) begin
end else if((tdd_cstate == ON) && (tdd_txrx_only_en_s == 1'b1)) begin
tdd_rx_vco_en <= tdd_rx_only;
end
else begin
end else begin
tdd_rx_vco_en <= tdd_rx_vco_en;
end
end
always @(posedge clk) begin
if((rst == 1'b1) && (tdd_resync == 1'b1)) begin
if((rst == 1'b1) || (tdd_sync_pulse == 1'b1)) begin
tdd_tx_vco_en <= 1'b0;
end
else if((tdd_counter_state == OFF) || (counter_at_tdd_vco_tx_off_1 == 1'b1) || (counter_at_tdd_vco_tx_off_2 == 1'b1)) begin
end else if((tdd_cstate == OFF) || (counter_at_tdd_vco_tx_off_1 == 1'b1) || (counter_at_tdd_vco_tx_off_2 == 1'b1)) begin
tdd_tx_vco_en <= 1'b0;
end
else if((tdd_counter_state == ON) && ((counter_at_tdd_vco_tx_on_1 == 1'b1) || (counter_at_tdd_vco_tx_on_2 == 1'b1))) begin
end else if((tdd_cstate == ON) && ((counter_at_tdd_vco_tx_on_1 == 1'b1) || (counter_at_tdd_vco_tx_on_2 == 1'b1))) begin
tdd_tx_vco_en <= 1'b1;
end
else if((tdd_counter_state == ON) && (tdd_txrx_only_en_s == 1'b1)) begin
end else if((tdd_cstate == ON) && (tdd_txrx_only_en_s == 1'b1)) begin
tdd_tx_vco_en <= tdd_tx_only;
end
else begin
end else begin
tdd_tx_vco_en <= tdd_tx_vco_en;
end
end
always @(posedge clk) begin
if((rst == 1'b1) && (tdd_resync == 1'b1)) begin
if((rst == 1'b1) || (tdd_sync_pulse == 1'b1)) begin
tdd_rx_rf_en <= 1'b0;
end
else if((tdd_counter_state == OFF) || (counter_at_tdd_rx_off_1 == 1'b1) || (counter_at_tdd_rx_off_2 == 1'b1)) begin
end else if((tdd_cstate == OFF) || (counter_at_tdd_rx_off_1 == 1'b1) || (counter_at_tdd_rx_off_2 == 1'b1)) begin
tdd_rx_rf_en <= 1'b0;
end
else if((tdd_counter_state == ON) && ((counter_at_tdd_rx_on_1 == 1'b1) || (counter_at_tdd_rx_on_2 == 1'b1))) begin
end else if((tdd_cstate == ON) && ((counter_at_tdd_rx_on_1 == 1'b1) || (counter_at_tdd_rx_on_2 == 1'b1))) begin
tdd_rx_rf_en <= 1'b1;
end
else if((tdd_counter_state == ON) && (tdd_txrx_only_en_s == 1'b1)) begin
end else if((tdd_cstate == ON) && (tdd_txrx_only_en_s == 1'b1)) begin
tdd_rx_rf_en <= tdd_rx_only;
end
else begin
end else begin
tdd_rx_rf_en <= tdd_rx_rf_en;
end
end
always @(posedge clk) begin
if((rst == 1'b1) && (tdd_resync == 1'b1)) begin
if((rst == 1'b1) || (tdd_sync_pulse == 1'b1)) begin
tdd_tx_rf_en <= 1'b0;
end
else if((tdd_counter_state == OFF) || (counter_at_tdd_tx_off_1 == 1'b1) || (counter_at_tdd_tx_off_2 == 1'b1)) begin
end else if((tdd_cstate == OFF) || (counter_at_tdd_tx_off_1 == 1'b1) || (counter_at_tdd_tx_off_2 == 1'b1)) begin
tdd_tx_rf_en <= 1'b0;
end
else if((tdd_counter_state == ON) && ((counter_at_tdd_tx_on_1 == 1'b1) || (counter_at_tdd_tx_on_2 == 1'b1))) begin
end else if((tdd_cstate == ON) && ((counter_at_tdd_tx_on_1 == 1'b1) || (counter_at_tdd_tx_on_2 == 1'b1))) begin
tdd_tx_rf_en <= 1'b1;
end
else if((tdd_counter_state == ON) && (tdd_txrx_only_en_s == 1'b1)) begin
end else if((tdd_cstate == ON) && (tdd_txrx_only_en_s == 1'b1)) begin
tdd_tx_rf_en <= tdd_tx_only;
end
else begin
end else begin
tdd_tx_rf_en <= tdd_tx_rf_en;
end
end
always @(posedge clk) begin
if((rst == 1'b1) && (tdd_resync == 1'b1)) begin
if((rst == 1'b1) || (tdd_sync_pulse == 1'b1)) begin
tdd_tx_dp_en <= 1'b0;
end
else if((tdd_counter_state == OFF) || (counter_at_tdd_tx_dp_off_1 == 1'b1) || (counter_at_tdd_tx_dp_off_2 == 1'b1)) begin
end else if((tdd_cstate == OFF) || (counter_at_tdd_tx_dp_off_1 == 1'b1) || (counter_at_tdd_tx_dp_off_2 == 1'b1)) begin
tdd_tx_dp_en <= 1'b0;
end
else if((tdd_counter_state == ON) && ((counter_at_tdd_tx_dp_on_1 == 1'b1) || (counter_at_tdd_tx_dp_on_2 == 1'b1))) begin
end else if((tdd_cstate == ON) && ((counter_at_tdd_tx_dp_on_1 == 1'b1) || (counter_at_tdd_tx_dp_on_2 == 1'b1))) begin
tdd_tx_dp_en <= 1'b1;
end
else if((tdd_counter_state == ON) && (tdd_txrx_only_en_s == 1'b1)) begin
end else if((tdd_cstate == ON) && (tdd_txrx_only_en_s == 1'b1)) begin
tdd_tx_dp_en <= tdd_tx_only;
end
else begin
end else begin
tdd_tx_dp_en <= tdd_tx_dp_en;
end
end

96
library/common/ad_tdd_sync.v
View File

@ -40,59 +40,35 @@
module ad_tdd_sync (
// clock & reset
clk,
clk, // system clock (100 Mhz)
rst,
// control signals
sync_en, // synchronization enabled
sync_en, // synchronization enabled
device_type, // master or slave
sync_period, // periodicity of the sync pulse,
endof_frame,
enable_in, // tdd enable signal asserted by software
enable_out, // synchronized tdd_enable
// sync interface
sync_o, // sync output
sync_i, // sync input
sync_t, // sync 3-state
resync // resync pulse for slave device
enable_in, // tdd enable signal asserted by software
enable_out, // synchronized tdd_enable
sync // re-synchronization signal
);
parameter TDD_SYNC_PERIOD = 100000000; // 1 second
input clk;
input rst;
input sync_en;
input device_type;
input [ 7:0] sync_period;
input endof_frame;
input enable_in;
output enable_out;
output sync_o;
input sync_i;
output sync_t;
output resync;
output sync;
// internal registers
reg enable_in_d = 1'b0;
reg sync = 1'b0;
reg enable_out = 1'b0;
reg enable_synced = 1'b0;
reg sync_i_d = 1'b0;
reg sync_o = 1'b0;
reg resync = 1'b0;
reg [ 7:0] frame_counter = 32'h0;
reg [ 2:0] pulse_counter = 3'h7;
reg pulse_en = 1'h0;
reg [31:0] sync_counter = 32'h0;
reg sync_pulse = 1'b0;
reg sync_period_eof = 1'b0;
// the sync module can be bypassed
@ -101,28 +77,19 @@ module ad_tdd_sync (
enable_out <= 1'b0;
end else begin
enable_out <= (sync_en) ? enable_synced : enable_in;
sync <= (sync_en) ? sync_pulse : 1'b0;
end
end
// sync pulse is generated at every posedge of enable_in
// OR after [sync_period] number of endof_frame
// a free running sync pulse generator
always @(posedge clk) begin
if (rst == 1) begin
enable_in_d <= 1'b0;
frame_counter <= 0;
pulse_en <= 0;
sync_counter <= 32'h0;
sync_period_eof <= 1'b0;
end else begin
enable_in_d <= enable_in;
if(endof_frame == 1) begin
frame_counter <= frame_counter + 1;
end
if((frame_counter == sync_period) || (~enable_in_d & enable_in == 1)) begin
frame_counter <= 1'b0;
pulse_en <= 1'b1;
end else begin
pulse_en <= 1'b0;
end
sync_counter <= (sync_counter < TDD_SYNC_PERIOD) ? (sync_counter + 1) : 32'b0;
sync_period_eof <= (sync_counter == TDD_SYNC_PERIOD) ? 1'b1 : 1'b0;
end
end
@ -131,33 +98,24 @@ module ad_tdd_sync (
always @(posedge clk) begin
if (rst == 1) begin
pulse_counter <= 0;
sync_o <= 0;
sync_pulse <= 0;
end else begin
if(pulse_en == 1'b1) begin
sync_o <= 1'b1;
pulse_counter <= (sync_pulse == 1'b1) ? pulse_counter + 1 : 3'h0;
if(sync_period_eof == 1'b1) begin
sync_pulse <= 1'b1;
end else if(pulse_counter == 3'h7) begin
sync_o <= 1'b0;
sync_pulse <= 1'b0;
end
pulse_counter <= (sync_o == 1'b1) ? pulse_counter + 1 : 3'h0;
end
end
assign sync_t = ~device_type;
// syncronize enalbe_in and generate resync for slave
// syncronize tdd_enalbe generated by software
always @(posedge clk) begin
sync_i_d <= sync_i;
if(device_type == 1'b1) begin
if (rst == 1'b1) begin
enable_synced <= 1'b0;
end else if (sync_period_eof == 1'b1) begin
enable_synced <= enable_in;
resync <= 1'b0;
end else begin
if (~sync_i_d & sync_i) begin
enable_synced <= enable_in;
resync <= 1'b1;
end else begin
resync <= 1'b0;
end
end
end