From c0a2ef1ac43ee4ea9f2d27feaccfa99aa5387798 Mon Sep 17 00:00:00 2001 From: Rejeesh Kutty Date: Tue, 20 Dec 2016 16:18:15 -0500 Subject: [PATCH] library- altera power up warnings --- library/altera/axi_adxcvr/axi_adxcvr_up.v | 2 +- library/common/ad_axi_ip_constr.sdc | 2 +- library/common/ad_axi_ip_constr.xdc | 2 +- library/common/up_adc_common.v | 4 ++-- 4 files changed, 5 insertions(+), 5 deletions(-) diff --git a/library/altera/axi_adxcvr/axi_adxcvr_up.v b/library/altera/axi_adxcvr/axi_adxcvr_up.v index 0ef6c3082..0980f19d8 100644 --- a/library/altera/axi_adxcvr/axi_adxcvr_up.v +++ b/library/altera/axi_adxcvr/axi_adxcvr_up.v @@ -73,7 +73,7 @@ module axi_adxcvr_up #( reg up_wreq_d = 'd0; reg [31:0] up_scratch = 'd0; reg up_resetn = 'd0; - reg [ 3:0] up_rst_cnt = 'd0; + reg [ 3:0] up_rst_cnt = 'd8; reg up_status_int = 'd0; reg up_rreq_d = 'd0; reg [31:0] up_rdata_d = 'd0; diff --git a/library/common/ad_axi_ip_constr.sdc b/library/common/ad_axi_ip_constr.sdc index 4decbe86e..40c5058dc 100644 --- a/library/common/ad_axi_ip_constr.sdc +++ b/library/common/ad_axi_ip_constr.sdc @@ -8,5 +8,5 @@ set_false_path -from [get_registers *up_xfer_status:i_xfer_status|d_xfer_data*] set_false_path -from [get_registers *up_clock_mon:i_clock_mon|d_count_toggle*] -to [get_registers *up_clock_mon:i_clock_mon|up_count_toggle_m1*] set_false_path -from [get_registers *up_clock_mon:i_clock_mon|d_count_hold*] -to [get_registers *up_clock_mon:i_clock_mon|up_d_count*] set_false_path -from [get_registers *up_clock_mon:i_clock_mon|up_count_toggle*] -to [get_registers *up_clock_mon:i_clock_mon|d_count_toggle_m1*] -set_false_path -from [get_registers *up_core_preset*] -to [get_registers *ad_rst:i_core_rst_reg|ad_rst_sync_m1*] +set_false_path -from [get_registers *up_*preset*] -to [get_registers *ad_rst:i_core_rst_reg|ad_rst_sync_m1*] diff --git a/library/common/ad_axi_ip_constr.xdc b/library/common/ad_axi_ip_constr.xdc index 8fccb8018..ee5cfc941 100644 --- a/library/common/ad_axi_ip_constr.xdc +++ b/library/common/ad_axi_ip_constr.xdc @@ -16,5 +16,5 @@ set_false_path -from [get_cells -hier -filter {name =~ *d_xfer_data* && I set_false_path -from [get_cells -hier -filter {name =~ *d_count_toggle_reg && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *up_count_toggle_m1_reg && IS_SEQUENTIAL}] set_false_path -from [get_cells -hier -filter {name =~ *d_count_hold* && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *up_d_count* && IS_SEQUENTIAL}] set_false_path -from [get_cells -hier -filter {name =~ *up_count_toggle_reg && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *d_count_toggle_m1_reg && IS_SEQUENTIAL}] -set_false_path -from [get_cells -hier -filter {name =~ *up_*preset_reg && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *ad_rst_sync_m1_reg && IS_SEQUENTIAL}] +set_false_path -from [get_cells -hier -filter {name =~ *up_*preset_reg && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *ad_rst_sync_m1_reg && IS_SEQUENTIAL}] diff --git a/library/common/up_adc_common.v b/library/common/up_adc_common.v index 8101fa038..baefdb905 100644 --- a/library/common/up_adc_common.v +++ b/library/common/up_adc_common.v @@ -108,8 +108,8 @@ module up_adc_common #( // internal registers - reg up_core_preset = 'd0; - reg up_mmcm_preset = 'd0; + reg up_core_preset = 'd1; + reg up_mmcm_preset = 'd1; reg up_wack_int = 'd0; reg [31:0] up_scratch = 'd0; reg up_mmcm_resetn = 'd0;