zcy
/
pluto_hdl_adi
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

library- altera power up warnings

main
Rejeesh Kutty 2016-12-20 16:18:15 -05:00
parent 3e57ff1fc5
commit c0a2ef1ac4
4 changed files with 5 additions and 5 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
library/altera/axi_adxcvr/axi_adxcvr_up.v
View File

@ -73,7 +73,7 @@ module axi_adxcvr_up #(
reg up_wreq_d = 'd0;
reg [31:0] up_scratch = 'd0;
reg up_resetn = 'd0;
reg [ 3:0] up_rst_cnt = 'd0;
reg [ 3:0] up_rst_cnt = 'd8;
reg up_status_int = 'd0;
reg up_rreq_d = 'd0;
reg [31:0] up_rdata_d = 'd0;

2
library/common/ad_axi_ip_constr.sdc
View File

@ -8,5 +8,5 @@ set_false_path -from [get_registers *up_xfer_status:i_xfer_status|d_xfer_data*]
set_false_path -from [get_registers *up_clock_mon:i_clock_mon|d_count_toggle*] -to [get_registers *up_clock_mon:i_clock_mon|up_count_toggle_m1*]
set_false_path -from [get_registers *up_clock_mon:i_clock_mon|d_count_hold*] -to [get_registers *up_clock_mon:i_clock_mon|up_d_count*]
set_false_path -from [get_registers *up_clock_mon:i_clock_mon|up_count_toggle*] -to [get_registers *up_clock_mon:i_clock_mon|d_count_toggle_m1*]
set_false_path -from [get_registers *up_core_preset*] -to [get_registers *ad_rst:i_core_rst_reg|ad_rst_sync_m1*]
set_false_path -from [get_registers *up_*preset*] -to [get_registers *ad_rst:i_core_rst_reg|ad_rst_sync_m1*]

2
library/common/ad_axi_ip_constr.xdc
View File

@ -16,5 +16,5 @@ set_false_path -from [get_cells -hier -filter {name =~ *d_xfer_data* && I
set_false_path -from [get_cells -hier -filter {name =~ *d_count_toggle_reg && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *up_count_toggle_m1_reg && IS_SEQUENTIAL}]
set_false_path -from [get_cells -hier -filter {name =~ *d_count_hold* && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *up_d_count* && IS_SEQUENTIAL}]
set_false_path -from [get_cells -hier -filter {name =~ *up_count_toggle_reg && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *d_count_toggle_m1_reg && IS_SEQUENTIAL}]
set_false_path -from [get_cells -hier -filter {name =~ *up_*preset_reg && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *ad_rst_sync_m1_reg && IS_SEQUENTIAL}]
set_false_path -from [get_cells -hier -filter {name =~ *up_*preset_reg && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *ad_rst_sync_m1_reg && IS_SEQUENTIAL}]

4
library/common/up_adc_common.v
View File

@ -108,8 +108,8 @@ module up_adc_common #(
// internal registers
reg up_core_preset = 'd0;
reg up_mmcm_preset = 'd0;
reg up_core_preset = 'd1;
reg up_mmcm_preset = 'd1;
reg up_wack_int = 'd0;
reg [31:0] up_scratch = 'd0;
reg up_mmcm_resetn = 'd0;