From c0ffdefe9dc624b9d5c23275c0a2616138994f0e Mon Sep 17 00:00:00 2001 From: StancaPop Date: Mon, 13 Nov 2023 18:04:31 +0200 Subject: [PATCH] docs: Add adaq7980 documentation --- docs/index.rst | 1 + .../adaq7980_sdz/adaq7980_sdz_hdl.svg | 2160 +++++++++++++++++ docs/projects/adaq7980_sdz/index.rst | 260 ++ 3 files changed, 2421 insertions(+) create mode 100644 docs/projects/adaq7980_sdz/adaq7980_sdz_hdl.svg create mode 100755 docs/projects/adaq7980_sdz/index.rst diff --git a/docs/index.rst b/docs/index.rst index b0bda7390..c3fb8634c 100755 --- a/docs/index.rst +++ b/docs/index.rst @@ -23,6 +23,7 @@ HDL Reference Designs AD7616-SDZ AD9081-FMCA-EBZ/AD9082-FMCA-EBZ AD9783-EBZ + ADAQ7980-SDZ .. role:: red .. role:: green diff --git a/docs/projects/adaq7980_sdz/adaq7980_sdz_hdl.svg b/docs/projects/adaq7980_sdz/adaq7980_sdz_hdl.svg new file mode 100644 index 000000000..003894d7b --- /dev/null +++ b/docs/projects/adaq7980_sdz/adaq7980_sdz_hdl.svg @@ -0,0 +1,2160 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + image/svg+xml + + + + + + + + + + + + + + + + + + + + + Ethernet + UART + DDRx + SPI + I2C + Interrupts + + Timer + + + MEMORY INTERCONNECT + Zed + + + + FMC CONNECTOR + + AXI_ADAQ7980_DMA + 80MHz + + + + ARM (Zynq) + Zynq SoC + + + + + + MISO/SDI + SPI ENGINE FRAMEWORK + CS + SCLK + + + + + + OFFLOAD + + INTER-CONNECT + + + EXECUTION + + AXI REGMAP + + + sys_clk = 100MHz + + + + + + + + AXI PWM GEN + + AXI CLKGEN + spi_clk = 160MHz + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 64b + + + 16b + trigger + + diff --git a/docs/projects/adaq7980_sdz/index.rst b/docs/projects/adaq7980_sdz/index.rst new file mode 100755 index 000000000..85d6ce72f --- /dev/null +++ b/docs/projects/adaq7980_sdz/index.rst @@ -0,0 +1,260 @@ +.. _adaq7980_sdz: + +ADAQ7980-SDZ HDL project +=============================================================================== + +Overview +------------------------------------------------------------------------------- + +The :adi:`ADAQ7980`/:adi:`ADAQ7988` are 16-bit analog-to-digital converter +(ADC) subsystems that integrate four common signal processing and conditioning +blocks into a system in package (SiP) design that supports a variety of +applications. These devices contain the most critical passive components, +eliminating many of the design challenges associated with traditional signal +chains that use successive approximation register (SAR) ADCs. These passive +components are crucial to achieving the specified device performance. + +The :adi:`ADAQ7980`/:adi:`ADAQ7988` contain a high accuracy, low power, +16-bit SAR ADC, a low power, high bandwidth, high input impedance ADC driver, +a low power, stable reference buffer, and an efficient power management block. +Housed within a tiny, 5 mm × 4 mm LGA package, these systems simplify the +design process for data acquisition systems. The level of system integration +of the :adi:`ADAQ7980`/:adi:`ADAQ7988` solves many design challenges, while +the devices still provide the flexibility of a configurable ADC driver feedback +loop to allow gain and/or common-mode adjustments. A set of four device +supplies provides optimal system performance; however, single-supply operation +is possible with minimal impact on device operating specifications. + +Using the SDI input, the SPI-compatible serial interface features the ability +to daisy-chain multiple devices on a single, 3-wire bus and provides an optional +busy indicator. The user interface is compatible with 1.8 V, 2.5 V, 3 V, or 5 V +logic. Specified operation of these devices is from −55°C to +125°C. + +Applications: + * Automated test equipment (ATE) + * Battery powered instrumentation + * Communications + * Data acquisition + * Process control + * Medical instruments + +Supported boards +------------------------------------------------------------------------------- + +- :adi:`EVAL-ADAQ7980 ` + +Supported devices +------------------------------------------------------------------------------- + +- :adi:`ADAQ7980` +- :adi:`ADAQ7988` + +Supported carriers +------------------------------------------------------------------------------- + +- :xilinx:`ZedBoard ` on FMC slot + +Block design +------------------------------------------------------------------------------- + +Block diagram +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +.. image:: adaq7980_sdz_hdl.svg + :width: 800 + :align: center + :alt: ADAQ7980_SDZ block diagram + +CPU/Memory interconnects addresses +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +=========================== ========== +Instance Address +=========================== ========== +axi_adaq7980_dma 0x44a30000 +spi_clkgen 0x44a70000 +spi_adaq7980_adc_axi_regmap 0x44a00000 +spi_trigger_gen 0x44b00000 +=========================== ========== + +I2C connections +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +.. list-table:: + :widths: 20 20 20 20 20 + :header-rows: 1 + + * - I2C type + - I2C manager instance + - Alias + - Address + - I2C subordinate + * - PL + - iic_fmc + - axi_iic_fmc + - 0x4162_0000 + - --- + * - PL + - iic_main + - axi_iic_main + - 0x4160_0000 + - --- + +SPI connections +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +.. list-table:: + :widths: 25 25 25 25 + :header-rows: 1 + + * - SPI type + - SPI manager instance + - SPI subordinate + - CS + * - PL + - axi_spi_engine + - adaq7980 + - 0 + +GPIOs +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +The Software GPIO number is calculated as follows: + +- Zynq-7000: if PS7 is used, then offset is 54 + +.. list-table:: + :widths: 25 25 25 25 + :header-rows: 2 + + * - GPIO signal + - Direction + - HDL GPIO EMIO + - Software GPIO + * - + - (from FPGA view) + - + - Zynq-7000 + * - adaq7980_rbuf_pf + - INOUT + - 41 + - 95 + * - adaq7980_ref_pd + - INOUT + - 40 + - 94 + * - adaq7980_gpio + - INOUT + - 39:32 + - 93:86 + +Interrupts +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +Below are the Programmable Logic interrupts used in this project. + +================ === ========== =========== +Instance name HDL Linux Zynq Actual Zynq +================ === ========== =========== +axi_adaq7980_dma 13 57 89 +spi_adaq7980 12 56 88 +================ === ========== =========== + +Building the HDL project +------------------------------------------------------------------------------- + +The design is built upon ADI's generic HDL reference design framework. +ADI does not distribute the bit/elf files of these projects so they +must be built from the sources available :git-hdl:`here `. To get the source +you must `clone `__ +the HDL repository, and then build the project as follows:. + +**Linux/Cygwin/WSL** + +.. code-block:: + :linenos: + + user@analog:~$ cd hdl/projects/adaq7980_sdz/zed + user@analog:~/hdl/projects/adaq7980_sdz/zed$ make + +A more comprehensive build guide can be found in the :ref:`build_hdl` user guide. + +Resources +------------------------------------------------------------------------------- + +Systems related +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +- :dokuwiki:`ADAQ7980 User guide ` +- :dokuwiki:`How to build No-OS ` + +Hardware related +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +- Product datasheet: :adi:`ADAQ7980`/:adi:`ADAQ7988` + +- `UG-1060, Evaluation Board User Guide `__ + +HDL related +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +- :git-hdl:`adaq7980_sdz HDL project ` +- :ref:`SPI_ENGINE ` + +.. list-table:: + :widths: 30 35 35 + :header-rows: 1 + + * - IP name + - Source code link + - Documentation link + * - AXI_CLKGEN + - :git-hdl:`library/axi_dmac ` + - :dokuwiki:`[Wiki] ` + * - AXI_DMAC + - :git-hdl:`library/axi_dmac ` + - :ref:`here ` + * - AXI_HDMI_TX + - :git-hdl:`library/axi_hdmi_tx ` + - :dokuwiki:`[Wiki] ` + * - AXI_I2S_ADI + - :git-hdl:`library/axi_i2s_adi ` + - --- + * - AXI_PWM_GEN + - :git-hdl:`library/axi_pwm_gen ` + - :dokuwiki:`[Wiki] ` + * - AXI_SPDIF_TX + - :git-hdl:`library/axi_spdif_tx ` + - --- + * - AXI_SPI_ENGINE + - :git-hdl:`library/spi_engine/axi_spi_engine ` + - :ref:`here ` + * - AXI_SYSID + - :git-hdl:`library/axi_sysid ` + - :dokuwiki:`[Wiki] ` + * - SPI_ENGINE_EXECUTION + - :git-hdl:`library/spi_engine/spi_engine_execution ` + - :ref:`here ` + * - SPI_ENGINE_INTERCONNECT + - :git-hdl:`library/spi_engine/spi_engine_interconnect ` + - :ref:`here ` + * - SPI_ENGINE_OFFLOAD + - :git-hdl:`library/spi_engine/spi_engine_offload ` + - :ref:`here ` + * - SYSID_ROM + - :git-hdl:`library/sysid_rom ` + - :dokuwiki:`[Wiki] ` + * - UTIL_I2C_MIXER + - :git-hdl:`library/util_i2c_mixer ` + - :ref:`here ` + +Software related +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +- :git-no-os:`No-OS project ` + +- :dokuwiki:`How to build No-OS ` + +.. include:: ../common/more_information.rst + +.. include:: ../common/support.rst