adrv9009_zu11eg_som: added i2s

projects/adrv9009_zu11eg_som/Makefile

@@ -14,6 +14,8 @@ M_DEPS += ../../library/xilinx/common/ad_iobuf.v
 M_DEPS += ../../library/jesd204/scripts/jesd204.tcl
 
 LIB_DEPS += axi_dmac
+LIB_DEPS += axi_i2s_adi
+LIB_DEPS += axi_clkgen
 LIB_DEPS += jesd204/ad_ip_jesd204_tpl_adc
 LIB_DEPS += jesd204/ad_ip_jesd204_tpl_dac
 LIB_DEPS += jesd204/axi_jesd204_rx

projects/adrv9009_zu11eg_som/carrier_bd.tcl

@@ -1,2 +1,88 @@
 
 add_files -fileset constrs_1 -norecurse ./carrier_constr.xdc
+
+create_bd_port -dir O -type clk i2s_mclk
+create_bd_intf_port -mode Master -vlnv analog.com:interface:i2s_rtl:1.0 i2s
+
+# 12.288MHz clk
+ad_ip_instance axi_clkgen sys_audio_clkgen
+ad_ip_parameter sys_audio_clkgen CONFIG.ID 6
+ad_ip_parameter sys_audio_clkgen CONFIG.CLKIN_PERIOD 10
+ad_ip_parameter sys_audio_clkgen CONFIG.VCO_DIV 2
+ad_ip_parameter sys_audio_clkgen CONFIG.VCO_MUL 21
+ad_ip_parameter sys_audio_clkgen CONFIG.CLK0_DIV 85.5
+
+ad_connect sys_cpu_clk sys_audio_clkgen/clk
+ad_connect sys_i2s_mclk sys_audio_clkgen/clk_0
+
+# i2s ip
+ad_ip_instance axi_i2s_adi axi_i2s_adi
+ad_ip_parameter axi_i2s_adi CONFIG.DMA_TYPE 0
+ad_ip_parameter axi_i2s_adi CONFIG.S_AXI_ADDRESS_WIDTH 32
+
+# dma
+ad_ip_instance axi_dmac i2s_tx_dma
+ad_ip_parameter i2s_tx_dma CONFIG.DMA_TYPE_SRC 0
+ad_ip_parameter i2s_tx_dma CONFIG.DMA_TYPE_DEST 1
+ad_ip_parameter i2s_tx_dma CONFIG.CYCLIC 1
+ad_ip_parameter i2s_tx_dma CONFIG.AXI_SLICE_SRC 0
+ad_ip_parameter i2s_tx_dma CONFIG.AXI_SLICE_DEST 0
+ad_ip_parameter i2s_tx_dma CONFIG.ASYNC_CLK_DEST_REQ 0
+ad_ip_parameter i2s_tx_dma CONFIG.ASYNC_CLK_SRC_DEST 0
+ad_ip_parameter i2s_tx_dma CONFIG.ASYNC_CLK_REQ_SRC 0
+ad_ip_parameter i2s_tx_dma CONFIG.DMA_2D_TRANSFER 0
+ad_ip_parameter i2s_tx_dma CONFIG.DMA_DATA_WIDTH_DEST 32
+ad_ip_parameter i2s_tx_dma CONFIG.DMA_DATA_WIDTH_SRC 64
+
+ad_ip_instance axi_dmac i2s_rx_dma
+ad_ip_parameter i2s_rx_dma CONFIG.DMA_TYPE_SRC 1
+ad_ip_parameter i2s_rx_dma CONFIG.DMA_TYPE_DEST 0
+ad_ip_parameter i2s_rx_dma CONFIG.CYCLIC 1
+ad_ip_parameter i2s_rx_dma CONFIG.AXI_SLICE_SRC 0
+ad_ip_parameter i2s_rx_dma CONFIG.AXI_SLICE_DEST 0
+ad_ip_parameter i2s_rx_dma CONFIG.ASYNC_CLK_DEST_REQ 0
+ad_ip_parameter i2s_rx_dma CONFIG.ASYNC_CLK_SRC_DEST 0
+ad_ip_parameter i2s_rx_dma CONFIG.ASYNC_CLK_REQ_SRC 0
+ad_ip_parameter i2s_rx_dma CONFIG.DMA_2D_TRANSFER 0
+ad_ip_parameter i2s_rx_dma CONFIG.DMA_DATA_WIDTH_DEST 64
+ad_ip_parameter i2s_rx_dma CONFIG.DMA_DATA_WIDTH_SRC 32
+
+# i2s connections
+ad_connect sys_cpu_clk axi_i2s_adi/s_axi_aclk
+ad_connect sys_cpu_clk axi_i2s_adi/s_axis_aclk
+ad_connect sys_cpu_clk axi_i2s_adi/m_axis_aclk
+ad_connect sys_cpu_resetn axi_i2s_adi/s_axi_aresetn
+ad_connect sys_cpu_resetn axi_i2s_adi/s_axis_aresetn
+ad_connect i2s_tx_dma/m_axis axi_i2s_adi/s_axis
+
+#ad_connect i2s_rx_dma/s_axis axi_i2s_adi/m_axis
+# not connecting tlast
+ad_connect i2s_rx_dma/s_axis_data axi_i2s_adi/m_axis_tdata
+ad_connect i2s_rx_dma/s_axis_valid axi_i2s_adi/m_axis_tvalid
+ad_connect i2s_rx_dma/s_axis_ready axi_i2s_adi/m_axis_tready
+ad_connect i2s axi_i2s_adi/I2S
+ad_connect sys_i2s_mclk axi_i2s_adi/data_clk_i
+ad_connect sys_i2s_mclk i2s_mclk
+
+ad_connect sys_cpu_clk i2s_tx_dma/s_axi_aclk
+ad_connect sys_cpu_clk i2s_tx_dma/m_src_axi_aclk
+ad_connect sys_cpu_clk i2s_tx_dma/m_axis_aclk
+ad_connect sys_cpu_resetn i2s_tx_dma/s_axi_aresetn
+ad_connect sys_cpu_resetn i2s_tx_dma/m_src_axi_aresetn
+ad_cpu_interrupt ps-6 mb-6 i2s_tx_dma/irq
+
+ad_connect sys_cpu_clk i2s_rx_dma/s_axi_aclk
+ad_connect sys_cpu_clk i2s_rx_dma/m_dest_axi_aclk
+ad_connect sys_cpu_clk i2s_rx_dma/s_axis_aclk
+ad_connect sys_cpu_resetn i2s_rx_dma/s_axi_aresetn
+ad_connect sys_cpu_resetn i2s_rx_dma/m_dest_axi_aresetn
+ad_cpu_interrupt ps-7 mb-7 i2s_rx_dma/irq
+
+# interconnect
+ad_cpu_interconnect 0x41000000 i2s_rx_dma
+ad_cpu_interconnect 0x41001000 i2s_tx_dma
+ad_cpu_interconnect 0x41010000 sys_audio_clkgen
+ad_cpu_interconnect 0x42000000 axi_i2s_adi
+
+ad_mem_hp0_interconnect sys_cpu_clk i2s_tx_dma/m_src_axi
+ad_mem_hp0_interconnect sys_cpu_clk i2s_rx_dma/m_dest_axi

projects/adrv9009_zu11eg_som/carrier_constr.xdc

@@ -1,10 +1,10 @@
 
 set_property -dict {PACKAGE_PIN  AT13 IOSTANDARD LVCMOS18} [get_ports fan_tach]
-set_property -dict {PACKAGE_PIN  AR13 IOSTANDARD LVCMOS18} [get_ports fan_pwrm]
+set_property -dict {PACKAGE_PIN  AR13 IOSTANDARD LVCMOS18} [get_ports fan_pwm]
 set_property -dict {PACKAGE_PIN  AR12 IOSTANDARD LVCMOS18} [get_ports i2s_sdata_in]
 set_property -dict {PACKAGE_PIN  AP12 IOSTANDARD LVCMOS18} [get_ports i2s_sdata_out]
 set_property -dict {PACKAGE_PIN  AP15 IOSTANDARD LVCMOS18} [get_ports i2s_mclk]
-set_property -dict {PACKAGE_PIN  AN16 IOSTANDARD LVCMOS18} [get_ports i2s_bclk]
+set_property -dict {PACKAGE_PIN  AR15 IOSTANDARD LVCMOS18} [get_ports i2s_bclk]
 set_property -dict {PACKAGE_PIN  AT10 IOSTANDARD LVCMOS18} [get_ports i2s_lrclk]
 set_property -dict {PACKAGE_PIN  AW12 IOSTANDARD LVCMOS18} [get_ports pmod0_d0]
 set_property -dict {PACKAGE_PIN  AV12 IOSTANDARD LVCMOS18} [get_ports pmod0_d1]

projects/adrv9009_zu11eg_som/system_top.v

@@ -38,7 +38,7 @@
 module system_top (
 
   output              fan_tach,
-  output              fan_pwrm,
+  output              fan_pwm,
   input               i2s_sdata_in,
   output              i2s_sdata_out,
   output              i2s_mclk,
@@ -341,7 +341,7 @@ module system_top (
               hmc7044_car_reset,  // 23
               resetb_ad9545,      // 22
               fan_tach,           // 21
-              fan_pwrm,           // 20
+              fan_pwm,           // 20
               pmod0_d7,           // 19
               pmod0_d6,           // 18
               pmod0_d5,           // 17
@@ -492,6 +492,11 @@ module system_top (
     .tx_sync_0 (tx_sync),
     .tx_sysref_0 (sysref_a),
     .dac_fifo_bypass(gpio_o[90]),
+    .i2s_bclk(i2s_bclk),
+    .i2s_lrclk(i2s_lrclk),
+    .i2s_mclk(i2s_mclk),
+    .i2s_sdata_in(i2s_sdata_in),
+    .i2s_sdata_out(i2s_sdata_out),
     .spi0_csn(spi_csn),
     .spi0_miso(spi0_miso),
     .spi0_mosi(spi_mosi),