usb_fx3: Added FIFO on the FX3 to Zynq path, between FX3 core and DMA core
parent
17cfdd6be9
commit
c1b7c5e77a
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@ -28,9 +28,16 @@ set_property -dict [list CONFIG.c_mm2s_burst_size {256}] $axi_usb_fx3_dma
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set_property -dict [list CONFIG.c_s2mm_burst_size {256}] $axi_usb_fx3_dma
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set_property -dict [list CONFIG.c_sg_length_width {16}] $axi_usb_fx3_dma
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ad_connect axi_usb_fx3_dma/S_AXIS_S2MM axi_usb_fx3/m_axis
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set usb_fx3_rx_axis_fifo [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:1.1 usb_fx3_rx_axis_fifo ]
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ad_connect axi_usb_fx3/s_axis axi_usb_fx3_dma/M_AXIS_MM2S
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ad_connect sys_cpu_clk usb_fx3_rx_axis_fifo/s_axis_aclk
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ad_connect sys_cpu_resetn usb_fx3_rx_axis_fifo/s_axis_aresetn
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ad_connect axi_usb_fx3/m_axis usb_fx3_rx_axis_fifo/S_AXIS
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ad_connect axi_usb_fx3_dma/S_AXIS_S2MM usb_fx3_rx_axis_fifo/M_AXIS
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ad_connect axi_uart/rx usb_fx3_uart_tx
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ad_connect axi_uart/tx usb_fx3_uart_rx
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@ -50,6 +57,7 @@ ad_connect axi_usb_fx3/slwr_n slwr_n
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ad_connect axi_usb_fx3/pktend_n pktend_n
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ad_connect axi_usb_fx3/epswitch_n epswitch_n
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ad_cpu_interrupt ps-13 mb-12 axi_usb_fx3/irq
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ad_cpu_interrupt ps-12 mb-13 axi_usb_fx3_dma/mm2s_introut
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ad_cpu_interrupt ps-11 mb-14 axi_usb_fx3_dma/s2mm_introut
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