From c1ba57f8084b7f3f3c856d63e6e8767f558b4369 Mon Sep 17 00:00:00 2001 From: Lars-Peter Clausen Date: Mon, 27 Mar 2017 16:53:38 +0200 Subject: [PATCH] m2k: Rework clocking domains At the moment the register map fabric and DMA system memory side are clocked by the 100MHz sys_cpu_clk. While this works fine that is a lot faster than the clock has to run. There are only a few 100 register map accesses per seconds at most and they are not on timing critical paths. The penalty from clocking them at a lower rate is negligible for the overall system performance. The maximum clock rate for the DMAs is determined by the throughput requirements. This is 200 Mbytes/s for the logic analyzer, pattern generator and each of the DAC DMAs and 400 Mbytes/s for the ADC DMA. The DMA datapath width is 64-bit so the required clock rates are 25MHz and 50MHz respectively. Some headroom is required to accommodate for occasional bubble cycles on the data bus and the difference in reference clocks for the converter and processing system. The sys_cpu_clk is reduced to 27.8MHz which is fast enough for all but the ADC DMA. For the ADC DMA a new clock domain running at 55.6 MHz is introduced. Signed-off-by: Lars-Peter Clausen --- projects/m2k/common/m2k_bd.tcl | 26 +++++++++++++++++------ projects/m2k/standalone/system_constr.xdc | 3 ++- 2 files changed, 21 insertions(+), 8 deletions(-) diff --git a/projects/m2k/common/m2k_bd.tcl b/projects/m2k/common/m2k_bd.tcl index ba50d99fb..4c6fd3a18 100644 --- a/projects/m2k/common/m2k_bd.tcl +++ b/projects/m2k/common/m2k_bd.tcl @@ -14,12 +14,18 @@ create_bd_port -dir I tx_clk create_bd_port -dir O txiq create_bd_port -dir O -from 11 -to 0 txd +# AXI control interface and logic analyzer DMA (FCLK0): 27.8 MHz # Logic analyzer (FCLK2): 100 MHz +# Converter DMA (FCLK3): 55.6 MHz set_property -dict [list CONFIG.PCW_EN_CLK2_PORT {1}] $sys_ps7 +set_property -dict [list CONFIG.PCW_EN_CLK3_PORT {1}] $sys_ps7 +set_property -dict [list CONFIG.PCW_FPGA0_PERIPHERAL_FREQMHZ {27.778}] $sys_ps7 set_property -dict [list CONFIG.PCW_FPGA2_PERIPHERAL_FREQMHZ {100.0}] $sys_ps7 +set_property -dict [list CONFIG.PCW_FPGA3_PERIPHERAL_FREQMHZ {55.556}] $sys_ps7 ad_connect logic_analyzer_clk sys_ps7/FCLK_CLK2 +ad_connect converter_dma_clk sys_ps7/FCLK_CLK3 set logic_analyzer [create_bd_cell -type ip -vlnv analog.com:user:axi_logic_analyzer:1.0 logic_analyzer] @@ -215,23 +221,29 @@ ad_cpu_interconnect 0x7C4c0000 adc_trigger ad_cpu_interconnect 0x7C500000 axi_adc_decimate ad_cpu_interconnect 0x7C5a0000 axi_dac_interpolate +# Logic analyzer DMA ad_connect sys_cpu_clk axi_rd_wr_combiner_logic/clk -ad_connect sys_cpu_clk axi_rd_wr_combiner_converter/clk ad_connect sys_cpu_clk logic_analyzer_dmac/m_dest_axi_aclk ad_connect sys_cpu_clk pattern_generator_dmac/m_src_axi_aclk -ad_connect sys_cpu_clk ad9963_adc_dmac/m_dest_axi_aclk -ad_connect sys_cpu_clk ad9963_dac_dmac_a/m_src_axi_aclk ad_connect logic_analyzer_dmac/m_dest_axi axi_rd_wr_combiner_logic/s_wr_axi ad_connect pattern_generator_dmac/m_src_axi axi_rd_wr_combiner_logic/s_rd_axi +ad_mem_hp1_interconnect sys_cpu_clk sys_ps7/S_AXI_HP1 +ad_mem_hp1_interconnect sys_cpu_clk axi_rd_wr_combiner_logic/m_axi + +# Converter DMA +ad_connect converter_dma_clk axi_rd_wr_combiner_converter/clk +ad_connect converter_dma_clk ad9963_adc_dmac/m_dest_axi_aclk +ad_connect converter_dma_clk ad9963_dac_dmac_a/m_src_axi_aclk + ad_connect ad9963_adc_dmac/m_dest_axi axi_rd_wr_combiner_converter/s_wr_axi ad_connect ad9963_dac_dmac_a/m_src_axi axi_rd_wr_combiner_converter/s_rd_axi -ad_mem_hp1_interconnect sys_cpu_clk sys_ps7/S_AXI_HP1 -ad_mem_hp1_interconnect sys_cpu_clk axi_rd_wr_combiner_logic/m_axi -ad_mem_hp2_interconnect sys_cpu_clk sys_ps7/S_AXI_HP2 -ad_mem_hp2_interconnect sys_cpu_clk axi_rd_wr_combiner_converter/m_axi +ad_mem_hp2_interconnect converter_dma_clk sys_ps7/S_AXI_HP2 +ad_mem_hp2_interconnect converter_dma_clk axi_rd_wr_combiner_converter/m_axi + +# Only 16-bit we can run at a slower clock ad_mem_hp3_interconnect sys_cpu_clk sys_ps7/S_AXI_HP3 ad_mem_hp3_interconnect sys_cpu_clk ad9963_dac_dmac_b/m_src_axi diff --git a/projects/m2k/standalone/system_constr.xdc b/projects/m2k/standalone/system_constr.xdc index 6e176aed4..ff760196a 100644 --- a/projects/m2k/standalone/system_constr.xdc +++ b/projects/m2k/standalone/system_constr.xdc @@ -67,9 +67,10 @@ create_clock -period 6.66 -name tx_clk [get_ports tx_clk] create_clock -period 12.500 -name trigger_clk [get_ports {trigger_bd[0]}] create_clock -period 12.500 -name data_clk [get_ports {data_bd[0]}] -create_clock -name clk_fpga_0 -period 10 [get_pins "i_system_wrapper/system_i/sys_ps7/inst/PS7_i/FCLKCLK[0]"] +create_clock -name clk_fpga_0 -period 36 [get_pins "i_system_wrapper/system_i/sys_ps7/inst/PS7_i/FCLKCLK[0]"] create_clock -name clk_fpga_1 -period 5 [get_pins "i_system_wrapper/system_i/sys_ps7/inst/PS7_i/FCLKCLK[1]"] create_clock -name clk_fpga_2 -period 10 [get_pins "i_system_wrapper/system_i/sys_ps7/inst/PS7_i/FCLKCLK[2]"] +create_clock -name clk_fpga_3 -period 18 [get_pins "i_system_wrapper/system_i/sys_ps7/inst/PS7_i/FCLKCLK[3]"] set_false_path -from [get_clocks data_clk] -to [get_pins {i_system_wrapper/system_i/logic_analyzer/inst/data_m1_reg[0]/D}] set_false_path -from [get_clocks trigger_clk] -to [get_pins {i_system_wrapper/system_i/logic_analyzer/inst/trigger_m1_reg[0]/D}]