fmcjesdadc1: a10gx
Rejeesh Kutty
parent
3f3ea5f99a
commit
c1bc1259a7
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####################################################################################
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####################################################################################
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## Copyright 2011(c) Analog Devices, Inc.
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## Auto-generated, do not modify!
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####################################################################################
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####################################################################################
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ifeq ($(NIOS2_MMU),)
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NIOS2_MMU := 1
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endif
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export ALT_NIOS_MMU_ENABLED := $(NIOS2_MMU)
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M_DEPS += system_top.v
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M_DEPS += system_qsys.tcl
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M_DEPS += system_project.tcl
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M_DEPS += system_constr.sdc
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M_DEPS += ../common/daq2_spi.v
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M_DEPS += ../common/daq2_qsys.tcl
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M_DEPS += ../../scripts/adi_tquest.tcl
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M_DEPS += ../../scripts/adi_project_alt.tcl
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M_DEPS += ../../scripts/adi_env.tcl
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M_DEPS += ../../common/a10gx/a10gx_system_qsys.tcl
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M_DEPS += ../../common/a10gx/a10gx_system_assign.tcl
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M_DEPS += ../../../library/altera/avl_adxcfg/avl_adxcfg.v
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M_DEPS += ../../../library/altera/avl_adxcfg/avl_adxcfg_hw.tcl
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M_DEPS += ../../../library/altera/avl_adxcvr/avl_adxcvr_hw.tcl
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M_DEPS += ../../../library/altera/axi_adxcvr/axi_adxcvr.v
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M_DEPS += ../../../library/altera/axi_adxcvr/axi_adxcvr_hw.tcl
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M_DEPS += ../../../library/altera/axi_adxcvr/axi_adxcvr_up.v
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M_DEPS += ../../../library/altera/common/ad_mul.v
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M_DEPS += ../../../library/altera/common/up_clock_mon_constr.sdc
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M_DEPS += ../../../library/altera/common/up_rst_constr.sdc
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M_DEPS += ../../../library/altera/common/up_xfer_cntrl_constr.sdc
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M_DEPS += ../../../library/altera/common/up_xfer_status_constr.sdc
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M_DEPS += ../../../library/axi_ad9144/axi_ad9144.v
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M_DEPS += ../../../library/axi_ad9144/axi_ad9144_channel.v
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M_DEPS += ../../../library/axi_ad9144/axi_ad9144_core.v
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M_DEPS += ../../../library/axi_ad9144/axi_ad9144_hw.tcl
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M_DEPS += ../../../library/axi_ad9144/axi_ad9144_if.v
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M_DEPS += ../../../library/axi_ad9680/axi_ad9680.v
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M_DEPS += ../../../library/axi_ad9680/axi_ad9680_channel.v
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M_DEPS += ../../../library/axi_ad9680/axi_ad9680_hw.tcl
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M_DEPS += ../../../library/axi_ad9680/axi_ad9680_if.v
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M_DEPS += ../../../library/axi_ad9680/axi_ad9680_pnmon.v
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M_DEPS += ../../../library/axi_dmac/2d_transfer.v
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M_DEPS += ../../../library/axi_dmac/address_generator.v
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M_DEPS += ../../../library/axi_dmac/axi_dmac.v
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M_DEPS += ../../../library/axi_dmac/axi_dmac_constr.sdc
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M_DEPS += ../../../library/axi_dmac/axi_dmac_hw.tcl
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M_DEPS += ../../../library/axi_dmac/axi_register_slice.v
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M_DEPS += ../../../library/axi_dmac/data_mover.v
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M_DEPS += ../../../library/axi_dmac/dest_axi_mm.v
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M_DEPS += ../../../library/axi_dmac/dest_axi_stream.v
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M_DEPS += ../../../library/axi_dmac/dest_fifo_inf.v
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M_DEPS += ../../../library/axi_dmac/inc_id.h
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M_DEPS += ../../../library/axi_dmac/request_arb.v
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M_DEPS += ../../../library/axi_dmac/request_generator.v
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M_DEPS += ../../../library/axi_dmac/resp.h
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M_DEPS += ../../../library/axi_dmac/response_generator.v
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M_DEPS += ../../../library/axi_dmac/response_handler.v
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M_DEPS += ../../../library/axi_dmac/splitter.v
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M_DEPS += ../../../library/axi_dmac/src_axi_mm.v
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M_DEPS += ../../../library/axi_dmac/src_axi_stream.v
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M_DEPS += ../../../library/axi_dmac/src_fifo_inf.v
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M_DEPS += ../../../library/common/ad_axis_inf_rx.v
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M_DEPS += ../../../library/common/ad_datafmt.v
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M_DEPS += ../../../library/common/ad_dds.v
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M_DEPS += ../../../library/common/ad_dds_1.v
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M_DEPS += ../../../library/common/ad_dds_sine.v
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M_DEPS += ../../../library/common/ad_pnmon.v
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M_DEPS += ../../../library/common/ad_rst.v
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M_DEPS += ../../../library/common/ad_xcvr_rx_if.v
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M_DEPS += ../../../library/common/up_adc_channel.v
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M_DEPS += ../../../library/common/up_adc_common.v
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M_DEPS += ../../../library/common/up_axi.v
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M_DEPS += ../../../library/common/up_clock_mon.v
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M_DEPS += ../../../library/common/up_dac_channel.v
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M_DEPS += ../../../library/common/up_dac_common.v
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M_DEPS += ../../../library/common/up_delay_cntrl.v
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M_DEPS += ../../../library/common/up_xfer_cntrl.v
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M_DEPS += ../../../library/common/up_xfer_status.v
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M_DEPS += ../../../library/scripts/adi_env.tcl
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M_DEPS += ../../../library/scripts/adi_ip_alt.tcl
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M_DEPS += ../../../library/util_adcfifo/util_adcfifo.v
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M_DEPS += ../../../library/util_adcfifo/util_adcfifo_constr.sdc
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M_DEPS += ../../../library/util_adcfifo/util_adcfifo_hw.tcl
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M_DEPS += ../../../library/util_axis_fifo/address_gray.v
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M_DEPS += ../../../library/util_axis_fifo/address_gray_pipelined.v
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M_DEPS += ../../../library/util_axis_fifo/address_sync.v
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M_DEPS += ../../../library/util_axis_fifo/util_axis_fifo.v
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M_DEPS += ../../../library/util_axis_resize/util_axis_resize.v
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M_DEPS += ../../../library/util_cdc/sync_bits.v
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M_DEPS += ../../../library/util_cdc/sync_gray.v
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M_DEPS += ../../../library/util_cpack/util_cpack.v
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M_DEPS += ../../../library/util_cpack/util_cpack_dsf.v
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M_DEPS += ../../../library/util_cpack/util_cpack_hw.tcl
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M_DEPS += ../../../library/util_cpack/util_cpack_mux.v
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M_DEPS += ../../../library/util_upack/util_upack.v
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M_DEPS += ../../../library/util_upack/util_upack_dmx.v
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M_DEPS += ../../../library/util_upack/util_upack_dsf.v
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M_DEPS += ../../../library/util_upack/util_upack_hw.tcl
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M_ALTERA := quartus_sh --64bit -t
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M_FLIST += *.log
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M_FLIST += *_INFO.txt
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M_FLIST += *_dump.txt
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M_FLIST += db
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M_FLIST += *.asm.rpt
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M_FLIST += *.done
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M_FLIST += *.eda.rpt
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M_FLIST += *.fit.*
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M_FLIST += *.map.*
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M_FLIST += *.sta.*
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M_FLIST += *.qsf
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M_FLIST += *.qpf
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M_FLIST += *.qws
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M_FLIST += *.sof
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M_FLIST += *.cdf
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M_FLIST += *.sld
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M_FLIST += *.qdf
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M_FLIST += hc_output
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M_FLIST += system_bd
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M_FLIST += hps_isw_handoff
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M_FLIST += hps_sdram_*.csv
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M_FLIST += *ddr3_*.csv
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M_FLIST += incremental_db
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M_FLIST += reconfig_mif
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M_FLIST += *.sopcinfo
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M_FLIST += *.jdi
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M_FLIST += *.pin
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M_FLIST += *_summary.csv
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M_FLIST += *.dpf
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.PHONY: all clean clean-all
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all: daq2_a10gx.sof
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clean:clean-all
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clean-all:
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rm -rf $(M_FLIST)
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daq2_a10gx.sof: $(M_DEPS)
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-rm -rf $(M_FLIST)
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$(M_ALTERA) system_project.tcl >> daq2_a10gx_quartus.log 2>&1
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####################################################################################
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####################################################################################
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@ -0,0 +1,11 @@
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create_clock -period "10.000 ns" -name sys_clk_100mhz [get_ports {sys_clk}]
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derive_pll_clocks
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derive_clock_uncertainty
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set_false_path -from [get_registers *altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out*]
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set_false_path -from [get_clocks {sys_clk_100mhz}] -through [get_nets *altera_jesd204*] -to [get_clocks *outclk0*]
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set_false_path -from [get_clocks *outclk0*] -through [get_nets *altera_jesd204*] -to [get_clocks {sys_clk_100mhz}]
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set_false_path -to [get_registers *altera_jesd204_rx_csr_inst|phy_csr_rx_pcfifo_full_latched*]
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@ -0,0 +1,100 @@
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source ../../scripts/adi_env.tcl
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source ../../scripts/adi_project_alt.tcl
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adi_project_altera daq2_a10gx
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source $ad_hdl_dir/projects/common/a10gx/a10gx_system_assign.tcl
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# files
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set_global_assignment -name VERILOG_FILE ../common/daq2_spi.v
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# lane interface
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set_location_assignment PIN_AJ8 -to rx_ref_clk ; ## B20 FMCA_GBTCLK1_M2C_P
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set_location_assignment PIN_AJ7 -to "rx_ref_clk(n)" ; ## B21 FMCA_GBTCLK1_M2C_N
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set_location_assignment PIN_AV5 -to rx_data[0] ; ## A10 FMCA_DP3_M2C_P
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set_location_assignment PIN_AV6 -to "rx_data[0](n)" ; ## A11 FMCA_DP3_M2C_N
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set_location_assignment PIN_AW7 -to rx_data[1] ; ## C06 FMCA_DP0_M2C_P
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set_location_assignment PIN_AW8 -to "rx_data[1](n)" ; ## C07 FMCA_DP0_M2C_N
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set_location_assignment PIN_AY5 -to rx_data[2] ; ## A06 FMCA_DP2_M2C_P
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set_location_assignment PIN_AY6 -to "rx_data[2](n)" ; ## A07 FMCA_DP2_M2C_N
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set_location_assignment PIN_BA7 -to rx_data[3] ; ## A02 FMCA_DP1_M2C_P
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set_location_assignment PIN_BA8 -to "rx_data[3](n)" ; ## A03 FMCA_DP1_M2C_N
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set_location_assignment PIN_AT10 -to rx_sync ; ## D08 FMCA_LA01_CC_P
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set_location_assignment PIN_AR11 -to "rx_sync(n)" ; ## D09 FMCA_LA01_CC_N
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set_location_assignment PIN_AR20 -to rx_sysref ; ## G09 FMCA_LA03_P
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set_location_assignment PIN_AR19 -to "rx_sysref(n)" ; ## G10 FMCA_LA03_N
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set_location_assignment PIN_AL8 -to tx_ref_clk ; ## D04 FMCA_GBTCLK0_M2C_P
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set_location_assignment PIN_AL7 -to "tx_ref_clk(n)" ; ## D05 FMCA_GBTCLK0_M2C_N
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set_location_assignment PIN_BC3 -to tx_data[0] ; ## A30 FMCA_DP3_C2M_P (tx_data_p[0])
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set_location_assignment PIN_BC4 -to "tx_data[0](n)" ; ## A31 FMCA_DP3_C2M_N (tx_data_n[0])
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set_location_assignment PIN_BC7 -to tx_data[1] ; ## C02 FMCA_DP0_C2M_P (tx_data_p[3])
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set_location_assignment PIN_BC8 -to "tx_data[1](n)" ; ## C03 FMCA_DP0_C2M_N (tx_data_n[3])
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set_location_assignment PIN_BB5 -to tx_data[2] ; ## A26 FMCA_DP2_C2M_P (tx_data_p[1])
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set_location_assignment PIN_BB6 -to "tx_data[2](n)" ; ## A27 FMCA_DP2_C2M_N (tx_data_n[1])
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set_location_assignment PIN_BD5 -to tx_data[3] ; ## A22 FMCA_DP1_C2M_P (tx_data_p[2])
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set_location_assignment PIN_BD6 -to "tx_data[3](n)" ; ## A23 FMCA_DP1_C2M_N (tx_data_n[2])
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set_location_assignment PIN_AR22 -to tx_sync ; ## H07 FMCA_LA02_P
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set_location_assignment PIN_AT22 -to "tx_sync(n)" ; ## H08 FMCA_LA02_N
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set_location_assignment PIN_AN20 -to tx_sysref ; ## H10 FMCA_LA04_P
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set_location_assignment PIN_AP19 -to "tx_sysref(n)" ; ## H11 FMCA_LA04_N
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set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to ref_clk
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set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to rx_data
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set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to tx_data
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set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to rx_data[0]
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set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to rx_data[1]
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set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to rx_data[2]
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set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to rx_data[3]
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set_instance_assignment -name IO_STANDARD LVDS -to rx_sync
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set_instance_assignment -name IO_STANDARD LVDS -to rx_sysref
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set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to rx_sysref
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set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to tx_data[0]
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set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to tx_data[1]
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set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to tx_data[2]
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set_instance_assignment -name IO_STANDARD "HIGH SPEED DIFFERENTIAL I/O" -to tx_data[3]
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set_instance_assignment -name IO_STANDARD LVDS -to tx_sync
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set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to tx_sync
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set_instance_assignment -name IO_STANDARD LVDS -to tx_sysref
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set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to tx_sysref
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set_instance_assignment -name XCVR_RECONFIG_GROUP xcvr_0 -to rx_data[0]
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set_instance_assignment -name XCVR_RECONFIG_GROUP xcvr_1 -to rx_data[1]
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set_instance_assignment -name XCVR_RECONFIG_GROUP xcvr_2 -to rx_data[2]
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set_instance_assignment -name XCVR_RECONFIG_GROUP xcvr_3 -to rx_data[3]
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set_instance_assignment -name XCVR_RECONFIG_GROUP xcvr_0 -to tx_data[0]
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set_instance_assignment -name XCVR_RECONFIG_GROUP xcvr_1 -to tx_data[1]
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set_instance_assignment -name XCVR_RECONFIG_GROUP xcvr_2 -to tx_data[2]
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set_instance_assignment -name XCVR_RECONFIG_GROUP xcvr_3 -to tx_data[3]
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# gpio
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set_location_assignment PIN_AT17 -to trig ; ## H13 FMCA_LA07_P
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set_location_assignment PIN_AU17 -to "trig(n)" ; ## H14 FMCA_LA07_N
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set_location_assignment PIN_AR14 -to adc_fdb ; ## H17 FMCA_LA11_N
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set_location_assignment PIN_AT14 -to adc_fda ; ## H16 FMCA_LA11_P
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set_location_assignment PIN_AR16 -to dac_irq ; ## G15 FMCA_LA12_P
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set_location_assignment PIN_AP17 -to clkd_status[1] ; ## D18 FMCA_LA13_N
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set_location_assignment PIN_AR17 -to clkd_status[0] ; ## D17 FMCA_LA13_P
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set_location_assignment PIN_AV14 -to adc_pd ; ## C10 FMCA_LA06_P
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set_location_assignment PIN_AP16 -to dac_txen ; ## G16 FMCA_LA12_N
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set_location_assignment PIN_AT15 -to dac_reset ; ## C15 FMCA_LA10_N
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set_location_assignment PIN_AP18 -to clkd_sync ; ## G12 FMCA_LA08_P
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set_instance_assignment -name IO_STANDARD LVDS -to trig
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# spi
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||||||
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set_location_assignment PIN_AV11 -to spi_csn_clk ; ## D11 FMCA_LA05_P
|
||||||
|
set_location_assignment PIN_AR15 -to spi_csn_dac ; ## C14 FMCA_LA10_P
|
||||||
|
set_location_assignment PIN_AV13 -to spi_csn_adc ; ## D15 FMCA_LA09_N
|
||||||
|
set_location_assignment PIN_AW11 -to spi_clk ; ## D12 FMCA_LA05_N
|
||||||
|
set_location_assignment PIN_AW13 -to spi_sdio ; ## D14 FMCA_LA09_P
|
||||||
|
set_location_assignment PIN_AN19 -to spi_dir ; ## G13 FMCA_LA08_N
|
||||||
|
|
||||||
|
execute_flow -compile
|
||||||
|
|
||||||
|
|
@ -0,0 +1,5 @@
|
||||||
|
|
||||||
|
source $ad_hdl_dir/projects/common/a10gx/a10gx_system_qsys.tcl
|
||||||
|
source ../common/daq2_qsys.tcl
|
||||||
|
|
||||||
|
|
||||||
|
|
@ -0,0 +1,227 @@
|
||||||
|
// ***************************************************************************
|
||||||
|
// ***************************************************************************
|
||||||
|
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
|
||||||
|
//
|
||||||
|
// In this HDL repository, there are many different and unique modules, consisting
|
||||||
|
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||||
|
// developed independently, and may be accompanied by separate and unique license
|
||||||
|
// terms.
|
||||||
|
//
|
||||||
|
// The user should read each of these license terms, and understand the
|
||||||
|
// freedoms and responsabilities that he or she has by using this source/core.
|
||||||
|
//
|
||||||
|
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||||
|
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||||
|
// A PARTICULAR PURPOSE.
|
||||||
|
//
|
||||||
|
// Redistribution and use of source or resulting binaries, with or without modification
|
||||||
|
// of this file, are permitted under one of the following two license terms:
|
||||||
|
//
|
||||||
|
// 1. The GNU General Public License version 2 as published by the
|
||||||
|
// Free Software Foundation, which can be found in the top level directory
|
||||||
|
// of this repository (LICENSE_GPL2), and also online at:
|
||||||
|
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
|
||||||
|
//
|
||||||
|
// OR
|
||||||
|
//
|
||||||
|
// 2. An ADI specific BSD license, which can be found in the top level directory
|
||||||
|
// of this repository (LICENSE_ADIBSD), and also on-line at:
|
||||||
|
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
|
||||||
|
// This will allow to generate bit files and not release the source code,
|
||||||
|
// as long as it attaches to an ADI device.
|
||||||
|
//
|
||||||
|
// ***************************************************************************
|
||||||
|
// ***************************************************************************
|
||||||
|
|
||||||
|
`timescale 1ns/100ps
|
||||||
|
|
||||||
|
module system_top (
|
||||||
|
|
||||||
|
// clock and resets
|
||||||
|
|
||||||
|
input sys_clk,
|
||||||
|
input sys_resetn,
|
||||||
|
|
||||||
|
// ddr3
|
||||||
|
|
||||||
|
output ddr3_clk_p,
|
||||||
|
output ddr3_clk_n,
|
||||||
|
output [ 14:0] ddr3_a,
|
||||||
|
output [ 2:0] ddr3_ba,
|
||||||
|
output ddr3_cke,
|
||||||
|
output ddr3_cs_n,
|
||||||
|
output ddr3_odt,
|
||||||
|
output ddr3_reset_n,
|
||||||
|
output ddr3_we_n,
|
||||||
|
output ddr3_ras_n,
|
||||||
|
output ddr3_cas_n,
|
||||||
|
inout [ 7:0] ddr3_dqs_p,
|
||||||
|
inout [ 7:0] ddr3_dqs_n,
|
||||||
|
inout [ 63:0] ddr3_dq,
|
||||||
|
output [ 7:0] ddr3_dm,
|
||||||
|
input ddr3_rzq,
|
||||||
|
input ddr3_ref_clk,
|
||||||
|
|
||||||
|
// ethernet
|
||||||
|
|
||||||
|
input eth_ref_clk,
|
||||||
|
input eth_rxd,
|
||||||
|
output eth_txd,
|
||||||
|
output eth_mdc,
|
||||||
|
inout eth_mdio,
|
||||||
|
output eth_resetn,
|
||||||
|
input eth_intn,
|
||||||
|
|
||||||
|
// board gpio
|
||||||
|
|
||||||
|
input [ 10:0] gpio_bd_i,
|
||||||
|
output [ 15:0] gpio_bd_o,
|
||||||
|
|
||||||
|
// lane interface
|
||||||
|
|
||||||
|
input rx_ref_clk,
|
||||||
|
input rx_sysref,
|
||||||
|
output rx_sync,
|
||||||
|
input [ 3:0] rx_data,
|
||||||
|
input tx_ref_clk,
|
||||||
|
input tx_sysref,
|
||||||
|
input tx_sync,
|
||||||
|
output [ 3:0] tx_data,
|
||||||
|
|
||||||
|
// gpio
|
||||||
|
|
||||||
|
input trig,
|
||||||
|
input adc_fdb,
|
||||||
|
input adc_fda,
|
||||||
|
input dac_irq,
|
||||||
|
input [ 1:0] clkd_status,
|
||||||
|
output adc_pd,
|
||||||
|
output dac_txen,
|
||||||
|
output dac_reset,
|
||||||
|
output clkd_sync,
|
||||||
|
|
||||||
|
// spi
|
||||||
|
|
||||||
|
output spi_csn_clk,
|
||||||
|
output spi_csn_dac,
|
||||||
|
output spi_csn_adc,
|
||||||
|
output spi_clk,
|
||||||
|
inout spi_sdio,
|
||||||
|
output spi_dir);
|
||||||
|
|
||||||
|
// internal signals
|
||||||
|
|
||||||
|
wire eth_reset;
|
||||||
|
wire eth_mdio_i;
|
||||||
|
wire eth_mdio_o;
|
||||||
|
wire eth_mdio_t;
|
||||||
|
wire [ 63:0] gpio_i;
|
||||||
|
wire [ 63:0] gpio_o;
|
||||||
|
wire spi_miso_s;
|
||||||
|
wire spi_mosi_s;
|
||||||
|
wire [ 7:0] spi_csn_s;
|
||||||
|
|
||||||
|
// daq2
|
||||||
|
|
||||||
|
assign spi_csn_adc = spi_csn_s[2];
|
||||||
|
assign spi_csn_dac = spi_csn_s[1];
|
||||||
|
assign spi_csn_clk = spi_csn_s[0];
|
||||||
|
|
||||||
|
daq2_spi i_daq2_spi (
|
||||||
|
.spi_csn (spi_csn_s[2:0]),
|
||||||
|
.spi_clk (spi_clk),
|
||||||
|
.spi_mosi (spi_mosi_s),
|
||||||
|
.spi_miso (spi_miso_s),
|
||||||
|
.spi_sdio (spi_sdio),
|
||||||
|
.spi_dir (spi_dir));
|
||||||
|
|
||||||
|
// gpio in & out are separate cores
|
||||||
|
|
||||||
|
assign gpio_i[63:44] = gpio_o[63:44];
|
||||||
|
assign gpio_i[43:43] = trig;
|
||||||
|
|
||||||
|
assign gpio_i[42:40] = gpio_o[42:40];
|
||||||
|
assign adc_pd = gpio_o[42];
|
||||||
|
assign dac_txen = gpio_o[41];
|
||||||
|
assign dac_reset = gpio_o[40];
|
||||||
|
|
||||||
|
assign gpio_i[39:39] = gpio_o[39];
|
||||||
|
|
||||||
|
assign gpio_i[38:38] = gpio_o[38];
|
||||||
|
assign clkd_sync = gpio_o[38];
|
||||||
|
|
||||||
|
assign gpio_i[37:37] = gpio_o[37];
|
||||||
|
assign gpio_i[36:36] = adc_fdb;
|
||||||
|
assign gpio_i[35:35] = adc_fda;
|
||||||
|
assign gpio_i[34:34] = dac_irq;
|
||||||
|
assign gpio_i[33:32] = clkd_status;
|
||||||
|
|
||||||
|
// board stuff
|
||||||
|
|
||||||
|
assign eth_resetn = ~eth_reset;
|
||||||
|
assign eth_mdio_i = eth_mdio;
|
||||||
|
assign eth_mdio = (eth_mdio_t == 1'b1) ? 1'bz : eth_mdio_o;
|
||||||
|
|
||||||
|
assign ddr3_a[14:12] = 3'd0;
|
||||||
|
|
||||||
|
assign gpio_i[31:27] = gpio_o[31:27];
|
||||||
|
assign gpio_i[26:16] = gpio_bd_i;
|
||||||
|
assign gpio_i[15: 0] = gpio_o[15:0];
|
||||||
|
|
||||||
|
assign gpio_bd_o = gpio_o[15:0];
|
||||||
|
|
||||||
|
system_bd i_system_bd (
|
||||||
|
.rx_data_0_rx_serial_data (rx_data[0]),
|
||||||
|
.rx_data_1_rx_serial_data (rx_data[1]),
|
||||||
|
.rx_data_2_rx_serial_data (rx_data[2]),
|
||||||
|
.rx_data_3_rx_serial_data (rx_data[3]),
|
||||||
|
.rx_ref_clk_clk (rx_ref_clk),
|
||||||
|
.rx_sync_export (rx_sync),
|
||||||
|
.rx_sysref_export (rx_sysref),
|
||||||
|
.sys_clk_clk (sys_clk),
|
||||||
|
.sys_ddr3_cntrl_mem_mem_ck (ddr3_clk_p),
|
||||||
|
.sys_ddr3_cntrl_mem_mem_ck_n (ddr3_clk_n),
|
||||||
|
.sys_ddr3_cntrl_mem_mem_a (ddr3_a[11:0]),
|
||||||
|
.sys_ddr3_cntrl_mem_mem_ba (ddr3_ba),
|
||||||
|
.sys_ddr3_cntrl_mem_mem_cke (ddr3_cke),
|
||||||
|
.sys_ddr3_cntrl_mem_mem_cs_n (ddr3_cs_n),
|
||||||
|
.sys_ddr3_cntrl_mem_mem_odt (ddr3_odt),
|
||||||
|
.sys_ddr3_cntrl_mem_mem_reset_n (ddr3_reset_n),
|
||||||
|
.sys_ddr3_cntrl_mem_mem_we_n (ddr3_we_n),
|
||||||
|
.sys_ddr3_cntrl_mem_mem_ras_n (ddr3_ras_n),
|
||||||
|
.sys_ddr3_cntrl_mem_mem_cas_n (ddr3_cas_n),
|
||||||
|
.sys_ddr3_cntrl_mem_mem_dqs (ddr3_dqs_p[7:0]),
|
||||||
|
.sys_ddr3_cntrl_mem_mem_dqs_n (ddr3_dqs_n[7:0]),
|
||||||
|
.sys_ddr3_cntrl_mem_mem_dq (ddr3_dq[63:0]),
|
||||||
|
.sys_ddr3_cntrl_mem_mem_dm (ddr3_dm[7:0]),
|
||||||
|
.sys_ddr3_cntrl_oct_oct_rzqin (ddr3_rzq),
|
||||||
|
.sys_ddr3_cntrl_pll_ref_clk_clk (ddr3_ref_clk),
|
||||||
|
.sys_ethernet_mdio_mdc (eth_mdc),
|
||||||
|
.sys_ethernet_mdio_mdio_in (eth_mdio_i),
|
||||||
|
.sys_ethernet_mdio_mdio_out (eth_mdio_o),
|
||||||
|
.sys_ethernet_mdio_mdio_oen (eth_mdio_t),
|
||||||
|
.sys_ethernet_ref_clk_clk (eth_ref_clk),
|
||||||
|
.sys_ethernet_reset_reset (eth_reset),
|
||||||
|
.sys_ethernet_sgmii_rxp_0 (eth_rxd),
|
||||||
|
.sys_ethernet_sgmii_txp_0 (eth_txd),
|
||||||
|
.sys_gpio_bd_in_port (gpio_i[31:0]),
|
||||||
|
.sys_gpio_bd_out_port (gpio_o[31:0]),
|
||||||
|
.sys_gpio_in_export (gpio_i[63:32]),
|
||||||
|
.sys_gpio_out_export (gpio_o[63:32]),
|
||||||
|
.sys_rst_reset_n (sys_resetn),
|
||||||
|
.sys_spi_MISO (spi_miso_s),
|
||||||
|
.sys_spi_MOSI (spi_mosi_s),
|
||||||
|
.sys_spi_SCLK (spi_clk),
|
||||||
|
.sys_spi_SS_n (spi_csn_s),
|
||||||
|
.tx_data_0_tx_serial_data (tx_data[0]),
|
||||||
|
.tx_data_1_tx_serial_data (tx_data[1]),
|
||||||
|
.tx_data_2_tx_serial_data (tx_data[2]),
|
||||||
|
.tx_data_3_tx_serial_data (tx_data[3]),
|
||||||
|
.tx_ref_clk_clk (tx_ref_clk),
|
||||||
|
.tx_sync_export (tx_sync),
|
||||||
|
.tx_sysref_export (tx_sysref));
|
||||||
|
|
||||||
|
endmodule
|
||||||
|
|
||||||
|
// ***************************************************************************
|
||||||
|
// ***************************************************************************
|
||||||
Loading…
Reference in New Issue