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data_offload: Fix fifo_dst_ready generation

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Istvan Csomortani 2021-03-19 08:09:42 +00:00 committed by Mihaita Nagy
parent 78999e154e
commit c27a0e4add
1 changed files with 3 additions and 3 deletions
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6
library/data_offload/data_offload.v
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@ -252,10 +252,8 @@ module data_offload #(
// interface) // interface)
generate generate
if (MEM_TYPE == 1'b1) begin if (MEM_TYPE == 1'b1) begin
assign fifo_dst_ready_int_s = fifo_dst_ready; assign dst_mem_valid_int_s = dst_mem_valid_s;
assign dst_mem_valid_int_s = dst_mem_valid_s & m_axis_ready;
end else begin end else begin
assign fifo_dst_ready_int_s = 1'b1;
// Compensate the 1 cycle READ latency of the BRAM // Compensate the 1 cycle READ latency of the BRAM
always @(posedge m_axis_aclk) begin always @(posedge m_axis_aclk) begin
dst_mem_valid_d <= dst_mem_valid_s; dst_mem_valid_d <= dst_mem_valid_s;
@ -264,6 +262,8 @@ module data_offload #(
end end
endgenerate endgenerate
assign fifo_dst_ready_int_s = fifo_dst_ready & m_axis_ready;
assign fifo_src_wdata = s_axis_data; assign fifo_src_wdata = s_axis_data;
assign fifo_dst_ren = dst_mem_valid_s; assign fifo_dst_ren = dst_mem_valid_s;