From c2d37b2db3078ffcca53f0352df832e692cbba76 Mon Sep 17 00:00:00 2001 From: Stanca Pop Date: Tue, 27 Jul 2021 16:06:13 +0300 Subject: [PATCH] pulsar_adc_pmdz: Initial commit --- projects/pulsar_adc_pmdz/Makefile | 7 + projects/pulsar_adc_pmdz/Readme.md | 38 +++++ .../common/pulsar_adc_pmdz_bd.tcl | 61 +++++++ projects/pulsar_adc_pmdz/coraz7s/Makefile | 27 +++ .../pulsar_adc_pmdz/coraz7s/system_bd.tcl | 11 ++ .../pulsar_adc_pmdz/coraz7s/system_constr.xdc | 20 +++ .../coraz7s/system_project.tcl | 15 ++ projects/pulsar_adc_pmdz/coraz7s/system_top.v | 161 ++++++++++++++++++ 8 files changed, 340 insertions(+) create mode 100644 projects/pulsar_adc_pmdz/Makefile create mode 100755 projects/pulsar_adc_pmdz/Readme.md create mode 100644 projects/pulsar_adc_pmdz/common/pulsar_adc_pmdz_bd.tcl create mode 100644 projects/pulsar_adc_pmdz/coraz7s/Makefile create mode 100644 projects/pulsar_adc_pmdz/coraz7s/system_bd.tcl create mode 100644 projects/pulsar_adc_pmdz/coraz7s/system_constr.xdc create mode 100755 projects/pulsar_adc_pmdz/coraz7s/system_project.tcl create mode 100644 projects/pulsar_adc_pmdz/coraz7s/system_top.v diff --git a/projects/pulsar_adc_pmdz/Makefile b/projects/pulsar_adc_pmdz/Makefile new file mode 100644 index 000000000..2458d9876 --- /dev/null +++ b/projects/pulsar_adc_pmdz/Makefile @@ -0,0 +1,7 @@ +#################################################################################### +## Copyright (c) 2018 - 2021 Analog Devices, Inc. +### SPDX short identifier: BSD-1-Clause +## Auto-generated, do not modify! +#################################################################################### + +include ../scripts/project-toplevel.mk diff --git a/projects/pulsar_adc_pmdz/Readme.md b/projects/pulsar_adc_pmdz/Readme.md new file mode 100755 index 000000000..659d1bba7 --- /dev/null +++ b/projects/pulsar_adc_pmdz/Readme.md @@ -0,0 +1,38 @@ +# PULSAR_ADC_PMDZ HDL Project + +Here are some pointers to help you: + * [Board Product Page](https://www.analog.com/eval-ad400x-fmcz) + * Parts : [AD7942: 14-Bit, 250 kSPS PulSAR, Pseudo Differential ADC in MSOP/LFCSP](https://www.analog.com/ad7942) + * Parts : [AD7946: 14-Bit, 500 kSPS PulSAR ADC in MSOP](https://www.analog.com/ad7946) + * Parts : [AD7988-1: 16-Bit Lower Power PulSAR ADCs in MSOP/LFCSP](https://www.analog.com/ad7988-1) + * Parts : [AD7685: 16-Bit, 250 kSPS PulSAR ADC in MSOP/QFN](https://www.analog.com/ad7685) + * Parts : [AD7687: 16-Bit, 1.5 LSB INL, 250 kSPS PulSAR Differential ADC in MSOP/QFN](https://www.analog.com/ad7687) + * Parts : [AD7691: 18-Bit, 1.5 LSB INL, 250 kSPS PulSAR Differential ADC in MSOP/QFN](https://www.analog.com/ad7691) + * Parts : [AD7686: 500 kSPS 16-BIT PulSAR A/D Converter in MSOP/QFN](https://www.analog.com/ad7686) + * Parts : [AD7688: 500 kSPS 16- BIT Differential PulSAR A/D Converter in µSOIC/QFN](https://www.analog.com/ad7688) + * Parts : [AD7693: 16-Bit, ±0.5 LSB, 500 kSPS PulSAR Differential A/D Converter in MSOP/QFN](https://www.analog.com/ad7693) + * Parts : [AD7988-5: 16-Bit Lower Power PulSAR ADCs in MSOP/LFCSP](https://www.analog.com/ad7988-5) + * Parts : [AD7980: 16-Bit, 1 MSPS, PulSAR ADC in MSOP/LFCSP](https://www.analog.com/ad7980) + * Parts : [AD7983: 16-Bit, 1.33 MSPS PulSAR ADC in MSOP/LFCSP](https://www.analog.com/ad7983) + * Parts : [AD7690: 18-Bit, 1.5 LSB INL, 400 kSPS PulSAR Differential ADC in MSOP/QFN](https://www.analog.com/ad7690) + * Project Doc: https://wiki.analog.com/resources/eval/10-lead-pulsar-adc-evaluation-board + * HDL Doc: https://wiki.analog.com/resources/eval/user-guides/pulsar_adc_pmods_hdl + * Linux Drivers: https://wiki.analog.com/resources/tools-software/linux-drivers/iio-adc/ad7476a + +## Supported parts + + * AD7942 + * AD7946 + * AD7988-1 + * AD7685 + * AD7687 + * AD7691 + * AD7686 + * AD7688 + * AD7693 + * AD7988-5 + * AD7980 + * AD7983 + * AD7690 + * AD7982 + * AD7984 diff --git a/projects/pulsar_adc_pmdz/common/pulsar_adc_pmdz_bd.tcl b/projects/pulsar_adc_pmdz/common/pulsar_adc_pmdz_bd.tcl new file mode 100644 index 000000000..7ef1b9118 --- /dev/null +++ b/projects/pulsar_adc_pmdz/common/pulsar_adc_pmdz_bd.tcl @@ -0,0 +1,61 @@ + +create_bd_intf_port -mode Master -vlnv analog.com:interface:spi_master_rtl:1.0 pulsar_adc_spi + +source $ad_hdl_dir/library/spi_engine/scripts/spi_engine.tcl + +set data_width 32 +set async_spi_clk 1 +set num_cs 1 +set num_sdi 1 +set sdi_delay 1 +set hier_spi_engine spi_pulsar_adc + +spi_engine_create $hier_spi_engine $data_width $async_spi_clk $num_cs $num_sdi $sdi_delay + +ad_ip_instance axi_clkgen spi_clkgen +ad_ip_parameter spi_clkgen CONFIG.CLK0_DIV 5 +ad_ip_parameter spi_clkgen CONFIG.VCO_DIV 1 +ad_ip_parameter spi_clkgen CONFIG.VCO_MUL 8 + +ad_ip_instance axi_pwm_gen pulsar_adc_trigger_gen +ad_ip_parameter pulsar_adc_trigger_gen CONFIG.PULSE_0_PERIOD 120 +ad_ip_parameter pulsar_adc_trigger_gen CONFIG.PULSE_0_WIDTH 1 + +# dma to receive data stream +ad_ip_instance axi_dmac axi_pulsar_adc_dma +ad_ip_parameter axi_pulsar_adc_dma CONFIG.DMA_TYPE_SRC 1 +ad_ip_parameter axi_pulsar_adc_dma CONFIG.DMA_TYPE_DEST 0 +ad_ip_parameter axi_pulsar_adc_dma CONFIG.CYCLIC 0 +ad_ip_parameter axi_pulsar_adc_dma CONFIG.SYNC_TRANSFER_START 0 +ad_ip_parameter axi_pulsar_adc_dma CONFIG.AXI_SLICE_SRC 0 +ad_ip_parameter axi_pulsar_adc_dma CONFIG.AXI_SLICE_DEST 1 +ad_ip_parameter axi_pulsar_adc_dma CONFIG.DMA_2D_TRANSFER 0 +ad_ip_parameter axi_pulsar_adc_dma CONFIG.DMA_DATA_WIDTH_SRC $data_width +ad_ip_parameter axi_pulsar_adc_dma CONFIG.DMA_DATA_WIDTH_DEST 64 + +ad_connect $sys_cpu_clk spi_clkgen/clk +ad_connect spi_clk spi_clkgen/clk_0 + +ad_connect spi_clk pulsar_adc_trigger_gen/ext_clk +ad_connect $sys_cpu_clk pulsar_adc_trigger_gen/s_axi_aclk +ad_connect sys_cpu_resetn pulsar_adc_trigger_gen/s_axi_aresetn +ad_connect pulsar_adc_trigger_gen/pwm_0 $hier_spi_engine/offload/trigger + +ad_connect axi_pulsar_adc_dma/s_axis spi_pulsar_adc/M_AXIS_SAMPLE +ad_connect spi_pulsar_adc/m_spi pulsar_adc_spi + +ad_connect $sys_cpu_clk spi_pulsar_adc/clk +ad_connect spi_clk spi_pulsar_adc/spi_clk +ad_connect spi_clk axi_pulsar_adc_dma/s_axis_aclk +ad_connect sys_cpu_resetn spi_pulsar_adc/resetn +ad_connect sys_cpu_resetn axi_pulsar_adc_dma/m_dest_axi_aresetn + +ad_cpu_interconnect 0x44a00000 spi_pulsar_adc/axi_regmap +ad_cpu_interconnect 0x44a30000 axi_pulsar_adc_dma +ad_cpu_interconnect 0x44a70000 spi_clkgen +ad_cpu_interconnect 0x44b00000 pulsar_adc_trigger_gen + +ad_cpu_interrupt "ps-13" "mb-13" axi_pulsar_adc_dma/irq +ad_cpu_interrupt "ps-12" "mb-12" /spi_pulsar_adc/irq + +ad_mem_hp0_interconnect sys_cpu_clk axi_pulsar_adc_dma/m_dest_axi diff --git a/projects/pulsar_adc_pmdz/coraz7s/Makefile b/projects/pulsar_adc_pmdz/coraz7s/Makefile new file mode 100644 index 000000000..0a6ee6af1 --- /dev/null +++ b/projects/pulsar_adc_pmdz/coraz7s/Makefile @@ -0,0 +1,27 @@ +#################################################################################### +## Copyright (c) 2018 - 2021 Analog Devices, Inc. +### SPDX short identifier: BSD-1-Clause +## Auto-generated, do not modify! +#################################################################################### + +PROJECT_NAME := pulsar_adc_pmdz_coraz7s + +M_DEPS += ../common/pulsar_adc_pmdz_bd.tcl +M_DEPS += ../../scripts/adi_pd.tcl +M_DEPS += ../../common/coraz7s/coraz7s_system_ps7.tcl +M_DEPS += ../../common/coraz7s/coraz7s_system_constr.xdc +M_DEPS += ../../common/coraz7s/coraz7s_system_bd.tcl +M_DEPS += ../../../library/spi_engine/scripts/spi_engine.tcl +M_DEPS += ../../../library/common/ad_iobuf.v + +LIB_DEPS += axi_clkgen +LIB_DEPS += axi_dmac +LIB_DEPS += axi_pwm_gen +LIB_DEPS += axi_sysid +LIB_DEPS += spi_engine/axi_spi_engine +LIB_DEPS += spi_engine/spi_engine_execution +LIB_DEPS += spi_engine/spi_engine_interconnect +LIB_DEPS += spi_engine/spi_engine_offload +LIB_DEPS += sysid_rom + +include ../../scripts/project-xilinx.mk diff --git a/projects/pulsar_adc_pmdz/coraz7s/system_bd.tcl b/projects/pulsar_adc_pmdz/coraz7s/system_bd.tcl new file mode 100644 index 000000000..e5367cba9 --- /dev/null +++ b/projects/pulsar_adc_pmdz/coraz7s/system_bd.tcl @@ -0,0 +1,11 @@ +source $ad_hdl_dir/projects/common/coraz7s/coraz7s_system_bd.tcl +source $ad_hdl_dir/projects/scripts/adi_pd.tcl +source ../common/pulsar_adc_pmdz_bd.tcl + +#system ID +ad_ip_parameter axi_sysid_0 CONFIG.ROM_ADDR_BITS 9 +ad_ip_parameter rom_sys_0 CONFIG.PATH_TO_FILE "[pwd]/mem_init_sys.txt" +ad_ip_parameter rom_sys_0 CONFIG.ROM_ADDR_BITS 9 + +sysid_gen_sys_init_file + diff --git a/projects/pulsar_adc_pmdz/coraz7s/system_constr.xdc b/projects/pulsar_adc_pmdz/coraz7s/system_constr.xdc new file mode 100644 index 000000000..c63b9312e --- /dev/null +++ b/projects/pulsar_adc_pmdz/coraz7s/system_constr.xdc @@ -0,0 +1,20 @@ + +# ad40xx_fmc SPI interface + +set_property -dict {PACKAGE_PIN Y19 IOSTANDARD LVCMOS33 IOB TRUE} [get_ports pulsar_adc_spi_sdo] ; ## PMOD JA [2] +set_property -dict {PACKAGE_PIN Y16 IOSTANDARD LVCMOS33 IOB TRUE} [get_ports pulsar_adc_spi_sdi] ; ## PMOD JA [1] +set_property -dict {PACKAGE_PIN Y17 IOSTANDARD LVCMOS33 IOB TRUE} [get_ports pulsar_adc_spi_sclk] ; ## PMOD JA [3] +set_property -dict {PACKAGE_PIN Y18 IOSTANDARD LVCMOS33 IOB TRUE} [get_ports pulsar_adc_spi_cs] ; ## PMOD JA [0] + +set_property -dict {PACKAGE_PIN U18 IOSTANDARD LVCMOS33} [get_ports pulsar_adc_spi_pd] ; ## PMOD JA [4] + +# rename auto-generated clock for SPIEngine to spi_clk - 160MHz +# NOTE: clk_fpga_0 is the first PL fabric clock, also called $sys_cpu_clk +create_generated_clock -name spi_clk -source [get_pins -filter name=~*CLKIN1 -of [get_cells -hier -filter name=~*spi_clkgen*i_mmcm]] -master_clock clk_fpga_0 [get_pins -filter name=~*CLKOUT0 -of [get_cells -hier -filter name=~*spi_clkgen*i_mmcm]] + +# relax the SDO path to help closing timing at high frequencies +set_multicycle_path -setup 8 -to [get_cells -hierarchical -filter {NAME=~*/data_sdo_shift_reg[*]}] -from [get_clocks spi_clk] +set_multicycle_path -hold 7 -to [get_cells -hierarchical -filter {NAME=~*/data_sdo_shift_reg[*]}] -from [get_clocks spi_clk] +set_multicycle_path -setup 8 -to [get_cells -hierarchical -filter {NAME=~*/execution/inst/left_aligned_reg*}] -from [get_clocks spi_clk] +set_multicycle_path -hold 7 -to [get_cells -hierarchical -filter {NAME=~*/execution/inst/left_aligned_reg*}] -from [get_clocks spi_clk] + diff --git a/projects/pulsar_adc_pmdz/coraz7s/system_project.tcl b/projects/pulsar_adc_pmdz/coraz7s/system_project.tcl new file mode 100755 index 000000000..85d3b7ab3 --- /dev/null +++ b/projects/pulsar_adc_pmdz/coraz7s/system_project.tcl @@ -0,0 +1,15 @@ + +source ../../scripts/adi_env.tcl +source $ad_hdl_dir/projects/scripts/adi_project_xilinx.tcl +source $ad_hdl_dir/projects/scripts/adi_board.tcl + +adi_project pulsar_adc_pmdz_coraz7s + +adi_project_files pulsar_adc_pmdz_coraz7s [list \ + "$ad_hdl_dir/library/common/ad_iobuf.v" \ + "system_top.v" \ + "system_constr.xdc" \ + "$ad_hdl_dir/projects/common/coraz7s/coraz7s_system_constr.xdc"] + +adi_project_run pulsar_adc_pmdz_coraz7s + diff --git a/projects/pulsar_adc_pmdz/coraz7s/system_top.v b/projects/pulsar_adc_pmdz/coraz7s/system_top.v new file mode 100644 index 000000000..8f372c420 --- /dev/null +++ b/projects/pulsar_adc_pmdz/coraz7s/system_top.v @@ -0,0 +1,161 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2018 - 2021 (c) Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsabilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module system_top ( + + inout [14:0] ddr_addr, + inout [ 2:0] ddr_ba, + inout ddr_cas_n, + inout ddr_ck_n, + inout ddr_ck_p, + inout ddr_cke, + inout ddr_cs_n, + inout [ 3:0] ddr_dm, + inout [31:0] ddr_dq, + inout [ 3:0] ddr_dqs_n, + inout [ 3:0] ddr_dqs_p, + inout ddr_odt, + inout ddr_ras_n, + inout ddr_reset_n, + inout ddr_we_n, + + inout fixed_io_ddr_vrn, + inout fixed_io_ddr_vrp, + inout [53:0] fixed_io_mio, + inout fixed_io_ps_clk, + inout fixed_io_ps_porb, + inout fixed_io_ps_srstb, + + output pulsar_adc_spi_cs, + output pulsar_adc_spi_sclk, + input pulsar_adc_spi_sdi, + output pulsar_adc_spi_sdo, + output pulsar_adc_spi_pd, + + inout [ 1:0] btn, + inout [ 5:0] led); + + // internal signals + + wire [63:0] gpio_i; + wire [63:0] gpio_o; + wire [63:0] gpio_t; + + // instantiations + + assign gpio_i[31:8] = gpio_o[31:8]; + assign gpio_i[63:33] = gpio_o[63:33]; + + ad_iobuf #( + .DATA_WIDTH(1) + ) i_admp_pd_iobuf ( + .dio_t(gpio_t[32]), + .dio_i(gpio_o[32]), + .dio_o(gpio_i[32]), + .dio_p(pulsar_adc_spi_pd)); + + ad_iobuf #( + .DATA_WIDTH(2) + ) i_iobuf_buttons ( + .dio_t(gpio_t[1:0]), + .dio_i(gpio_o[1:0]), + .dio_o(gpio_i[1:0]), + .dio_p(btn)); + + ad_iobuf #( + .DATA_WIDTH(6) + ) i_iobuf_leds ( + .dio_t(gpio_t[7:2]), + .dio_i(gpio_o[7:2]), + .dio_o(gpio_i[7:2]), + .dio_p(led)); + + system_wrapper i_system_wrapper ( + .ddr_addr (ddr_addr), + .ddr_ba (ddr_ba), + .ddr_cas_n (ddr_cas_n), + .ddr_ck_n (ddr_ck_n), + .ddr_ck_p (ddr_ck_p), + .ddr_cke (ddr_cke), + .ddr_cs_n (ddr_cs_n), + .ddr_dm (ddr_dm), + .ddr_dq (ddr_dq), + .ddr_dqs_n (ddr_dqs_n), + .ddr_dqs_p (ddr_dqs_p), + .ddr_odt (ddr_odt), + .ddr_ras_n (ddr_ras_n), + .ddr_reset_n (ddr_reset_n), + .ddr_we_n (ddr_we_n), + .fixed_io_ddr_vrn (fixed_io_ddr_vrn), + .fixed_io_ddr_vrp (fixed_io_ddr_vrp), + .fixed_io_mio (fixed_io_mio), + .fixed_io_ps_clk (fixed_io_ps_clk), + .fixed_io_ps_porb (fixed_io_ps_porb), + .fixed_io_ps_srstb (fixed_io_ps_srstb), + .gpio_i (gpio_i), + .gpio_o (gpio_o), + .gpio_t (gpio_t), + .spi0_clk_i (1'b0), + .spi0_clk_o (), + .spi0_csn_0_o (), + .spi0_csn_1_o (), + .spi0_csn_2_o (), + .spi0_csn_i (1'b1), + .spi0_sdi_i (1'b0), + .spi0_sdo_i (1'b0), + .spi0_sdo_o (), + .spi1_clk_i (1'b0), + .spi1_clk_o (), + .spi1_csn_0_o (), + .spi1_csn_1_o (), + .spi1_csn_2_o (), + .spi1_csn_i (1'b1), + .spi1_sdi_i (1'b0), + .spi1_sdo_i (1'b0), + .spi1_sdo_o (), + .pulsar_adc_spi_cs(pulsar_adc_spi_cs), + .pulsar_adc_spi_sclk(pulsar_adc_spi_sclk), + .pulsar_adc_spi_sdi(pulsar_adc_spi_sdi), + .pulsar_adc_spi_sdo(pulsar_adc_spi_sdo), + .pulsar_adc_spi_sdo_t(), + .pulsar_adc_spi_three_wire() + ); + +endmodule + +// *************************************************************************** +// ***************************************************************************