axi_hdmi_tx: es split
parent
3bca324c33
commit
c2e626d0b6
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@ -218,17 +218,6 @@ module axi_hdmi_tx_core (
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reg hdmi_es_hs_de = 'd0;
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reg hdmi_es_vs_de = 'd0;
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reg [15:0] hdmi_es_data = 'd0;
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reg hdmi_es_hs_de_d = 'd0;
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reg [15:0] hdmi_es_data_d = 'd0;
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reg hdmi_es_hs_de_2d = 'd0;
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reg [15:0] hdmi_es_data_2d = 'd0;
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reg hdmi_es_hs_de_3d = 'd0;
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reg [15:0] hdmi_es_data_3d = 'd0;
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reg hdmi_es_hs_de_4d = 'd0;
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reg [15:0] hdmi_es_data_4d = 'd0;
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reg hdmi_es_hs_de_5d = 'd0;
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reg [15:0] hdmi_es_data_5d = 'd0;
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reg [15:0] hdmi_es_data_6d = 'd0;
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// internal wires
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@ -258,8 +247,6 @@ module axi_hdmi_tx_core (
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wire hdmi_es_vs_de_s;
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wire hdmi_es_de_s;
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wire [15:0] hdmi_es_data_s;
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wire [15:0] hdmi_es_sav_s;
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wire [15:0] hdmi_es_eav_s;
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// binary to grey conversion
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@ -526,43 +513,6 @@ module axi_hdmi_tx_core (
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end
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end
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// hdmi embedded sync insertion
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assign hdmi_es_sav_s = (hdmi_es_vs_de == 1) ? 16'h8080 : 16'habab;
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assign hdmi_es_eav_s = (hdmi_es_vs_de == 1) ? 16'h9d9d : 16'hb6b6;
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always @(posedge hdmi_clk) begin
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hdmi_es_hs_de_d <= hdmi_es_hs_de;
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case ({hdmi_es_hs_de_4d, hdmi_es_hs_de_3d, hdmi_es_hs_de_2d,
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hdmi_es_hs_de_d, hdmi_es_hs_de})
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5'b10000: hdmi_es_data_d <= hdmi_es_eav_s;
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5'b11000: hdmi_es_data_d <= 16'h0000;
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5'b11100: hdmi_es_data_d <= 16'h0000;
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5'b11110: hdmi_es_data_d <= 16'hffff;
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default: hdmi_es_data_d <= hdmi_es_data;
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endcase
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hdmi_es_hs_de_2d <= hdmi_es_hs_de_d;
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hdmi_es_data_2d <= hdmi_es_data_d;
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hdmi_es_hs_de_3d <= hdmi_es_hs_de_2d;
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hdmi_es_data_3d <= hdmi_es_data_2d;
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hdmi_es_hs_de_4d <= hdmi_es_hs_de_3d;
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hdmi_es_data_4d <= hdmi_es_data_3d;
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hdmi_es_hs_de_5d <= hdmi_es_hs_de_4d;
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hdmi_es_data_5d <= hdmi_es_data_4d;
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case ({hdmi_es_hs_de_5d, hdmi_es_hs_de_4d, hdmi_es_hs_de_3d,
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hdmi_es_hs_de_2d, hdmi_es_hs_de_d})
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5'b01111: hdmi_es_data_6d <= hdmi_es_sav_s;
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5'b00111: hdmi_es_data_6d <= 16'h0000;
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5'b00011: hdmi_es_data_6d <= 16'h0000;
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5'b00001: hdmi_es_data_6d <= 16'hffff;
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default: hdmi_es_data_6d <= hdmi_es_data_5d;
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endcase
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end
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// es outputs
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assign hdmi_16_es_data = hdmi_es_data_6d;
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// data memory
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ad_mem #(.DATA_WIDTH(48), .ADDR_WIDTH(9)) i_mem (
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@ -609,6 +559,15 @@ module axi_hdmi_tx_core (
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hdmi_ss_data_e_s}),
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.s422_data (hdmi_ss_data_s));
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// embedded sync
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axi_hdmi_tx_es #(.DATA_WIDTH(16)) i_es (
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.hdmi_clk (hdmi_clk),
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.hdmi_hs_de (hdmi_es_hs_de),
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.hdmi_vs_de (hdmi_es_vs_de),
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.hdmi_data_de (hdmi_es_data),
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.hdmi_data (hdmi_16_es_data));
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endmodule
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// ***************************************************************************
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@ -0,0 +1,119 @@
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// ***************************************************************************
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// ***************************************************************************
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// Copyright 2011(c) Analog Devices, Inc.
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//
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without modification,
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// are permitted provided that the following conditions are met:
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// - Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// - Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in
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// the documentation and/or other materials provided with the
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// distribution.
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// - Neither the name of Analog Devices, Inc. nor the names of its
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// contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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// - The use of this software may or may not infringe the patent rights
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// of one or more patent holders. This license does not release you
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// from the requirement that you obtain separate licenses from these
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// patent holders to use this software.
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// - Use of the software either in source or binary form, must be run
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// on or directly connected to an Analog Devices Inc. component.
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//
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// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
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// PARTICULAR PURPOSE ARE DISCLAIMED.
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//
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// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
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// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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// Transmit HDMI, video dma data in, hdmi separate syncs data out.
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module axi_hdmi_tx_es (
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// hdmi interface
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hdmi_clk,
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hdmi_hs_de,
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hdmi_vs_de,
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hdmi_data_de,
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hdmi_data);
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// parameters
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parameter DATA_WIDTH = 32;
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localparam BYTE_WIDTH = DATA_WIDTH/8;
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// hdmi interface
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input hdmi_clk;
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input hdmi_hs_de = 'd0;
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input hdmi_vs_de = 'd0;
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input [(DATA_WIDTH-1):0] hdmi_data_de = 'd0;
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output [(DATA_WIDTH-1):0] hdmi_data = 'd0;
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// internal registers
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reg hdmi_hs_de_d = 'd0;
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reg [(DATA_WIDTH-1):0] hdmi_data_d = 'd0;
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reg hdmi_hs_de_2d = 'd0;
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reg [(DATA_WIDTH-1):0] hdmi_data_2d = 'd0;
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reg hdmi_hs_de_3d = 'd0;
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reg [(DATA_WIDTH-1):0] hdmi_data_3d = 'd0;
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reg hdmi_hs_de_4d = 'd0;
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reg [(DATA_WIDTH-1):0] hdmi_data_4d = 'd0;
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reg hdmi_hs_de_5d = 'd0;
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reg [(DATA_WIDTH-1):0] hdmi_data_5d = 'd0;
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reg [(DATA_WIDTH-1):0] hdmi_data = 'd0;
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// internal wires
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wire [(DATA_WIDTH-1):0] hdmi_sav_s;
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wire [(DATA_WIDTH-1):0] hdmi_eav_s;
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// hdmi embedded sync insertion
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assign hdmi_sav_s = (hdmi_vs_de == 1) ? {BYTE_WIDTH{8'h80}} : {BYTE_WIDTH{8'hab}};
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assign hdmi_eav_s = (hdmi_vs_de == 1) ? {BYTE_WIDTH{8'h9d}} : {BYTE_WIDTH{8'hb6}};
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always @(posedge hdmi_clk) begin
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hdmi_hs_de_d <= hdmi_hs_de;
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case ({hdmi_hs_de_4d, hdmi_hs_de_3d, hdmi_hs_de_2d,
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hdmi_hs_de_d, hdmi_hs_de})
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5'b11000: hdmi_data_d <= {BYTE_WIDTH{8'h00}};
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5'b11100: hdmi_data_d <= {BYTE_WIDTH{8'h00}};
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5'b11110: hdmi_data_d <= {BYTE_WIDTH{8'hff}};
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5'b10000: hdmi_data_d <= hdmi_eav_s;
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default: hdmi_data_d <= hdmi_data_de;
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endcase
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hdmi_hs_de_2d <= hdmi_hs_de_d;
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hdmi_data_2d <= hdmi_data_d;
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hdmi_hs_de_3d <= hdmi_hs_de_2d;
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hdmi_data_3d <= hdmi_data_2d;
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hdmi_hs_de_4d <= hdmi_hs_de_3d;
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hdmi_data_4d <= hdmi_data_3d;
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hdmi_hs_de_5d <= hdmi_hs_de_4d;
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hdmi_data_5d <= hdmi_data_4d;
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case ({hdmi_hs_de_5d, hdmi_hs_de_4d, hdmi_hs_de_3d,
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hdmi_hs_de_2d, hdmi_hs_de_d})
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5'b00111: hdmi_data <= {BYTE_WIDTH{8'h00}};
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5'b00011: hdmi_data <= {BYTE_WIDTH{8'h00}};
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5'b00001: hdmi_data <= {BYTE_WIDTH{8'hff}};
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5'b01111: hdmi_data <= hdmi_sav_s;
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default: hdmi_data <= hdmi_data_5d;
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endcase
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end
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endmodule
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// ***************************************************************************
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// ***************************************************************************
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@ -18,6 +18,7 @@ adi_ip_files axi_hdmi_tx [list \
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"$ad_hdl_dir/library/common/up_clock_mon.v" \
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"$ad_hdl_dir/library/common/up_hdmi_tx.v" \
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"axi_hdmi_tx_vdma.v" \
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"axi_hdmi_tx_es.v" \
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"axi_hdmi_tx_core.v" \
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"axi_hdmi_tx.v" \
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"axi_hdmi_tx_constr.xdc" ]
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