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daq2/a10gx- constraints remove 16.0

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Rejeesh Kutty 2017-05-16 10:09:30 -04:00
parent 0c5dabe358
commit c4b4bdc415
1 changed files with 11 additions and 50 deletions
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59
projects/daq2/a10gx/system_constr.sdc
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@ -1,59 +1,20 @@
create_clock -period "10.000 ns" -name sys_clk_100mhz [get_ports {sys_clk}]
create_clock -period "2.000 ns" -name rx_ref_clk_500mhz [get_ports {rx_ref_clk}]
create_clock -period "2.000 ns" -name tx_ref_clk_500mhz [get_ports {tx_ref_clk}]
derive_pll_clocks
derive_clock_uncertainty
set_false_path -from [get_clocks {sys_clk_100mhz}] -to [get_clocks {\
i_system_bd|sys_ddr3_cntrl_phy_clk_0 \
i_system_bd|sys_ddr3_cntrl_phy_clk_1 \
i_system_bd|sys_ddr3_cntrl_phy_clk_2 \
i_system_bd|sys_ddr3_cntrl_phy_clk_l_0 \
i_system_bd|sys_ddr3_cntrl_phy_clk_l_1 \
i_system_bd|sys_ddr3_cntrl_phy_clk_l_2}]
set_false_path -from [get_clocks {sys_clk_100mhz}] \
-to [get_clocks {i_system_bd|sys_ddr3_cntrl_core_nios_clk}]
set_false_path -from [get_clocks {sys_clk_100mhz}] \
-through [get_nets *altera_jesd204_tx_csr_inst*] \
-to [get_clocks {i_system_bd|avl_ad9144_xcvr|alt_core_pll|outclk0}]
set_false_path -from [get_clocks {sys_clk_100mhz}] \
-through [get_nets *altera_jesd204_tx_ctl_inst*] \
-to [get_clocks {i_system_bd|avl_ad9144_xcvr|alt_core_pll|outclk0}]
set_false_path -from [get_clocks {sys_clk_100mhz}] \
-through [get_nets *altera_jesd204_rx_csr_inst*] \
set_false_path -from [get_clocks {sys_clk_100mhz}] -through [get_nets *altera_jesd204_rx_csr_inst*] \
-to [get_clocks {i_system_bd|avl_ad9680_xcvr|alt_core_pll|outclk0}]
set_false_path -from [get_clocks {i_system_bd|avl_ad9144_xcvr|alt_core_pll|outclk0}] \
-through [get_nets *altera_jesd204_tx_csr_inst*] \
-to [get_clocks {sys_clk_100mhz}]
set_false_path -from [get_clocks {i_system_bd|avl_ad9144_xcvr|alt_core_pll|outclk0}] \
-through [get_nets *altera_jesd204_tx_ctl_inst*] \
-to [get_clocks {sys_clk_100mhz}]
set_false_path -from [get_clocks {sys_clk_100mhz}] -through [get_nets *altera_jesd204_tx_csr_inst*] \
-to [get_clocks {i_system_bd|avl_ad9144_xcvr|alt_core_pll|outclk0}]
set_false_path -from [get_clocks {sys_clk_100mhz}] -through [get_nets *altera_jesd204_tx_ctl_inst*] \
-to [get_clocks {i_system_bd|avl_ad9144_xcvr|alt_core_pll|outclk0}]
set_false_path -from [get_clocks {i_system_bd|avl_ad9680_xcvr|alt_core_pll|outclk0}] \
-through [get_nets *altera_jesd204_rx_csr_inst*] \
-to [get_clocks {sys_clk_100mhz}]
-through [get_nets *altera_jesd204_rx_csr_inst*] -to [get_clocks {sys_clk_100mhz}]
set_false_path -from [get_clocks {i_system_bd|avl_ad9144_xcvr|alt_core_pll|outclk0}] \
-through [get_nets *altera_jesd204_tx_csr_inst*] -to [get_clocks {sys_clk_100mhz}]
set_false_path -from [get_clocks {i_system_bd|avl_ad9144_xcvr|alt_core_pll|outclk0}] \
-through [get_nets *altera_jesd204_tx_ctl_inst*] -to [get_clocks {sys_clk_100mhz}]
set_false_path -from [get_clocks {i_system_bd|avl_ad9680_xcvr|alt_phy_0|rx_pma_clk}] \
-through [get_nets *altera_jesd204_rx_csr_inst*] \
-to [get_clocks {i_system_bd|avl_ad9680_xcvr|alt_core_pll|outclk0}]
set_false_path -from [get_clocks {i_system_bd|avl_ad9680_xcvr|alt_phy_1|rx_pma_clk}] \
-through [get_nets *altera_jesd204_rx_csr_inst*] \
-to [get_clocks {i_system_bd|avl_ad9680_xcvr|alt_core_pll|outclk0}]
set_false_path -from [get_clocks {i_system_bd|avl_ad9680_xcvr|alt_phy_2|rx_pma_clk}] \
-through [get_nets *altera_jesd204_rx_csr_inst*] \
-to [get_clocks {i_system_bd|avl_ad9680_xcvr|alt_core_pll|outclk0}]
set_false_path -from [get_clocks {i_system_bd|avl_ad9680_xcvr|alt_phy_3|rx_pma_clk}] \
-through [get_nets *altera_jesd204_rx_csr_inst*] \
-to [get_clocks {i_system_bd|avl_ad9680_xcvr|alt_core_pll|outclk0}]