common,adv7511: Added mitx045 platform.
Adrian Costina
parent
877b81a373
commit
c52327d0c6
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source $ad_hdl_dir/projects/common/mitx045/mitx045_system_bd.tcl
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set_property -dict [list CONFIG.PCW_GPIO_EMIO_GPIO_IO {32}] $sys_ps7
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set_property -dict [list CONFIG.NUM_MI {7}] $axi_cpu_interconnect
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set_property -dict [list CONFIG.NUM_PORTS {5}] $sys_concat_intc
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set_property LEFT 31 [get_bd_ports GPIO_I]
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set_property LEFT 31 [get_bd_ports GPIO_O]
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set_property LEFT 31 [get_bd_ports GPIO_T]
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source ../../scripts/adi_env.tcl
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source $ad_hdl_dir/projects/scripts/adi_project.tcl
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adi_project_create adv7511_mitx045
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adi_project_files adv7511_mitx045 [list \
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"system_top.v" \
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"$ad_hdl_dir/library/common/ad_iobuf.v" \
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"$ad_hdl_dir/projects/common/mitx045/mitx045.xml" \
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"$ad_hdl_dir/projects/common/mitx045/mitx045_system_constr.xdc" ]
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adi_project_run adv7511_mitx045
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// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014(c) Analog Devices, Inc.
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//
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without modification,
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// are permitted provided that the following conditions are met:
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// - Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// - Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in
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// the documentation and/or other materials provided with the
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// distribution.
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// - Neither the name of Analog Devices, Inc. nor the names of its
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// contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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// - The use of this software may or may not infringe the patent rights
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// of one or more patent holders. This license does not release you
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// from the requirement that you obtain separate licenses from these
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// patent holders to use this software.
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// - Use of the software either in source or binary form, must be run
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// on or directly connected to an Analog Devices Inc. component.
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//
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// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
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// PARTICULAR PURPOSE ARE DISCLAIMED.
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//
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// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
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// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module system_top (
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DDR_addr,
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DDR_ba,
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DDR_cas_n,
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DDR_ck_n,
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DDR_ck_p,
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DDR_cke,
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DDR_cs_n,
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DDR_dm,
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DDR_dq,
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DDR_dqs_n,
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DDR_dqs_p,
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DDR_odt,
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DDR_ras_n,
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DDR_reset_n,
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DDR_we_n,
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FIXED_IO_ddr_vrn,
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FIXED_IO_ddr_vrp,
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FIXED_IO_mio,
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FIXED_IO_ps_clk,
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FIXED_IO_ps_porb,
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FIXED_IO_ps_srstb,
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gpio_bd,
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hdmi_out_clk,
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hdmi_vsync,
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hdmi_hsync,
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hdmi_data_e,
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hdmi_data,
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spdif,
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iic_scl,
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iic_sda);
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inout [14:0] DDR_addr;
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inout [ 2:0] DDR_ba;
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inout DDR_cas_n;
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inout DDR_ck_n;
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inout DDR_ck_p;
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inout DDR_cke;
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inout DDR_cs_n;
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inout [ 3:0] DDR_dm;
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inout [31:0] DDR_dq;
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inout [ 3:0] DDR_dqs_n;
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inout [ 3:0] DDR_dqs_p;
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inout DDR_odt;
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inout DDR_ras_n;
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inout DDR_reset_n;
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inout DDR_we_n;
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inout FIXED_IO_ddr_vrn;
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inout FIXED_IO_ddr_vrp;
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inout [53:0] FIXED_IO_mio;
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inout FIXED_IO_ps_clk;
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inout FIXED_IO_ps_porb;
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inout FIXED_IO_ps_srstb;
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inout [11:0] gpio_bd;
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output hdmi_out_clk;
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output hdmi_vsync;
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output hdmi_hsync;
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output hdmi_data_e;
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output [15:0] hdmi_data;
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output spdif;
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inout iic_scl;
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inout iic_sda;
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// internal signals
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wire [31:0] gpio_i;
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wire [31:0] gpio_o;
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wire [31:0] gpio_t;
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wire [19:0] gpio_wire;
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// instantiations
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ad_iobuf #(.DATA_WIDTH(32)) i_iobuf (
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.dt (gpio_t[31:0]),
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.di (gpio_o[31:0]),
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.do (gpio_i[31:0]),
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.dio({ gpio_wire,
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gpio_bd}));
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system_wrapper i_system_wrapper (
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.DDR_addr (DDR_addr),
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.DDR_ba (DDR_ba),
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.DDR_cas_n (DDR_cas_n),
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.DDR_ck_n (DDR_ck_n),
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.DDR_ck_p (DDR_ck_p),
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.DDR_cke (DDR_cke),
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.DDR_cs_n (DDR_cs_n),
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.DDR_dm (DDR_dm),
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.DDR_dq (DDR_dq),
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.DDR_dqs_n (DDR_dqs_n),
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.DDR_dqs_p (DDR_dqs_p),
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.DDR_odt (DDR_odt),
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.DDR_ras_n (DDR_ras_n),
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.DDR_reset_n (DDR_reset_n),
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.DDR_we_n (DDR_we_n),
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.FIXED_IO_ddr_vrn (FIXED_IO_ddr_vrn),
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.FIXED_IO_ddr_vrp (FIXED_IO_ddr_vrp),
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.FIXED_IO_mio (FIXED_IO_mio),
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.FIXED_IO_ps_clk (FIXED_IO_ps_clk),
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.FIXED_IO_ps_porb (FIXED_IO_ps_porb),
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.FIXED_IO_ps_srstb (FIXED_IO_ps_srstb),
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.GPIO_I (gpio_i),
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.GPIO_O (gpio_o),
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.GPIO_T (gpio_t),
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.hdmi_data (hdmi_data),
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.hdmi_data_e (hdmi_data_e),
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.hdmi_hsync (hdmi_hsync),
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.hdmi_out_clk (hdmi_out_clk),
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.hdmi_vsync (hdmi_vsync),
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.iic_main_scl_io (iic_scl),
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.iic_main_sda_io (iic_sda),
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.spdif (spdif));
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endmodule
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// ***************************************************************************
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// ***************************************************************************
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@ -0,0 +1,228 @@
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<?xml version="1.0" encoding="UTF-8" ?>
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<!DOCTYPE project PUBLIC "project" "project.dtd" >
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<project version="1.0" >
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<set param="PCW::UART1::PERIPHERAL::ENABLE" value="1" />
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<set param="PCW::CAN0::PERIPHERAL::ENABLE" value="0" />
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<set param="PCW::SD0::GRP_CD::IO" value="MIO 14" />
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<set param="PCW::ENET1::RESET::IO" value="-1" />
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<set param="PCW::USB0::RESET::IO" value="MIO 7" />
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<set param="PCW::USB0::PERIPHERAL::ENABLE" value="1" />
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<set param="PCW::USB0::RESET::ENABLE" value="1" />
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<set param="PCW::QSPI::GRP_FBCLK::ENABLE" value="1" />
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<set param="PCW::QSPI::GRP_IO1::ENABLE" value="1" />
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<set param="PCW::QSPI::GRP_SS1::ENABLE" value="1" />
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<set param="PCW::QSPI::PERIPHERAL::ENABLE" value="1" />
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<set param="PCW::WDT::PERIPHERAL::ENABLE" value="1" />
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<set param="PCW::PJTAG::PERIPHERAL::ENABLE" value="1" />
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<set param="PCW::MIO::MIO[1]::SLEW" value="slow" />
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<set param="PCW::MIO::MIO[0]::IOTYPE" value="LVCMOS 1.8V" />
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<set param="PCW::MIO::MIO[1]::IOTYPE" value="LVCMOS 1.8V" />
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<set param="PCW::MIO::MIO[7]::PULLUP" value="disabled" />
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<set param="PCW::MIO::MIO[7]::IOTYPE" value="LVCMOS 1.8V" />
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<set param="PCW::MIO::MIO[6]::IOTYPE" value="LVCMOS 1.8V" />
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<set param="PCW::MIO::MIO[3]::PULLUP" value="disabled" />
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<set param="PCW::MIO::MIO[5]::PULLUP" value="disabled" />
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<set param="PCW::MIO::MIO[5]::SLEW" value="slow" />
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<set param="PCW::MIO::MIO[4]::SLEW" value="slow" />
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<set param="PCW::MIO::MIO[3]::IOTYPE" value="LVCMOS 1.8V" />
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<set param="PCW::MIO::MIO[8]::PULLUP" value="disabled" />
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<set param="PCW::MIO::MIO[8]::IOTYPE" value="LVCMOS 1.8V" />
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<set param="PCW::MIO::MIO[7]::DIRECTION" value="in" />
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<set param="PCW::MIO::MIO[6]::PULLUP" value="disabled" />
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<set param="PCW::MIO::MIO[6]::SLEW" value="slow" />
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<set param="PCW::MIO::MIO[5]::IOTYPE" value="LVCMOS 1.8V" />
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<set param="PCW::MIO::MIO[4]::IOTYPE" value="LVCMOS 1.8V" />
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<set param="PCW::MIO::MIO[2]::PULLUP" value="disabled" />
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<set param="PCW::MIO::MIO[4]::PULLUP" value="disabled" />
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<set param="PCW::MIO::MIO[3]::SLEW" value="slow" />
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<set param="PCW::MIO::MIO[2]::IOTYPE" value="LVCMOS 1.8V" />
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<set param="PCW::MIO::MIO[2]::SLEW" value="slow" />
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<set param="PCW::MIO::MIO[20]::PULLUP" value="disabled" />
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<set param="PCW::MIO::MIO[20]::IOTYPE" value="LVCMOS 1.8V" />
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<set param="PCW::MIO::MIO[19]::SLEW" value="slow" />
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<set param="PCW::MIO::MIO[18]::PULLUP" value="disabled" />
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<set param="PCW::MIO::MIO[18]::IOTYPE" value="LVCMOS 1.8V" />
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<set param="PCW::MIO::MIO[17]::SLEW" value="slow" />
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<set param="PCW::MIO::MIO[16]::PULLUP" value="disabled" />
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<set param="PCW::MIO::MIO[16]::IOTYPE" value="LVCMOS 1.8V" />
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<set param="PCW::MIO::MIO[15]::DIRECTION" value="in" />
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<set param="PCW::MIO::MIO[14]::IOTYPE" value="LVCMOS 1.8V" />
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<set param="PCW::MIO::MIO[20]::SLEW" value="slow" />
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<set param="PCW::MIO::MIO[19]::PULLUP" value="disabled" />
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<set param="PCW::MIO::MIO[19]::IOTYPE" value="LVCMOS 1.8V" />
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<set param="PCW::MIO::MIO[18]::SLEW" value="slow" />
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<set param="PCW::MIO::MIO[17]::PULLUP" value="disabled" />
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<set param="PCW::MIO::MIO[17]::IOTYPE" value="LVCMOS 1.8V" />
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<set param="PCW::MIO::MIO[16]::SLEW" value="slow" />
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<set param="PCW::MIO::MIO[15]::PULLUP" value="enabled" />
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<set param="PCW::MIO::MIO[15]::IOTYPE" value="LVCMOS 1.8V" />
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<set param="PCW::MIO::MIO[13]::PULLUP" value="disabled" />
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<set param="PCW::MIO::MIO[27]::SLEW" value="slow" />
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<set param="PCW::MIO::MIO[26]::PULLUP" value="disabled" />
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<set param="PCW::MIO::MIO[26]::IOTYPE" value="LVCMOS 1.8V" />
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<set param="PCW::MIO::MIO[25]::SLEW" value="slow" />
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<set param="PCW::MIO::MIO[24]::PULLUP" value="disabled" />
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<set param="PCW::MIO::MIO[24]::IOTYPE" value="LVCMOS 1.8V" />
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<set param="PCW::MIO::MIO[23]::SLEW" value="slow" />
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<set param="PCW::MIO::MIO[22]::PULLUP" value="disabled" />
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<set param="PCW::MIO::MIO[22]::IOTYPE" value="LVCMOS 1.8V" />
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<set param="PCW::MIO::MIO[21]::SLEW" value="slow" />
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<set param="PCW::MIO::MIO[28]::IOTYPE" value="LVCMOS 1.8V" />
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<set param="PCW::MIO::MIO[28]::SLEW" value="slow" />
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<set param="PCW::MIO::MIO[27]::PULLUP" value="disabled" />
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<set param="PCW::MIO::MIO[27]::IOTYPE" value="LVCMOS 1.8V" />
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<set param="PCW::MIO::MIO[26]::SLEW" value="slow" />
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<set param="PCW::MIO::MIO[25]::PULLUP" value="disabled" />
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<set param="PCW::MIO::MIO[25]::IOTYPE" value="LVCMOS 1.8V" />
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<set param="PCW::MIO::MIO[24]::SLEW" value="slow" />
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<set param="PCW::MIO::MIO[23]::PULLUP" value="disabled" />
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<set param="PCW::MIO::MIO[23]::IOTYPE" value="LVCMOS 1.8V" />
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<set param="PCW::MIO::MIO[22]::SLEW" value="slow" />
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<set param="PCW::MIO::MIO[21]::PULLUP" value="disabled" />
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<set param="PCW::MIO::MIO[21]::IOTYPE" value="LVCMOS 1.8V" />
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<set param="PCW::MIO::MIO[35]::SLEW" value="slow" />
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<set param="PCW::MIO::MIO[34]::PULLUP" value="disabled" />
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<set param="PCW::MIO::MIO[34]::IOTYPE" value="LVCMOS 1.8V" />
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<set param="PCW::MIO::MIO[33]::SLEW" value="slow" />
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<set param="PCW::MIO::MIO[32]::PULLUP" value="disabled" />
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<set param="PCW::MIO::MIO[32]::IOTYPE" value="LVCMOS 1.8V" />
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<set param="PCW::MIO::MIO[31]::SLEW" value="slow" />
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<set param="PCW::MIO::MIO[30]::PULLUP" value="disabled" />
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<set param="PCW::MIO::MIO[30]::IOTYPE" value="LVCMOS 1.8V" />
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<set param="PCW::MIO::MIO[29]::SLEW" value="slow" />
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<set param="PCW::MIO::MIO[28]::PULLUP" value="disabled" />
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<set param="PCW::MIO::MIO[35]::PULLUP" value="disabled" />
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<set param="PCW::MIO::MIO[35]::IOTYPE" value="LVCMOS 1.8V" />
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<set param="PCW::MIO::MIO[34]::SLEW" value="slow" />
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<set param="PCW::MIO::MIO[33]::PULLUP" value="disabled" />
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<set param="PCW::MIO::MIO[33]::IOTYPE" value="LVCMOS 1.8V" />
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<set param="PCW::MIO::MIO[32]::SLEW" value="slow" />
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<set param="PCW::MIO::MIO[31]::PULLUP" value="disabled" />
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<set param="PCW::MIO::MIO[31]::IOTYPE" value="LVCMOS 1.8V" />
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<set param="PCW::MIO::MIO[30]::SLEW" value="slow" />
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<set param="PCW::MIO::MIO[29]::PULLUP" value="disabled" />
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<set param="PCW::MIO::MIO[29]::IOTYPE" value="LVCMOS 1.8V" />
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<set param="PCW::MIO::MIO[11]::PULLUP" value="disabled" />
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<set param="PCW::MIO::MIO[11]::IOTYPE" value="LVCMOS 1.8V" />
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<set param="PCW::MIO::MIO[9]::PULLUP" value="disabled" />
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<set param="PCW::MIO::MIO[9]::IOTYPE" value="LVCMOS 1.8V" />
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<set param="PCW::MIO::MIO[13]::IOTYPE" value="LVCMOS 1.8V" />
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<set param="PCW::MIO::MIO[12]::PULLUP" value="disabled" />
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<set param="PCW::MIO::MIO[12]::IOTYPE" value="LVCMOS 1.8V" />
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<set param="PCW::MIO::MIO[10]::PULLUP" value="disabled" />
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<set param="PCW::MIO::MIO[10]::IOTYPE" value="LVCMOS 1.8V" />
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<set param="PCW::MIO::MIO[39]::SLEW" value="slow" />
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<set param="PCW::MIO::MIO[38]::PULLUP" value="disabled" />
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<set param="PCW::MIO::MIO[38]::IOTYPE" value="LVCMOS 1.8V" />
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<set param="PCW::MIO::MIO[37]::PULLUP" value="disabled" />
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<set param="PCW::MIO::MIO[37]::SLEW" value="slow" />
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<set param="PCW::MIO::MIO[36]::IOTYPE" value="LVCMOS 1.8V" />
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<set param="PCW::MIO::MIO[39]::PULLUP" value="disabled" />
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<set param="PCW::MIO::MIO[39]::IOTYPE" value="LVCMOS 1.8V" />
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<set param="PCW::MIO::MIO[38]::SLEW" value="slow" />
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<set param="PCW::MIO::MIO[36]::PULLUP" value="disabled" />
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<set param="PCW::MIO::MIO[36]::SLEW" value="slow" />
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<set param="PCW::MIO::MIO[37]::IOTYPE" value="LVCMOS 1.8V" />
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<set param="PCW::MIO::MIO[40]::SLEW" value="slow" />
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<set param="PCW::MIO::MIO[41]::PULLUP" value="disabled" />
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<set param="PCW::MIO::MIO[40]::PULLUP" value="disabled" />
|
||||
<set param="PCW::MIO::MIO[43]::PULLUP" value="disabled" />
|
||||
<set param="PCW::MIO::MIO[43]::IOTYPE" value="LVCMOS 1.8V" />
|
||||
<set param="PCW::MIO::MIO[42]::SLEW" value="slow" />
|
||||
<set param="PCW::MIO::MIO[41]::SLEW" value="slow" />
|
||||
<set param="PCW::MIO::MIO[41]::IOTYPE" value="LVCMOS 1.8V" />
|
||||
<set param="PCW::MIO::MIO[43]::SLEW" value="slow" />
|
||||
<set param="PCW::MIO::MIO[42]::PULLUP" value="disabled" />
|
||||
<set param="PCW::MIO::MIO[42]::IOTYPE" value="LVCMOS 1.8V" />
|
||||
<set param="PCW::MIO::MIO[40]::IOTYPE" value="LVCMOS 1.8V" />
|
||||
<set param="PCW::MIO::MIO[44]::IOTYPE" value="LVCMOS 1.8V" />
|
||||
<set param="PCW::MIO::MIO[44]::SLEW" value="slow" />
|
||||
<set param="PCW::MIO::MIO[47]::PULLUP" value="enabled" />
|
||||
<set param="PCW::MIO::MIO[47]::IOTYPE" value="LVCMOS 1.8V" />
|
||||
<set param="PCW::MIO::MIO[46]::DIRECTION" value="in" />
|
||||
<set param="PCW::MIO::MIO[48]::PULLUP" value="disabled" />
|
||||
<set param="PCW::MIO::MIO[48]::IOTYPE" value="LVCMOS 1.8V" />
|
||||
<set param="PCW::MIO::MIO[47]::DIRECTION" value="in" />
|
||||
<set param="PCW::MIO::MIO[46]::PULLUP" value="enabled" />
|
||||
<set param="PCW::MIO::MIO[46]::IOTYPE" value="LVCMOS 1.8V" />
|
||||
<set param="PCW::MIO::MIO[45]::IOTYPE" value="LVCMOS 1.8V" />
|
||||
<set param="PCW::MIO::MIO[45]::PULLUP" value="disabled" />
|
||||
<set param="PCW::MIO::MIO[45]::SLEW" value="slow" />
|
||||
<set param="PCW::MIO::MIO[44]::PULLUP" value="disabled" />
|
||||
<set param="PCW::MIO::MIO[50]::IOTYPE" value="LVCMOS 1.8V" />
|
||||
<set param="PCW::MIO::MIO[49]::IOTYPE" value="LVCMOS 1.8V" />
|
||||
<set param="PCW::MIO::MIO[49]::PULLUP" value="disabled" />
|
||||
<set param="PCW::MIO::MIO[51]::IOTYPE" value="LVCMOS 1.8V" />
|
||||
<set param="PCW::MIO::MIO[53]::PULLUP" value="disabled" />
|
||||
<set param="PCW::MIO::MIO[53]::IOTYPE" value="LVCMOS 1.8V" />
|
||||
<set param="PCW::MIO::MIO[52]::PULLUP" value="disabled" />
|
||||
<set param="PCW::MIO::MIO[52]::IOTYPE" value="LVCMOS 1.8V" />
|
||||
<set param="PCW::UIPARAM::DDR::CWL" value="6" />
|
||||
<set param="PCW::UIPARAM::DDR::CL" value="7" />
|
||||
<set param="PCW::UIPARAM::DDR::COL_ADDR_COUNT" value="10" />
|
||||
<set param="PCW::UIPARAM::DDR::FREQ_MHZ" value="533.333313" />
|
||||
<set param="PCW::UIPARAM::DDR::SPEED_BIN" value="DDR3_1066F" />
|
||||
<set param="PCW::UIPARAM::DDR::DEVICE_CAPACITY" value="4096 MBits" />
|
||||
<set param="PCW::UIPARAM::DDR::DRAM_WIDTH" value="16 Bits" />
|
||||
<set param="PCW::UIPARAM::DDR::BL" value="8" />
|
||||
<set param="PCW::UIPARAM::DDR::BUS_WIDTH" value="32 Bit" />
|
||||
<set param="PCW::UIPARAM::DDR::MEMORY_TYPE" value="DDR 3" />
|
||||
<set param="PCW::UIPARAM::DDR::DQS_TO_CLK_DELAY_3" value="-0.055" />
|
||||
<set param="PCW::UIPARAM::DDR::DQS_TO_CLK_DELAY_1" value="0.074" />
|
||||
<set param="PCW::UIPARAM::DDR::T_RAS_MIN" value="36.0" />
|
||||
<set param="PCW::UIPARAM::DDR::T_RP" value="7" />
|
||||
<set param="PCW::UIPARAM::DDR::PARTNO" value="Custom" />
|
||||
<set param="PCW::UIPARAM::DDR::DQS_TO_CLK_DELAY_2" value="-0.059" />
|
||||
<set param="PCW::UIPARAM::DDR::DQS_TO_CLK_DELAY_0" value="0.078" />
|
||||
<set param="PCW::UIPARAM::DDR::T_FAW" value="45.0" />
|
||||
<set param="PCW::UIPARAM::DDR::T_RC" value="49.5" />
|
||||
<set param="PCW::UIPARAM::DDR::T_RCD" value="7" />
|
||||
<set param="PCW::UIPARAM::DDR::CLOCK_0_LENGTH_MM" value="80.36" />
|
||||
<set param="PCW::UIPARAM::DDR::DQ_3_LENGTH_MM" value="67.56" />
|
||||
<set param="PCW::UIPARAM::DDR::DQ_2_LENGTH_MM" value="67.56" />
|
||||
<set param="PCW::UIPARAM::DDR::DQ_1_LENGTH_MM" value="67.56" />
|
||||
<set param="PCW::UIPARAM::DDR::DQS_3_LENGTH_MM" value="67.56" />
|
||||
<set param="PCW::UIPARAM::DDR::DQS_1_LENGTH_MM" value="67.56" />
|
||||
<set param="PCW::UIPARAM::DDR::BOARD_DELAY3" value="0.416" />
|
||||
<set param="PCW::UIPARAM::DDR::BOARD_DELAY1" value="0.484" />
|
||||
<set param="PCW::UIPARAM::DDR::TRAIN_DATA_EYE" value="1" />
|
||||
<set param="PCW::UIPARAM::DDR::TRAIN_WRITE_LEVEL" value="1" />
|
||||
<set param="PCW::UIPARAM::DDR::DQ_0_LENGTH_MM" value="67.56" />
|
||||
<set param="PCW::UIPARAM::DDR::DQS_2_LENGTH_MM" value="67.56" />
|
||||
<set param="PCW::UIPARAM::DDR::DQS_0_LENGTH_MM" value="67.56" />
|
||||
<set param="PCW::UIPARAM::DDR::BOARD_DELAY2" value="0.417" />
|
||||
<set param="PCW::UIPARAM::DDR::BOARD_DELAY0" value="0.482" />
|
||||
<set param="PCW::UIPARAM::DDR::USE_INTERNAL_VREF" value="1" />
|
||||
<set param="PCW::UIPARAM::DDR::TRAIN_READ_GATE" value="1" />
|
||||
<set param="PCW::UIPARAM::DDR::CLOCK_2_LENGTH_MM" value="59.26" />
|
||||
<set param="PCW::UIPARAM::DDR::CLOCK_3_LENGTH_MM" value="59.26" />
|
||||
<set param="PCW::UIPARAM::DDR::CLOCK_1_LENGTH_MM" value="80.36" />
|
||||
<set param="PCW::GPIO::GPIO::IO" value="MIO" />
|
||||
<set param="PCW::GPIO::PERIPHERAL::ENABLE" value="1" />
|
||||
<set param="PCW::CAN::PERIPHERAL::FREQMHZ" value="100" />
|
||||
<set param="PCW::UART::PERIPHERAL::FREQMHZ" value="50" />
|
||||
<set param="PCW::ENET0::PERIPHERAL::FREQMHZ" value="1000 Mbps" />
|
||||
<set param="PCW::APU::PERIPHERAL::FREQMHZ" value="667.000000" />
|
||||
<set param="PCW::PRESET::GLOBAL::DEFAULT" value="powerup" />
|
||||
<set param="PCW::SDIO::PERIPHERAL::FREQMHZ" value="50" />
|
||||
<set param="PCW::PRESET::GLOBAL::CONFIG" value="Default" />
|
||||
<set param="PCW::PRESET::BANK1::VOLTAGE" value="LVCMOS 1.8V" />
|
||||
<set param="PCW::PRESET::FPGA::PARTNUMBER" value="xc7z045ffg900-2" />
|
||||
<set param="PCW::PRESET::BANK0::VOLTAGE" value="LVCMOS 1.8V" />
|
||||
<set param="PCW::PRESET::FPGA::SPEED" value="-2" />
|
||||
<set param="PCW::TTC0::PERIPHERAL::ENABLE" value="1" />
|
||||
<set param="PCW::I2C0::RESET::IO" value="MIO 46" />
|
||||
<set param="PCW::I2C0::RESET::ENABLE" value="1" />
|
||||
<set param="PCW::I2C0::I2C0::IO" value="MIO 50 .. 51" />
|
||||
<set param="PCW::I2C0::PERIPHERAL::ENABLE" value="1" />
|
||||
<set param="PCW::SD0::GRP_WP::ENABLE" value="1" />
|
||||
<set param="PCW::SD0::GRP_CD::ENABLE" value="1" />
|
||||
<set param="PCW::SD0::PERIPHERAL::ENABLE" value="1" />
|
||||
<set param="PCW::ENET0::GRP_MDIO::IO" value="MIO 52 .. 53" />
|
||||
<set param="PCW::ENET0::RESET::IO" value="MIO 47" />
|
||||
<set param="PCW::ENET0::RESET::ENABLE" value="1" />
|
||||
<set param="PCW::ENET0::GRP_MDIO::ENABLE" value="1" />
|
||||
<set param="PCW::ENET0::ENET0::IO" value="MIO 16 .. 27" />
|
||||
<set param="PCW::ENET0::PERIPHERAL::ENABLE" value="1" />
|
||||
<set param="PCW::USB1::RESET::IO" value="-1" />
|
||||
</project>
|
||||
|
|
@ -0,0 +1,209 @@
|
|||
# create board design
|
||||
# interface ports
|
||||
|
||||
set DDR [create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 DDR]
|
||||
set FIXED_IO [create_bd_intf_port -mode Master -vlnv xilinx.com:display_processing_system7:fixedio_rtl:1.0 FIXED_IO]
|
||||
set IIC_MAIN [create_bd_intf_port -mode Master -vlnv xilinx.com:interface:iic_rtl:1.0 IIC_MAIN]
|
||||
|
||||
set GPIO_I [create_bd_port -dir I -from 31 -to 0 GPIO_I]
|
||||
set GPIO_O [create_bd_port -dir O -from 31 -to 0 GPIO_O]
|
||||
set GPIO_T [create_bd_port -dir O -from 31 -to 0 GPIO_T]
|
||||
|
||||
# hdmi interface
|
||||
|
||||
set hdmi_out_clk [create_bd_port -dir O hdmi_out_clk]
|
||||
set hdmi_hsync [create_bd_port -dir O hdmi_hsync]
|
||||
set hdmi_vsync [create_bd_port -dir O hdmi_vsync]
|
||||
set hdmi_data_e [create_bd_port -dir O hdmi_data_e]
|
||||
set hdmi_data [create_bd_port -dir O -from 15 -to 0 hdmi_data]
|
||||
|
||||
# spdif audio
|
||||
|
||||
set spdif [create_bd_port -dir O spdif]
|
||||
|
||||
# instance: sys_ps7
|
||||
|
||||
set sys_ps7 [create_bd_cell -type ip -vlnv xilinx.com:ip:processing_system7:5.3 sys_ps7]
|
||||
set_property -dict [list CONFIG.PCW_IMPORT_BOARD_PRESET {../../common/mitx045/mitx045.xml} ] [get_bd_cells sys_ps7]
|
||||
set_property -dict [list CONFIG.PCW_GPIO_MIO_GPIO_ENABLE {1} ] $sys_ps7
|
||||
set_property -dict [list CONFIG.PCW_EN_CLK1_PORT {1}] $sys_ps7
|
||||
set_property -dict [list CONFIG.PCW_EN_RST1_PORT {1}] $sys_ps7
|
||||
set_property -dict [list CONFIG.PCW_FPGA0_PERIPHERAL_FREQMHZ {100.0}] $sys_ps7
|
||||
set_property -dict [list CONFIG.PCW_FPGA1_PERIPHERAL_FREQMHZ {200.0}] $sys_ps7
|
||||
set_property -dict [list CONFIG.PCW_USE_FABRIC_INTERRUPT {1}] $sys_ps7
|
||||
set_property -dict [list CONFIG.PCW_USE_S_AXI_HP0 {1}] $sys_ps7
|
||||
set_property -dict [list CONFIG.PCW_IRQ_F2P_INTR {1}] $sys_ps7
|
||||
set_property -dict [list CONFIG.PCW_GPIO_EMIO_GPIO_ENABLE {1}] $sys_ps7
|
||||
set_property -dict [list CONFIG.PCW_GPIO_EMIO_GPIO_IO {32}] $sys_ps7
|
||||
set_property -dict [list CONFIG.PCW_USE_DMA0 {1}] $sys_ps7
|
||||
|
||||
set axi_iic_main [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_iic:2.0 axi_iic_main]
|
||||
set_property -dict [list CONFIG.USE_BOARD_FLOW {true} CONFIG.IIC_BOARD_INTERFACE {IIC_MAIN}] $axi_iic_main
|
||||
|
||||
set sys_concat_intc [create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:1.0 sys_concat_intc]
|
||||
set_property -dict [list CONFIG.NUM_PORTS {5}] $sys_concat_intc
|
||||
|
||||
set axi_cpu_interconnect [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_cpu_interconnect]
|
||||
set_property -dict [list CONFIG.NUM_MI {7}] $axi_cpu_interconnect
|
||||
|
||||
set sys_rstgen [create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 sys_rstgen]
|
||||
set_property -dict [list CONFIG.C_EXT_RST_WIDTH {1}] $sys_rstgen
|
||||
|
||||
# hdmi peripherals
|
||||
|
||||
set axi_hdmi_clkgen [create_bd_cell -type ip -vlnv analog.com:user:axi_clkgen:1.0 axi_hdmi_clkgen]
|
||||
set axi_hdmi_core [create_bd_cell -type ip -vlnv analog.com:user:axi_hdmi_tx:1.0 axi_hdmi_core]
|
||||
|
||||
set axi_hdmi_dma [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_vdma:6.1 axi_hdmi_dma]
|
||||
set_property -dict [list CONFIG.c_m_axis_mm2s_tdata_width {64}] $axi_hdmi_dma
|
||||
set_property -dict [list CONFIG.c_use_mm2s_fsync {1}] $axi_hdmi_dma
|
||||
set_property -dict [list CONFIG.c_include_s2mm {0}] $axi_hdmi_dma
|
||||
|
||||
set axi_hdmi_interconnect [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_hdmi_interconnect]
|
||||
set_property -dict [list CONFIG.NUM_MI {1}] $axi_hdmi_interconnect
|
||||
|
||||
# audio peripherals
|
||||
|
||||
set sys_audio_clkgen [create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:5.1 sys_audio_clkgen]
|
||||
set_property -dict [list CONFIG.PRIM_IN_FREQ {200.000}] $sys_audio_clkgen
|
||||
set_property -dict [list CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {12.288}] $sys_audio_clkgen
|
||||
|
||||
set axi_spdif_tx_core [create_bd_cell -type ip -vlnv analog.com:user:axi_spdif_tx:1.0 axi_spdif_tx_core]
|
||||
set_property -dict [list CONFIG.C_DMA_TYPE {1}] $axi_spdif_tx_core
|
||||
set_property -dict [list CONFIG.C_S_AXI_ADDR_WIDTH {16}] $axi_spdif_tx_core
|
||||
set_property -dict [list CONFIG.C_HIGHADDR {0xffffffff}] $axi_spdif_tx_core
|
||||
set_property -dict [list CONFIG.C_BASEADDR {0x00000000}] $axi_spdif_tx_core
|
||||
|
||||
# system reset/clock definitions
|
||||
|
||||
set sys_100m_clk_source [get_bd_pins sys_ps7/FCLK_CLK0]
|
||||
set sys_200m_clk_source [get_bd_pins sys_ps7/FCLK_CLK1]
|
||||
|
||||
connect_bd_net -net sys_100m_clk $sys_100m_clk_source
|
||||
connect_bd_net -net sys_200m_clk $sys_200m_clk_source
|
||||
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins sys_rstgen/slowest_sync_clk]
|
||||
connect_bd_net -net sys_aux_reset [get_bd_pins sys_rstgen/ext_reset_in] [get_bd_pins sys_ps7/FCLK_RESET0_N]
|
||||
|
||||
set sys_100m_resetn_source [get_bd_pins sys_rstgen/peripheral_aresetn]
|
||||
set sys_200m_resetn_source [get_bd_pins sys_rstgen/interconnect_aresetn]
|
||||
connect_bd_net -net sys_100m_resetn $sys_100m_resetn_source
|
||||
connect_bd_net -net sys_200m_resetn $sys_200m_resetn_source
|
||||
|
||||
# interface connections
|
||||
|
||||
connect_bd_intf_net -intf_net sys_ps7_ddr [get_bd_intf_ports DDR] [get_bd_intf_pins sys_ps7/DDR]
|
||||
connect_bd_net -net sys_ps7_GPIO_I [get_bd_ports GPIO_I] [get_bd_pins sys_ps7/GPIO_I]
|
||||
connect_bd_net -net sys_ps7_GPIO_O [get_bd_ports GPIO_O] [get_bd_pins sys_ps7/GPIO_O]
|
||||
connect_bd_net -net sys_ps7_GPIO_T [get_bd_ports GPIO_T] [get_bd_pins sys_ps7/GPIO_T]
|
||||
connect_bd_intf_net -intf_net sys_ps7_fixed_io [get_bd_intf_ports FIXED_IO] [get_bd_intf_pins sys_ps7/FIXED_IO]
|
||||
connect_bd_intf_net -intf_net axi_iic_main_iic [get_bd_intf_ports IIC_MAIN] [get_bd_intf_pins axi_iic_main/iic]
|
||||
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins sys_ps7/M_AXI_GP0_ACLK]
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/ACLK] $sys_100m_clk_source
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/ARESETN] $sys_100m_resetn_source
|
||||
|
||||
connect_bd_intf_net -intf_net axi_cpu_interconnect_s00_axi [get_bd_intf_pins axi_cpu_interconnect/S00_AXI] [get_bd_intf_pins sys_ps7/M_AXI_GP0]
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/S00_ACLK] $sys_100m_clk_source
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/S00_ARESETN] $sys_100m_resetn_source
|
||||
|
||||
connect_bd_intf_net -intf_net axi_cpu_interconnect_m00_axi [get_bd_intf_pins axi_cpu_interconnect/M00_AXI] [get_bd_intf_pins axi_iic_main/s_axi]
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M00_ACLK] $sys_100m_clk_source
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M00_ARESETN] $sys_100m_resetn_source
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_iic_main/s_axi_aclk]
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_iic_main/s_axi_aresetn]
|
||||
connect_bd_net -net sys_concat_intc_din_1 [get_bd_pins sys_concat_intc/In1] [get_bd_pins axi_iic_main/iic2intc_irpt]
|
||||
|
||||
connect_bd_net -net sys_ps7_interrupt [get_bd_pins sys_concat_intc/dout] [get_bd_pins sys_ps7/IRQ_F2P]
|
||||
|
||||
# hdmi
|
||||
|
||||
connect_bd_net -net sys_200m_clk [get_bd_pins axi_hdmi_clkgen/clk]
|
||||
|
||||
connect_bd_intf_net -intf_net axi_cpu_interconnect_m01_axi [get_bd_intf_pins axi_cpu_interconnect/M01_AXI] [get_bd_intf_pins axi_hdmi_clkgen/s_axi]
|
||||
connect_bd_intf_net -intf_net axi_cpu_interconnect_m02_axi [get_bd_intf_pins axi_cpu_interconnect/M02_AXI] [get_bd_intf_pins axi_hdmi_core/s_axi]
|
||||
connect_bd_intf_net -intf_net axi_cpu_interconnect_m03_axi [get_bd_intf_pins axi_cpu_interconnect/M03_AXI] [get_bd_intf_pins axi_hdmi_dma/S_AXI_LITE]
|
||||
|
||||
connect_bd_intf_net -intf_net axi_hdmi_interconnect_s00_axi [get_bd_intf_pins axi_hdmi_interconnect/S00_AXI] [get_bd_intf_pins axi_hdmi_dma/M_AXI_MM2S]
|
||||
connect_bd_intf_net -intf_net axi_hdmi_interconnect_m00_axi [get_bd_intf_pins axi_hdmi_interconnect/M00_AXI] [get_bd_intf_pins sys_ps7/S_AXI_HP0]
|
||||
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M01_ACLK] $sys_100m_clk_source
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M02_ACLK] $sys_100m_clk_source
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M03_ACLK] $sys_100m_clk_source
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_hdmi_interconnect/ACLK] $sys_100m_clk_source
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_hdmi_interconnect/S00_ACLK] $sys_100m_clk_source
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_hdmi_interconnect/M00_ACLK] $sys_100m_clk_source
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_hdmi_clkgen/s_axi_aclk]
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_hdmi_clkgen/drp_clk]
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_hdmi_core/s_axi_aclk]
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_hdmi_core/m_axis_mm2s_clk]
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_hdmi_dma/s_axi_lite_aclk]
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_hdmi_dma/m_axi_mm2s_aclk]
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_hdmi_dma/m_axis_mm2s_aclk]
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins sys_ps7/S_AXI_HP0_ACLK]
|
||||
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M01_ARESETN] $sys_100m_resetn_source
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M02_ARESETN] $sys_100m_resetn_source
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M03_ARESETN] $sys_100m_resetn_source
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_hdmi_interconnect/ARESETN] $sys_100m_resetn_source
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_hdmi_interconnect/S00_ARESETN] $sys_100m_resetn_source
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_hdmi_interconnect/M00_ARESETN] $sys_100m_resetn_source
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_hdmi_clkgen/s_axi_aresetn]
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_hdmi_core/s_axi_aresetn]
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_hdmi_dma/axi_resetn]
|
||||
|
||||
connect_bd_net -net axi_hdmi_tx_core_hdmi_clk [get_bd_pins axi_hdmi_core/hdmi_clk] [get_bd_pins axi_hdmi_clkgen/clk_0]
|
||||
connect_bd_net -net axi_hdmi_tx_core_hdmi_out_clk [get_bd_pins axi_hdmi_core/hdmi_out_clk] [get_bd_ports hdmi_out_clk]
|
||||
connect_bd_net -net axi_hdmi_tx_core_hdmi_hsync [get_bd_pins axi_hdmi_core/hdmi_16_hsync] [get_bd_ports hdmi_hsync]
|
||||
connect_bd_net -net axi_hdmi_tx_core_hdmi_vsync [get_bd_pins axi_hdmi_core/hdmi_16_vsync] [get_bd_ports hdmi_vsync]
|
||||
connect_bd_net -net axi_hdmi_tx_core_hdmi_data_e [get_bd_pins axi_hdmi_core/hdmi_16_data_e] [get_bd_ports hdmi_data_e]
|
||||
connect_bd_net -net axi_hdmi_tx_core_hdmi_data [get_bd_pins axi_hdmi_core/hdmi_16_data] [get_bd_ports hdmi_data]
|
||||
connect_bd_net -net axi_hdmi_tx_core_mm2s_tvalid [get_bd_pins axi_hdmi_core/m_axis_mm2s_tvalid] [get_bd_pins axi_hdmi_dma/m_axis_mm2s_tvalid]
|
||||
connect_bd_net -net axi_hdmi_tx_core_mm2s_tdata [get_bd_pins axi_hdmi_core/m_axis_mm2s_tdata] [get_bd_pins axi_hdmi_dma/m_axis_mm2s_tdata]
|
||||
connect_bd_net -net axi_hdmi_tx_core_mm2s_tkeep [get_bd_pins axi_hdmi_core/m_axis_mm2s_tkeep] [get_bd_pins axi_hdmi_dma/m_axis_mm2s_tkeep]
|
||||
connect_bd_net -net axi_hdmi_tx_core_mm2s_tlast [get_bd_pins axi_hdmi_core/m_axis_mm2s_tlast] [get_bd_pins axi_hdmi_dma/m_axis_mm2s_tlast]
|
||||
connect_bd_net -net axi_hdmi_tx_core_mm2s_tready [get_bd_pins axi_hdmi_core/m_axis_mm2s_tready] [get_bd_pins axi_hdmi_dma/m_axis_mm2s_tready]
|
||||
connect_bd_net -net axi_hdmi_tx_core_mm2s_fsync [get_bd_pins axi_hdmi_core/m_axis_mm2s_fsync] [get_bd_pins axi_hdmi_dma/mm2s_fsync]
|
||||
connect_bd_net -net axi_hdmi_tx_core_mm2s_fsync [get_bd_pins axi_hdmi_core/m_axis_mm2s_fsync_ret]
|
||||
|
||||
connect_bd_net -net sys_concat_intc_din_0 [get_bd_pins sys_concat_intc/In0] [get_bd_pins axi_hdmi_dma/mm2s_introut]
|
||||
|
||||
# spdif audio
|
||||
|
||||
connect_bd_intf_net -intf_net axi_cpu_interconnect_m04_axi [get_bd_intf_pins axi_cpu_interconnect/M04_AXI] [get_bd_intf_pins axi_spdif_tx_core/s_axi]
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M04_ACLK] $sys_100m_clk_source
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_spdif_tx_core/S_AXI_ACLK]
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M04_ARESETN] $sys_100m_resetn_source
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_spdif_tx_core/S_AXI_ARESETN]
|
||||
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_spdif_tx_core/DMA_REQ_ACLK]
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins sys_ps7/DMA0_ACLK]
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_spdif_tx_core/DMA_REQ_RSTN]
|
||||
connect_bd_intf_net -intf_net axi_spdif_dma_req_tx [get_bd_intf_pins sys_ps7/DMA0_REQ] [get_bd_intf_pins axi_spdif_tx_core/DMA_REQ]
|
||||
connect_bd_intf_net -intf_net axi_spdif_dma_ack_tx [get_bd_intf_pins sys_ps7/DMA0_ACK] [get_bd_intf_pins axi_spdif_tx_core/DMA_ACK]
|
||||
|
||||
connect_bd_net -net sys_200m_clk [get_bd_pins sys_audio_clkgen/clk_in1]
|
||||
connect_bd_net -net sys_audio_clkgen_clk [get_bd_pins sys_audio_clkgen/clk_out1] [get_bd_pins axi_spdif_tx_core/spdif_data_clk]
|
||||
connect_bd_net -net spdif_s [get_bd_ports spdif] [get_bd_pins axi_spdif_tx_core/spdif_tx_o]
|
||||
|
||||
# match up interconnects
|
||||
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M05_ACLK] $sys_100m_clk_source
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M05_ARESETN] $sys_100m_resetn_source
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M06_ACLK] $sys_100m_clk_source
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M06_ARESETN] $sys_100m_resetn_source
|
||||
|
||||
# address map
|
||||
|
||||
set sys_zynq 1
|
||||
set sys_mem_size 0x40000000
|
||||
set sys_addr_cntrl_space [get_bd_addr_spaces sys_ps7/Data]
|
||||
|
||||
create_bd_addr_seg -range 0x00010000 -offset 0x41600000 $sys_addr_cntrl_space [get_bd_addr_segs axi_iic_main/s_axi/Reg] SEG_data_iic_main
|
||||
create_bd_addr_seg -range 0x00010000 -offset 0x79000000 $sys_addr_cntrl_space [get_bd_addr_segs axi_hdmi_clkgen/s_axi/axi_lite] SEG_data_hdmi_clkgen
|
||||
create_bd_addr_seg -range 0x00010000 -offset 0x43000000 $sys_addr_cntrl_space [get_bd_addr_segs axi_hdmi_dma/S_AXI_LITE/Reg] SEG_data_hdmi_dma
|
||||
create_bd_addr_seg -range 0x00010000 -offset 0x70e00000 $sys_addr_cntrl_space [get_bd_addr_segs axi_hdmi_core/s_axi/axi_lite] SEG_data_hdmi_core
|
||||
create_bd_addr_seg -range 0x00010000 -offset 0x75c00000 $sys_addr_cntrl_space [get_bd_addr_segs axi_spdif_tx_core/S_AXI/reg0] SEG_data_spdif_core
|
||||
|
||||
create_bd_addr_seg -range $sys_mem_size -offset 0x00000000 [get_bd_addr_spaces axi_hdmi_dma/Data_MM2S] [get_bd_addr_segs sys_ps7/S_AXI_HP0/HP0_DDR_LOWOCM] SEG_sys_ps7_hp0_ddr_lowocm
|
||||
|
||||
|
|
@ -0,0 +1,62 @@
|
|||
|
||||
# constraints
|
||||
# hdmi
|
||||
|
||||
set_property -dict {PACKAGE_PIN E15 IOSTANDARD LVCMOS18} [get_ports hdmi_out_clk]
|
||||
set_property -dict {PACKAGE_PIN D15 IOSTANDARD LVCMOS18} [get_ports hdmi_vsync]
|
||||
set_property -dict {PACKAGE_PIN D14 IOSTANDARD LVCMOS18} [get_ports hdmi_hsync]
|
||||
set_property -dict {PACKAGE_PIN E16 IOSTANDARD LVCMOS18} [get_ports hdmi_data_e]
|
||||
set_property -dict {PACKAGE_PIN G17 IOSTANDARD LVCMOS18} [get_ports hdmi_data[0]]
|
||||
set_property -dict {PACKAGE_PIN G16 IOSTANDARD LVCMOS18} [get_ports hdmi_data[1]]
|
||||
set_property -dict {PACKAGE_PIN H16 IOSTANDARD LVCMOS18} [get_ports hdmi_data[2]]
|
||||
set_property -dict {PACKAGE_PIN J16 IOSTANDARD LVCMOS18} [get_ports hdmi_data[3]]
|
||||
set_property -dict {PACKAGE_PIN G15 IOSTANDARD LVCMOS18} [get_ports hdmi_data[4]]
|
||||
set_property -dict {PACKAGE_PIN F15 IOSTANDARD LVCMOS18} [get_ports hdmi_data[5]]
|
||||
set_property -dict {PACKAGE_PIN J15 IOSTANDARD LVCMOS18} [get_ports hdmi_data[6]]
|
||||
set_property -dict {PACKAGE_PIN K15 IOSTANDARD LVCMOS18} [get_ports hdmi_data[7]]
|
||||
set_property -dict {PACKAGE_PIN F14 IOSTANDARD LVCMOS18} [get_ports hdmi_data[8]]
|
||||
set_property -dict {PACKAGE_PIN G14 IOSTANDARD LVCMOS18} [get_ports hdmi_data[9]]
|
||||
set_property -dict {PACKAGE_PIN F13 IOSTANDARD LVCMOS18} [get_ports hdmi_data[10]]
|
||||
set_property -dict {PACKAGE_PIN G12 IOSTANDARD LVCMOS18} [get_ports hdmi_data[11]]
|
||||
set_property -dict {PACKAGE_PIN E13 IOSTANDARD LVCMOS18} [get_ports hdmi_data[12]]
|
||||
set_property -dict {PACKAGE_PIN D13 IOSTANDARD LVCMOS18} [get_ports hdmi_data[13]]
|
||||
set_property -dict {PACKAGE_PIN F12 IOSTANDARD LVCMOS18} [get_ports hdmi_data[14]]
|
||||
set_property -dict {PACKAGE_PIN E12 IOSTANDARD LVCMOS18} [get_ports hdmi_data[15]]
|
||||
|
||||
# spdif
|
||||
|
||||
set_property -dict {PACKAGE_PIN F17 IOSTANDARD LVCMOS18} [get_ports spdif]
|
||||
|
||||
# iic
|
||||
|
||||
set_property -dict {PACKAGE_PIN B15 IOSTANDARD LVCMOS18 PULLTYPE PULLUP} [get_ports iic_scl]
|
||||
set_property -dict {PACKAGE_PIN A15 IOSTANDARD LVCMOS18 PULLTYPE PULLUP} [get_ports iic_sda]
|
||||
|
||||
# gpio (switches, leds and such)
|
||||
|
||||
set_property -dict {PACKAGE_PIN B14 IOSTANDARD LVCMOS18} [get_ports gpio_bd[0]] ; ## GPIO_DIP_SW4_PB0
|
||||
set_property -dict {PACKAGE_PIN A14 IOSTANDARD LVCMOS18} [get_ports gpio_bd[1]] ; ## GPIO_DIP_SW5_PB1
|
||||
set_property -dict {PACKAGE_PIN A13 IOSTANDARD LVCMOS18} [get_ports gpio_bd[2]] ; ## GPIO_DIP_SW6_PB2
|
||||
set_property -dict {PACKAGE_PIN A12 IOSTANDARD LVCMOS18} [get_ports gpio_bd[3]] ; ## GPIO_DIP_SW7_PB3
|
||||
|
||||
set_property -dict {PACKAGE_PIN C7 IOSTANDARD LVCMOS15} [get_ports gpio_bd[4]] ; ## GPIO_SW_0
|
||||
set_property -dict {PACKAGE_PIN B7 IOSTANDARD LVCMOS15} [get_ports gpio_bd[5]] ; ## GPIO_SW_1
|
||||
set_property -dict {PACKAGE_PIN A7 IOSTANDARD LVCMOS15} [get_ports gpio_bd[6]] ; ## GPIO_SW_2
|
||||
set_property -dict {PACKAGE_PIN B9 IOSTANDARD LVCMOS15} [get_ports gpio_bd[7]] ; ## GPIO_SW_3
|
||||
set_property -dict {PACKAGE_PIN A8 IOSTANDARD LVCMOS15} [get_ports gpio_bd[8]] ; ## GPIO_SW_4
|
||||
set_property -dict {PACKAGE_PIN A9 IOSTANDARD LVCMOS15} [get_ports gpio_bd[9]] ; ## GPIO_SW_5
|
||||
set_property -dict {PACKAGE_PIN B10 IOSTANDARD LVCMOS15} [get_ports gpio_bd[10]] ; ## GPIO_SW_6
|
||||
set_property -dict {PACKAGE_PIN A10 IOSTANDARD LVCMOS15} [get_ports gpio_bd[11]] ; ## GPIO_SW_7
|
||||
|
||||
# clocks
|
||||
|
||||
create_clock -name cpu_clk -period 10.00 [get_pins i_system_wrapper/system_i/sys_ps7/FCLK_CLK0]
|
||||
create_clock -name m200_clk -period 5.00 [get_pins i_system_wrapper/system_i/sys_ps7/FCLK_CLK1]
|
||||
create_clock -name hdmi_clk -period 6.73 [get_pins i_system_wrapper/system_i/axi_hdmi_clkgen/clk_0]
|
||||
create_clock -name spdif_clk -period 50.00 [get_pins i_system_wrapper/system_i/sys_audio_clkgen/clk_out1]
|
||||
|
||||
set_clock_groups -asynchronous -group {cpu_clk}
|
||||
set_clock_groups -asynchronous -group {m200_clk}
|
||||
set_clock_groups -asynchronous -group {hdmi_clk}
|
||||
set_clock_groups -asynchronous -group {spdif_clk}
|
||||
|
||||
|
|
@ -52,6 +52,12 @@ proc adi_project_create {project_name} {
|
|||
set project_board "xilinx.com:zynq:zc706:1.1"
|
||||
}
|
||||
|
||||
if [regexp "_mitx045$" $project_name] {
|
||||
set xl_board "mitx045"
|
||||
set project_part "xc7z045ffg900-2"
|
||||
set project_board "not-applicable"
|
||||
}
|
||||
|
||||
# planahead - 6 and down
|
||||
|
||||
if {$xl_board eq "ml605"} {
|
||||
|
|
|
|||
Loading…
Reference in New Issue