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up_delay_cntrl:ad_serdes_in: Make delay value width parametrizable 

US/US+ devices have IDELAY/ODELAY with 512 taps. This requires wider
control value for delay selection. 9 bits contrary to 5 on 7series.
main
Laszlo Nagy 2019-07-18 07:26:24 +01:00 committed by Laszlo Nagy
parent 37d378c753
commit c5c772127d
2 changed files with 19 additions and 28 deletions
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34
library/common/up_delay_cntrl.v
View File

@ -42,6 +42,7 @@ module up_delay_cntrl #(
parameter DISABLE = 0, parameter DISABLE = 0,
parameter INIT_DELAY = 0, parameter INIT_DELAY = 0,
parameter DATA_WIDTH = 8, parameter DATA_WIDTH = 8,
parameter DRP_WIDTH = 5,
parameter BASE_ADDRESS = 6'h02) ( parameter BASE_ADDRESS = 6'h02) (
// delay interface // delay interface
@ -53,8 +54,8 @@ module up_delay_cntrl #(
// io interface // io interface
output [(DATA_WIDTH-1):0] up_dld, output [(DATA_WIDTH-1):0] up_dld,
output [((DATA_WIDTH*5)-1):0] up_dwdata, output [((DATA_WIDTH*DRP_WIDTH)-1):0] up_dwdata,
input [((DATA_WIDTH*5)-1):0] up_drdata, input [((DATA_WIDTH*DRP_WIDTH)-1):0] up_drdata,
// processor interface // processor interface
@ -92,22 +93,22 @@ module up_delay_cntrl #(
reg up_dlocked_m3 = 'd0; reg up_dlocked_m3 = 'd0;
reg up_dlocked = 'd0; reg up_dlocked = 'd0;
reg [(DATA_WIDTH-1):0] up_dld_int = 'd0; reg [(DATA_WIDTH-1):0] up_dld_int = 'd0;
reg [((DATA_WIDTH*5)-1):0] up_dwdata_int = 'd0; reg [((DATA_WIDTH*DRP_WIDTH)-1):0] up_dwdata_int = 'd0;
// internal signals // internal signals
wire up_wreq_s; wire up_wreq_s;
wire up_rreq_s; wire up_rreq_s;
wire [ 4:0] up_rdata_s; wire [ DRP_WIDTH-1:0] up_rdata_s;
wire [(DATA_WIDTH-1):0] up_drdata4_s; wire [(DATA_WIDTH-1):0] up_drdata4_s;
wire [(DATA_WIDTH-1):0] up_drdata3_s; wire [(DATA_WIDTH-1):0] up_drdata3_s;
wire [(DATA_WIDTH-1):0] up_drdata2_s; wire [(DATA_WIDTH-1):0] up_drdata2_s;
wire [(DATA_WIDTH-1):0] up_drdata1_s; wire [(DATA_WIDTH-1):0] up_drdata1_s;
wire [(DATA_WIDTH-1):0] up_drdata0_s; wire [(DATA_WIDTH-1):0] up_drdata0_s;
wire [(DATA_WIDTH-1):0] up_dld_s; wire [(DATA_WIDTH-1):0] up_dld_s;
wire [((DATA_WIDTH*5)-1):0] up_dwdata_s; wire [((DATA_WIDTH*DRP_WIDTH)-1):0] up_dwdata_s;
wire [(DATA_WIDTH-1):0] up_dinit_s; wire [(DATA_WIDTH-1):0] up_dinit_s;
wire [((DATA_WIDTH*5)-1):0] up_dinitdata_s; wire [((DATA_WIDTH*DRP_WIDTH)-1):0] up_dinitdata_s;
wire delay_rst_s; wire delay_rst_s;
// variables // variables
@ -118,19 +119,8 @@ module up_delay_cntrl #(
assign up_wreq_s = (up_waddr[13:8] == BASE_ADDRESS) ? up_wreq : 1'b0; assign up_wreq_s = (up_waddr[13:8] == BASE_ADDRESS) ? up_wreq : 1'b0;
assign up_rreq_s = (up_raddr[13:8] == BASE_ADDRESS) ? up_rreq : 1'b0; assign up_rreq_s = (up_raddr[13:8] == BASE_ADDRESS) ? up_rreq : 1'b0;
assign up_rdata_s[4] = | up_drdata4_s;
assign up_rdata_s[3] = | up_drdata3_s;
assign up_rdata_s[2] = | up_drdata2_s;
assign up_rdata_s[1] = | up_drdata1_s;
assign up_rdata_s[0] = | up_drdata0_s;
for (n = 0; n < DATA_WIDTH; n = n + 1) begin: g_drd assign up_rdata_s = up_drdata >> (DRP_WIDTH*up_raddr[7:0]);
assign up_drdata4_s[n] = (up_raddr[7:0] == n) ? up_drdata[((n*5)+4)] : 1'd0;
assign up_drdata3_s[n] = (up_raddr[7:0] == n) ? up_drdata[((n*5)+3)] : 1'd0;
assign up_drdata2_s[n] = (up_raddr[7:0] == n) ? up_drdata[((n*5)+2)] : 1'd0;
assign up_drdata1_s[n] = (up_raddr[7:0] == n) ? up_drdata[((n*5)+1)] : 1'd0;
assign up_drdata0_s[n] = (up_raddr[7:0] == n) ? up_drdata[((n*5)+0)] : 1'd0;
end
// processor interface // processor interface
@ -156,7 +146,7 @@ module up_delay_cntrl #(
if (up_dlocked == 1'b0) begin if (up_dlocked == 1'b0) begin
up_rdata_int <= 32'hffffffff; up_rdata_int <= 32'hffffffff;
end else begin end else begin
up_rdata_int <= {27'd0, up_rdata_s}; up_rdata_int <= {{32-DRP_WIDTH{1'b0}}, up_rdata_s};
end end
end else begin end else begin
up_rdata_int <= 32'd0; up_rdata_int <= 32'd0;
@ -172,15 +162,15 @@ module up_delay_cntrl #(
for (n = 0; n < DATA_WIDTH; n = n + 1) begin: g_dinit for (n = 0; n < DATA_WIDTH; n = n + 1) begin: g_dinit
assign up_dinit_s[n] = up_dlocked_m2 & ~up_dlocked_m3; assign up_dinit_s[n] = up_dlocked_m2 & ~up_dlocked_m3;
assign up_dinitdata_s[((n*5)+4):(n*5)] = INIT_DELAY; assign up_dinitdata_s[(n*DRP_WIDTH) +: DRP_WIDTH] = INIT_DELAY;
end end
// write does not hold- read back what goes into effect. // write does not hold- read back what goes into effect.
for (n = 0; n < DATA_WIDTH; n = n + 1) begin: g_dwr for (n = 0; n < DATA_WIDTH; n = n + 1) begin: g_dwr
assign up_dld_s[n] = (up_waddr[7:0] == n) ? up_wreq_s : 1'b0; assign up_dld_s[n] = (up_waddr[7:0] == n) ? up_wreq_s : 1'b0;
assign up_dwdata_s[((n*5)+4):(n*5)] = (up_waddr[7:0] == n) ? assign up_dwdata_s[(n*DRP_WIDTH) +: DRP_WIDTH] = (up_waddr[7:0] == n) ?
up_wdata[4:0] : up_dwdata_int[((n*5)+4):(n*5)]; up_wdata[DRP_WIDTH-1:0] : up_dwdata_int[(n*DRP_WIDTH) +: DRP_WIDTH];
end end
assign up_dld = up_dld_int; assign up_dld = up_dld_int;

13
library/xilinx/common/ad_serdes_in.v
View File

@ -41,6 +41,7 @@ module ad_serdes_in #(
parameter DDR_OR_SDR_N = 0, parameter DDR_OR_SDR_N = 0,
parameter SERDES_FACTOR = 8, parameter SERDES_FACTOR = 8,
parameter DATA_WIDTH = 16, parameter DATA_WIDTH = 16,
parameter DRP_WIDTH = 5,
parameter IODELAY_CTRL = 0, parameter IODELAY_CTRL = 0,
parameter IODELAY_GROUP = "dev_if_delay_group", parameter IODELAY_GROUP = "dev_if_delay_group",
parameter REFCLK_FREQUENCY = 200) ( parameter REFCLK_FREQUENCY = 200) (
@ -71,8 +72,8 @@ module ad_serdes_in #(
input up_clk, input up_clk,
input [(DATA_WIDTH-1):0] up_dld, input [(DATA_WIDTH-1):0] up_dld,
input [((DATA_WIDTH*5)-1):0] up_dwdata, input [((DATA_WIDTH*DRP_WIDTH)-1):0] up_dwdata,
output [((DATA_WIDTH*5)-1):0] up_drdata, output [((DATA_WIDTH*DRP_WIDTH)-1):0] up_drdata,
// delay-control interface // delay-control interface
@ -150,8 +151,8 @@ module ad_serdes_in #(
.IDATAIN (data_in_ibuf_s[l_inst]), .IDATAIN (data_in_ibuf_s[l_inst]),
.DATAOUT (data_in_idelay_s[l_inst]), .DATAOUT (data_in_idelay_s[l_inst]),
.LD (up_dld[l_inst]), .LD (up_dld[l_inst]),
.CNTVALUEIN (up_dwdata[((5*l_inst)+4):(5*l_inst)]), .CNTVALUEIN (up_dwdata[DRP_WIDTH*l_inst +: DRP_WIDTH]),
.CNTVALUEOUT (up_drdata[((5*l_inst)+4):(5*l_inst)])); .CNTVALUEOUT (up_drdata[DRP_WIDTH*l_inst +: DRP_WIDTH]));
ISERDESE2 #( ISERDESE2 #(
.DATA_RATE (DATA_RATE), .DATA_RATE (DATA_RATE),
@ -240,13 +241,13 @@ module ad_serdes_in #(
) )
i_idelay( i_idelay(
.CASC_OUT (), // 1-bit output: Cascade delay output to ODELAY input cascade .CASC_OUT (), // 1-bit output: Cascade delay output to ODELAY input cascade
.CNTVALUEOUT(up_drdata[((5*l_inst)+4):(5*l_inst)]), // 9-bit output: Counter value output .CNTVALUEOUT (up_drdata[DRP_WIDTH*l_inst +: DRP_WIDTH]), // 9-bit output: Counter value output
.DATAOUT (data_in_idelay_s[l_inst]), // 1-bit output: Delayed data output .DATAOUT (data_in_idelay_s[l_inst]), // 1-bit output: Delayed data output
.CASC_IN (1'b0), // 1-bit input: Cascade delay input from slave ODELAY CASCADE_OUT .CASC_IN (1'b0), // 1-bit input: Cascade delay input from slave ODELAY CASCADE_OUT
.CASC_RETURN (1'b0), // 1-bit input: Cascade delay returning from slave ODELAY DATAOUT .CASC_RETURN (1'b0), // 1-bit input: Cascade delay returning from slave ODELAY DATAOUT
.CE (1'b0), // 1-bit input: Active high enable increment/decrement input .CE (1'b0), // 1-bit input: Active high enable increment/decrement input
.CLK (div_clk), // 1-bit input: Clock input .CLK (div_clk), // 1-bit input: Clock input
.CNTVALUEIN(up_dwdata[((5*l_inst)+4):(5*l_inst)]), // 9-bit input: Counter value input .CNTVALUEIN (up_dwdata[DRP_WIDTH*l_inst +: DRP_WIDTH]), // 9-bit input: Counter value input
.DATAIN (1'b0), // 1-bit input: Data input from the logic .DATAIN (1'b0), // 1-bit input: Data input from the logic
.EN_VTC (en_vtc), // 1-bit input: Keep delay constant over VT .EN_VTC (en_vtc), // 1-bit input: Keep delay constant over VT
.IDATAIN (data_in_ibuf_s[l_inst]), // 1-bit input: Data input from the IOBUF .IDATAIN (data_in_ibuf_s[l_inst]), // 1-bit input: Data input from the IOBUF