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Istvan Csomortani 2016-01-14 14:37:56 +02:00
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// ***************************************************************************
// ***************************************************************************
// Copyright 2015(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
// IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module axi_ad9684 (
// device interface ports
adc_clk_in_p,
adc_clk_in_n,
adc_data_in_p,
adc_data_in_n,
adc_data_or_p,
adc_data_or_n,
// dma interface ports
adc_clk,
adc_rst,
adc_valid_0,
adc_enable_0,
adc_data_0,
adc_valid_1,
adc_enable_1,
adc_data_1,
adc_dovf,
adc_dunf,
// delay clock ports
delay_clk,
// axi slave interface ports
s_axi_aclk,
s_axi_aresetn,
s_axi_awvalid,
s_axi_awaddr,
s_axi_awready,
s_axi_wvalid,
s_axi_wdata,
s_axi_wstrb,
s_axi_wready,
s_axi_bvalid,
s_axi_bresp,
s_axi_bready,
s_axi_arvalid,
s_axi_araddr,
s_axi_arready,
s_axi_rvalid,
s_axi_rresp,
s_axi_rdata,
s_axi_rready
);
// parameters
parameter ID = 0;
parameter DEVICE_TYPE = 0;
parameter IO_DELAY_GROUP = "dev_if_delay_group";
parameter OR_STATUS = 1;
// IO definitions
input adc_clk_in_p;
input adc_clk_in_n;
input [13:0] adc_data_in_p;
input [13:0] adc_data_in_n;
input adc_data_or_p;
input adc_data_or_n;
output adc_clk;
output adc_rst;
output adc_valid_0;
output adc_enable_0;
output [31:0] adc_data_0;
output adc_valid_1;
output adc_enable_1;
output [31:0] adc_data_1;
input adc_dovf;
input adc_dunf;
input delay_clk;
input s_axi_aclk;
input s_axi_aresetn;
input s_axi_awvalid;
input [31:0] s_axi_awaddr;
output s_axi_awready;
input s_axi_wvalid;
input [31:0] s_axi_wdata;
input [ 3:0] s_axi_wstrb;
output s_axi_wready;
output s_axi_bvalid;
output [ 1:0] s_axi_bresp;
input s_axi_bready;
input s_axi_arvalid;
input [31:0] s_axi_araddr;
output s_axi_arready;
output s_axi_rvalid;
output [ 1:0] s_axi_rresp;
output [31:0] s_axi_rdata;
input s_axi_rready;
// internal registers
reg up_wack = 1'b0;
reg [31:0] up_rdata = 32'b0;
reg up_rack = 1'b0;
// internal clocks & resets
wire up_clk;
wire up_rstn;
wire delay_rst;
// internal signals
wire [55:0] adc_rawdata_s;
wire [27:0] adc_rawdata_0_s;
wire [27:0] adc_rawdata_1_s;
wire adc_or_0_s;
wire adc_or_1_s;
wire adc_status_s;
wire adc_or_s;
wire [14:0] up_dld_s;
wire [74:0] up_dwdata_s;
wire [74:0] up_drdata_s;
wire delay_locked_s;
wire up_status_pn_err_s;
wire up_status_pn_oos_s;
wire up_status_or_s;
wire [ 1:0] up_adc_pn_err_s;
wire [ 1:0] up_adc_pn_oos_s;
wire [ 1:0] up_adc_or_s;
wire up_rreq_s;
wire [13:0] up_raddr_s;
wire [31:0] up_rdata_s[0:3];
wire up_rack_s[0:3];
wire up_wack_s[0:3];
wire up_wreq_s;
wire [13:0] up_waddr_s;
wire [31:0] up_wdata_s;
wire up_drp_sel_s;
wire up_drp_wr_s;
wire [11:0] up_drp_addr_s;
wire [15:0] up_drp_wdata_s;
wire [15:0] up_drp_rdata_s;
wire up_drp_ready_s;
wire up_drp_locked_s;
wire mmcm_rst_s;
//defaults
assign up_clk = s_axi_aclk;
assign up_rstn = s_axi_aresetn;
assign adc_valid = 1'b1;
// processor read interface
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_rdata <= 32'd0;
up_rack <= 1'd0;
up_wack <= 1'd0;
end else begin
up_rdata <= up_rdata_s[0] | up_rdata_s[1] | up_rdata_s[2] | up_rdata_s[3];
up_rack <= up_rack_s[0] | up_rack_s[1] | up_rack_s[2] | up_rack_s[3];
up_wack <= up_wack_s[0] | up_wack_s[1] | up_wack_s[2] | up_wack_s[3];
end
end
// device interface instance
axi_ad9684_if #(
.DEVICE_TYPE(DEVICE_TYPE),
.IO_DELAY_GROUP(IO_DELAY_GROUP),
.OR_STATUS (OR_STATUS))
i_ad9684_if (
.adc_clk_in_p (adc_clk_in_p),
.adc_clk_in_n (adc_clk_in_n),
.adc_data_in_p (adc_data_in_p),
.adc_data_in_n (adc_data_in_n),
.adc_data_or_p (adc_data_or_p),
.adc_data_or_n (adc_data_or_n),
.adc_clk (adc_clk),
.adc_rst (adc_rst),
.adc_data_a (adc_rawdata_0_s),
.adc_or_a (adc_or_0_s),
.adc_data_b (adc_rawdata_1_s),
.adc_or_b (adc_or_1_s),
.adc_status (adc_status_s),
.delay_clk (delay_clk),
.delay_rst (delay_rst),
.delay_dload (up_dld_s),
.delay_wdata (up_dwdata_s),
.delay_rdata (up_drdata_s),
.delay_locked (delay_locked_s),
.mmcm_rst (mmcm_rst_s),
.up_clk (up_clk),
.up_rstn (up_rstn),
.up_drp_sel (up_drp_sel_s),
.up_drp_wr (up_drp_wr_s),
.up_drp_addr (up_drp_addr_s),
.up_drp_wdata (up_drp_wdata_s),
.up_drp_rdata (up_drp_rdata_s),
.up_drp_ready (up_drp_ready_s),
.up_drp_locked (up_drp_locked_s));
// common processor control instance
assign up_status_pn_err_s = up_adc_pn_err_s[0] | up_adc_pn_err_s[1];
assign up_status_pn_oos_s = up_adc_pn_oos_s[0] | up_adc_pn_oos_s[1];
assign up_status_or_s = up_adc_or_s[0] | up_adc_or_s[1];
up_adc_common #(
.ID(ID))
i_up_adc_common (
.mmcm_rst (mmcm_rst_s),
.adc_clk (adc_clk),
.adc_rst (adc_rst),
.adc_r1_mode (),
.adc_ddr_edgesel (),
.adc_pin_mode (),
.adc_status (adc_status_s),
.adc_sync_status (1'd0),
.adc_status_ovf (adc_dovf),
.adc_status_unf (adc_dunf),
.adc_clk_ratio (32'b1),
.adc_start_code (),
.adc_sync (),
.up_status_pn_err (up_status_pn_err_s),
.up_status_pn_oos (up_status_pn_oos_s),
.up_status_or (up_status_or_s),
.up_drp_sel (up_drp_sel_s),
.up_drp_wr (up_drp_wr_s),
.up_drp_addr (up_drp_addr_s),
.up_drp_wdata (up_drp_wdata_s),
.up_drp_rdata (up_drp_rdata_s),
.up_drp_ready (up_drp_ready_s),
.up_drp_locked (up_drp_locked_s),
.up_usr_chanmax (),
.adc_usr_chanmax (8'd1),
.up_adc_gpio_in (32'd0),
.up_adc_gpio_out (),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (up_wack_s[0]),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (up_rdata_s[0]),
.up_rack (up_rack_s[0]));
// adc channel 0 instance
axi_ad9684_channel #(
.CHANNEL_ID (0),
.Q_OR_I_N (0))
i_channel_0 (
.adc_clk (adc_clk),
.adc_rst (adc_rst),
.adc_data (adc_rawdata_0_s),
.adc_data_q (adc_rawdata_1_s),
.adc_or (adc_or_0_s),
.adc_dfmt_data (adc_data_0),
.adc_valid (adc_valid_0),
.adc_enable (adc_enable_0),
.up_adc_pn_err (up_adc_pn_err_s[0]),
.up_adc_pn_oos (up_adc_pn_oos_s[0]),
.up_adc_or (up_adc_or_s[0]),
.up_clk (up_clk),
.up_rstn (up_rstn),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (up_wack_s[1]),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (up_rdata_s[1]),
.up_rack (up_rack_s[1]));
// adc channel 1 instance
axi_ad9684_channel #(
.CHANNEL_ID (1),
.Q_OR_I_N (1))
i_channel_1 (
.adc_clk (adc_clk),
.adc_rst (adc_rst),
.adc_data (adc_rawdata_1_s),
.adc_data_q (adc_rawdata_0_s),
.adc_or (adc_or_1_s),
.adc_dfmt_data (adc_data_1),
.adc_valid (adc_valid_1),
.adc_enable (adc_enable_1),
.up_adc_pn_err (up_adc_pn_err_s[1]),
.up_adc_pn_oos (up_adc_pn_oos_s[1]),
.up_adc_or (up_adc_or_s[1] ),
.up_clk (up_clk),
.up_rstn (up_rstn),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (up_wack_s[2]),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (up_rdata_s[2]),
.up_rack (up_rack_s[2]));
// adc delay control instance
up_delay_cntrl #(
.DATA_WIDTH(15))
i_delay_cntrl (
.delay_clk (delay_clk),
.delay_rst (delay_rst),
.delay_locked (delay_locked_s),
.up_dld (up_dld_s),
.up_dwdata (up_dwdata_s),
.up_drdata (up_drdata_s),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (up_wack_s[3]),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (up_rdata_s[3]),
.up_rack (up_rack_s[3]));
// uP bus interface instance
up_axi i_up_axi (
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_axi_awvalid (s_axi_awvalid),
.up_axi_awaddr (s_axi_awaddr),
.up_axi_awready (s_axi_awready),
.up_axi_wvalid (s_axi_wvalid),
.up_axi_wdata (s_axi_wdata),
.up_axi_wstrb (s_axi_wstrb),
.up_axi_wready (s_axi_wready),
.up_axi_bvalid (s_axi_bvalid),
.up_axi_bresp (s_axi_bresp),
.up_axi_bready (s_axi_bready),
.up_axi_arvalid (s_axi_arvalid),
.up_axi_araddr (s_axi_araddr),
.up_axi_arready (s_axi_arready),
.up_axi_rvalid (s_axi_rvalid),
.up_axi_rresp (s_axi_rresp),
.up_axi_rdata (s_axi_rdata),
.up_axi_rready (s_axi_rready),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (up_wack),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (up_rdata),
.up_rack (up_rack));
endmodule

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// ***************************************************************************
// ***************************************************************************
// Copyright 2015(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
// IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module axi_ad9684_channel (
// adc data interface
adc_clk,
adc_rst,
adc_data,
adc_data_q,
adc_or,
// channel interface
adc_dfmt_data,
adc_valid,
adc_enable,
up_adc_pn_err,
up_adc_pn_oos,
up_adc_or,
// up interface
up_clk,
up_rstn,
up_wreq,
up_waddr,
up_wdata,
up_wack,
up_rreq,
up_raddr,
up_rdata,
up_rack
);
// parameters
parameter Q_OR_I_N = 0;
parameter CHANNEL_ID = 0;
parameter DATAPATH_DISABLE = 0;
// IO definitions
input adc_clk;
input adc_rst;
input [27:0] adc_data;
input [27:0] adc_data_q;
input adc_or;
output [31:0] adc_dfmt_data;
output adc_enable;
output adc_valid;
output up_adc_pn_err;
output up_adc_pn_oos;
output up_adc_or;
input up_clk;
input up_rstn;
input up_wreq;
input [13:0] up_waddr;
input [31:0] up_wdata;
output up_wack;
input up_rreq;
input [13:0] up_raddr;
output [31:0] up_rdata;
output up_rack;
// internal signals
wire adc_pn_oos_s;
wire adc_pn_err_s;
wire adc_dfmt_enable_s;
wire adc_dfmt_type_s;
wire adc_dfmt_se_s;
wire [ 1:0] adc_dfmt_valid_s;
wire [ 3:0] adc_pnseq_sel_s;
// instantiations
axi_ad9684_pnmon i_pnmon (
.adc_clk (adc_clk),
.adc_data (adc_data),
.adc_pn_oos (adc_pn_oos_s),
.adc_pn_err (adc_pn_err_s),
.adc_pnseq_sel (adc_pnseq_sel_s));
genvar n;
generate
for (n = 0; n < 2; n = n + 1) begin: g_ad_datafmt_1
ad_datafmt #(.DATA_WIDTH(14)) i_ad_datafmt (
.clk (adc_clk),
.valid (1'b1),
.data (adc_data[n*14+13:n*14]),
.valid_out (adc_dfmt_valid_s[n]),
.data_out (adc_dfmt_data[n*16+15:n*16]),
.dfmt_enable (adc_dfmt_enable_s),
.dfmt_type (adc_dfmt_type_s),
.dfmt_se (adc_dfmt_se_s));
end
endgenerate
assign adc_valid = adc_dfmt_valid_s[0] | adc_dfmt_valid_s[1];
up_adc_channel #(.ADC_CHANNEL_ID(CHANNEL_ID)) i_up_adc_channel (
.adc_clk (adc_clk),
.adc_rst (adc_rst),
.adc_enable (adc_enable),
.adc_iqcor_enb (),
.adc_dcfilt_enb (),
.adc_dfmt_se (adc_dfmt_se_s),
.adc_dfmt_type (adc_dfmt_type_s),
.adc_dfmt_enable (adc_dfmt_enable_s),
.adc_dcfilt_offset (),
.adc_dcfilt_coeff (),
.adc_iqcor_coeff_1 (),
.adc_iqcor_coeff_2 (),
.adc_pnseq_sel (adc_pnseq_sel_s),
.adc_data_sel (),
.adc_pn_err (adc_pn_err_s),
.adc_pn_oos (adc_pn_oos_s),
.adc_or (adc_or),
.up_adc_pn_err (up_adc_pn_err),
.up_adc_pn_oos (up_adc_pn_oos),
.up_adc_or (up_adc_or),
.up_usr_datatype_be (),
.up_usr_datatype_signed (),
.up_usr_datatype_shift (),
.up_usr_datatype_total_bits (),
.up_usr_datatype_bits (),
.up_usr_decimation_m (),
.up_usr_decimation_n (),
.adc_usr_datatype_be (1'b0),
.adc_usr_datatype_signed (1'b1),
.adc_usr_datatype_shift (8'd0),
.adc_usr_datatype_total_bits (8'd16),
.adc_usr_datatype_bits (8'd16),
.adc_usr_decimation_m (16'd1),
.adc_usr_decimation_n (16'd1),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq),
.up_waddr (up_waddr),
.up_wdata (up_wdata),
.up_wack (up_wack),
.up_rreq (up_rreq),
.up_raddr (up_raddr),
.up_rdata (up_rdata),
.up_rack (up_rack));
endmodule

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set_false_path -from [get_cells -hier -filter {name =~ *up_drp_locked_reg && IS_SEQUENTIAL}]
-to [get_cells -hier -filter {name =~ *adc_status_m1_reg && IS_SEQUENTIAL}]

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// ***************************************************************************
// ***************************************************************************
// Copyright 2015(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
// IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module axi_ad9684_if (
// device interface
adc_clk_in_p,
adc_clk_in_n,
adc_data_in_p,
adc_data_in_n,
adc_data_or_p,
adc_data_or_n,
// data interface
adc_clk,
adc_rst,
adc_data_a,
adc_or_a,
adc_data_b,
adc_or_b,
adc_status,
// delay interface
delay_clk,
delay_rst,
delay_dload,
delay_wdata,
delay_rdata,
delay_locked,
// mmcm_rst
mmcm_rst,
// drp interface
up_clk,
up_rstn,
up_drp_sel,
up_drp_wr,
up_drp_addr,
up_drp_wdata,
up_drp_rdata,
up_drp_ready,
up_drp_locked
);
// parameters
parameter DEVICE_TYPE = 0; // 0 - 7Series / 1 - 6Series
parameter IO_DELAY_GROUP = "dev_if_delay_group";
parameter OR_STATUS = 0;
// buffer type based on the target device
localparam DDR_OR_SDR_N = 1;
// IO definitions
input adc_clk_in_p;
input adc_clk_in_n;
input [13:0] adc_data_in_p;
input [13:0] adc_data_in_n;
input adc_data_or_p;
input adc_data_or_n;
output adc_clk;
input adc_rst;
output [27:0] adc_data_a;
output adc_or_a;
output [27:0] adc_data_b;
output adc_or_b;
output adc_status;
input delay_clk;
input delay_rst;
input [14:0] delay_dload;
input [74:0] delay_wdata;
output [74:0] delay_rdata;
output delay_locked;
input mmcm_rst;
input up_clk;
input up_rstn;
input up_drp_sel;
input up_drp_wr;
input [11:0] up_drp_addr;
input [15:0] up_drp_wdata;
output [15:0] up_drp_rdata;
output up_drp_ready;
output up_drp_locked;
// internal registers
reg adc_status = 'd0;
reg adc_status_m1 = 'd0;
// internal signals
wire adc_clk_in;
wire adc_div_clk;
wire [ 1:0] adc_data_or_a_s;
wire [ 1:0] adc_data_or_b_s;
genvar l_inst;
// adc_clk is 1:2 of the sampling clock
// f_max = 250 MHz
assign adc_clk = adc_div_clk;
// data interface
ad_serdes_in #(
.DEVICE_TYPE(DEVICE_TYPE),
.IODELAY_CTRL(1),
.IODELAY_GROUP(IO_DELAY_GROUP),
.DDR_OR_SDR_N(DDR_OR_SDR_N),
.DATA_WIDTH(4))
i_adc_data (
.rst(adc_rst),
.clk(adc_clk_in),
.div_clk(adc_div_clk),
.data_s0(adc_data_b[(1*14)]),
.data_s1(adc_data_a[(1*14)]),
.data_s2(adc_data_b[(0*14)]),
.data_s3(adc_data_a[(0*14)]),
.data_s4(),
.data_s5(),
.data_s6(),
.data_s7(),
.data_in_p(adc_data_in_p[0]),
.data_in_n(adc_data_in_n[0]),
.up_clk (up_clk),
.up_dld (delay_dload[0]),
.up_dwdata (delay_wdata[4:0]),
.up_drdata (delay_rdata[4:0]),
.delay_clk(delay_clk),
.delay_rst(delay_rst),
.delay_locked(delay_locked));
generate
for (l_inst = 1; l_inst <= 13; l_inst = l_inst + 1) begin : g_adc_if
ad_serdes_in #(
.DEVICE_TYPE(DEVICE_TYPE),
.IODELAY_CTRL(0),
.IODELAY_GROUP(IO_DELAY_GROUP),
.DDR_OR_SDR_N(DDR_OR_SDR_N),
.DATA_WIDTH(4))
i_adc_data (
.rst(adc_rst),
.clk(adc_clk_in),
.div_clk(adc_div_clk),
.data_s0(adc_data_b[(1*14)+l_inst]),
.data_s1(adc_data_a[(1*14)+l_inst]),
.data_s2(adc_data_b[(0*14)+l_inst]),
.data_s3(adc_data_a[(0*14)+l_inst]),
.data_s4(),
.data_s5(),
.data_s6(),
.data_s7(),
.data_in_p(adc_data_in_p[l_inst]),
.data_in_n(adc_data_in_n[l_inst]),
.up_clk (up_clk),
.up_dld (delay_dload[l_inst]),
.up_dwdata (delay_wdata[((l_inst*5)+4):(l_inst*5)]),
.up_drdata (delay_rdata[((l_inst*5)+4):(l_inst*5)]),
.delay_clk(delay_clk),
.delay_rst(delay_rst),
.delay_locked());
end
endgenerate
generate if (OR_STATUS == 1) begin
ad_serdes_in #(
.DEVICE_TYPE(DEVICE_TYPE),
.IODELAY_CTRL(0),
.IODELAY_GROUP(IO_DELAY_GROUP),
.DDR_OR_SDR_N(DDR_OR_SDR_N),
.DATA_WIDTH(4))
i_adc_or (
.rst(adc_rst),
.clk(adc_clk_in),
.div_clk(adc_div_clk),
.data_s0(adc_data_or_b_s[1]),
.data_s1(adc_data_or_a_s[1]),
.data_s2(adc_data_or_b_s[0]),
.data_s3(adc_data_or_a_s[0]),
.data_s4(),
.data_s5(),
.data_s6(),
.data_s7(),
.data_in_p(adc_data_or_p),
.data_in_n(adc_data_or_n),
.up_clk (up_clk),
.up_dld (delay_dload[14]),
.up_dwdata (delay_wdata[74:70]),
.up_drdata (delay_rdata[74:70]),
.delay_clk(delay_clk),
.delay_rst(delay_rst),
.delay_locked());
assign adc_or_a = adc_data_or_a_s[0] | adc_data_or_a_s[1];
assign adc_or_b = adc_data_or_b_s[0] | adc_data_or_b_s[1];
end else begin
assign adc_or_a = 1'b0;
assign adc_or_b = 1'b0;
end
endgenerate
// clock input buffers and MMCM_OR_BUFR_N
ad_serdes_clk #(
.MMCM_DEVICE_TYPE (DEVICE_TYPE),
.MMCM_CLKIN_PERIOD (2),
.MMCM_VCO_DIV (6),
.MMCM_VCO_MUL (12),
.MMCM_CLK0_DIV (2),
.MMCM_CLK1_DIV (4))
i_serdes_clk (
.mmcm_rst (mmcm_rst),
.clk_in_p (adc_clk_in_p),
.clk_in_n (adc_clk_in_n),
.clk (adc_clk_in),
.div_clk (adc_div_clk),
.up_clk (up_clk),
.up_rstn (up_rstn),
.up_drp_sel (up_drp_sel),
.up_drp_wr (up_drp_wr),
.up_drp_addr (up_drp_addr),
.up_drp_wdata (up_drp_wdata),
.up_drp_rdata (up_drp_rdata),
.up_drp_ready (up_drp_ready),
.up_drp_locked (up_drp_locked));
// adc status: adc is up, if both the MMCM_OR_BUFR_N and DELAY blocks are up
always @(posedge adc_div_clk) begin
if(adc_rst == 1'b1) begin
adc_status_m1 <= 1'b0;
adc_status <= 1'b0;
end else begin
adc_status_m1 <= up_drp_locked;
adc_status <= adc_status_m1;
end
end
endmodule

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library/axi_ad9684/axi_ad9684_ip.tcl Normal file
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# ip
source ../scripts/adi_env.tcl
source $ad_hdl_dir/library/scripts/adi_ip.tcl
adi_ip_create axi_ad9684
adi_ip_files axi_ad9684 [list \
"$ad_hdl_dir/library/common/ad_rst.v" \
"$ad_hdl_dir/library/common/ad_serdes_in.v" \
"$ad_hdl_dir/library/common/ad_serdes_clk.v" \
"$ad_hdl_dir/library/common/ad_mmcm_drp.v" \
"$ad_hdl_dir/library/common/ad_datafmt.v" \
"$ad_hdl_dir/library/common/ad_pnmon.v" \
"$ad_hdl_dir/library/common/up_xfer_status.v" \
"$ad_hdl_dir/library/common/up_xfer_cntrl.v" \
"$ad_hdl_dir/library/common/up_clock_mon.v" \
"$ad_hdl_dir/library/common/up_delay_cntrl.v" \
"$ad_hdl_dir/library/common/up_adc_common.v" \
"$ad_hdl_dir/library/common/up_adc_channel.v" \
"$ad_hdl_dir/library/common/up_axi.v" \
"$ad_hdl_dir/library/common/ad_axi_ip_constr.xdc" \
"axi_ad9684_pnmon.v" \
"axi_ad9684_if.v" \
"axi_ad9684_channel.v" \
"axi_ad9684_constr.xdc" \
"axi_ad9684.v"]
adi_ip_properties axi_ad9684
adi_ip_constraints axi_ad9684 [list \
"axi_ad9684_constr.xdc" \
"$ad_hdl_dir/library/common/ad_axi_ip_constr.xdc"]
set_property driver_value 0 [ipx::get_ports *dovf* -of_objects [ipx::current_core]]
set_property driver_value 0 [ipx::get_ports *dunf* -of_objects [ipx::current_core]]
ipx::save_core [ipx::current_core]

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// ***************************************************************************
// ***************************************************************************
// Copyright 2015(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// PN monitors
`timescale 1ns/100ps
module axi_ad9684_pnmon (
// adc interface
adc_clk,
adc_data,
// pn out of sync and error
adc_pn_oos,
adc_pn_err,
// processor interface PN9 (0x0), PN23 (0x1)
adc_pnseq_sel);
// adc interface
input adc_clk;
input [27:0] adc_data;
// pn out of sync and error
output adc_pn_oos;
output adc_pn_err;
// processor interface PN9 (0x0), PN23 (0x1)
input [ 3:0] adc_pnseq_sel;
// internal registers
reg [27:0] adc_pn_data_in = 'd0;
reg [27:0] adc_pn_data_pn = 'd0;
// internal signals
wire [27:0] adc_pn_data_pn_s;
// PN23 function
function [27:0] pn23;
input [27:0] din;
reg [27:0] dout;
begin
dout[27] = din[22] ^ din[17];
dout[26] = din[21] ^ din[16];
dout[25] = din[20] ^ din[15];
dout[24] = din[19] ^ din[14];
dout[23] = din[18] ^ din[13];
dout[22] = din[17] ^ din[12];
dout[21] = din[16] ^ din[11];
dout[20] = din[15] ^ din[10];
dout[19] = din[14] ^ din[ 9];
dout[18] = din[13] ^ din[ 8];
dout[17] = din[12] ^ din[ 7];
dout[16] = din[11] ^ din[ 6];
dout[15] = din[10] ^ din[ 5];
dout[14] = din[ 9] ^ din[ 4];
dout[13] = din[ 8] ^ din[ 3];
dout[12] = din[ 7] ^ din[ 2];
dout[11] = din[ 6] ^ din[ 1];
dout[10] = din[ 5] ^ din[ 0];
dout[ 9] = din[ 4] ^ din[22] ^ din[17];
dout[ 8] = din[ 3] ^ din[21] ^ din[16];
dout[ 7] = din[ 2] ^ din[20] ^ din[15];
dout[ 6] = din[ 1] ^ din[19] ^ din[14];
dout[ 5] = din[ 0] ^ din[18] ^ din[13];
dout[ 4] = din[22] ^ din[12];
dout[ 3] = din[21] ^ din[11];
dout[ 2] = din[20] ^ din[10];
dout[ 1] = din[19] ^ din[ 9];
dout[ 0] = din[18] ^ din[ 8];
pn23 = dout;
end
endfunction
// PN9 function
function [27:0] pn9;
input [27:0] din;
reg [27:0] dout;
begin
dout[27] = din[ 8] ^ din[ 4];
dout[26] = din[ 7] ^ din[ 3];
dout[25] = din[ 6] ^ din[ 2];
dout[24] = din[ 5] ^ din[ 1];
dout[23] = din[ 4] ^ din[ 0];
dout[22] = din[ 3] ^ din[ 8] ^ din[ 4];
dout[21] = din[ 2] ^ din[ 7] ^ din[ 3];
dout[20] = din[ 1] ^ din[ 6] ^ din[ 2];
dout[19] = din[ 0] ^ din[ 5] ^ din[ 1];
dout[18] = din[ 8] ^ din[ 0];
dout[17] = din[ 7] ^ din[ 8] ^ din[ 4];
dout[16] = din[ 6] ^ din[ 7] ^ din[ 3];
dout[15] = din[ 5] ^ din[ 6] ^ din[ 2];
dout[14] = din[ 4] ^ din[ 5] ^ din[ 1];
dout[13] = din[ 3] ^ din[ 4] ^ din[ 0];
dout[12] = din[ 2] ^ din[ 3] ^ din[ 8] ^ din[ 4];
dout[11] = din[ 1] ^ din[ 2] ^ din[ 7] ^ din[ 3];
dout[10] = din[ 0] ^ din[ 1] ^ din[ 6] ^ din[ 2];
dout[ 9] = din[ 8] ^ din[ 0] ^ din[ 4] ^ din[ 5] ^ din[ 1];
dout[ 8] = din[ 7] ^ din[ 8] ^ din[ 3] ^ din[ 0];
dout[ 7] = din[ 6] ^ din[ 7] ^ din[ 2] ^ din[ 8] ^ din[ 4];
dout[ 6] = din[ 5] ^ din[ 6] ^ din[ 1] ^ din[ 7] ^ din[ 3];
dout[ 5] = din[ 4] ^ din[ 5] ^ din[ 0] ^ din[ 6] ^ din[ 2];
dout[ 4] = din[ 3] ^ din[ 8] ^ din[ 5] ^ din[ 1];
dout[ 3] = din[ 2] ^ din[ 4] ^ din[ 7] ^ din[ 0];
dout[ 2] = din[ 1] ^ din[ 3] ^ din[ 6] ^ din[ 8] ^ din[ 4];
dout[ 1] = din[ 0] ^ din[ 2] ^ din[ 5] ^ din[ 7] ^ din[ 3];
dout[ 0] = din[ 8] ^ din[ 1] ^ din[ 6] ^ din[ 2];
pn9 = dout;
end
endfunction
// pn sequence select
assign adc_pn_data_pn_s = (adc_pn_oos == 1'b1) ? adc_pn_data_in : adc_pn_data_pn;
always @(posedge adc_clk) begin
adc_pn_data_in <= { ~adc_data[13], adc_data[12: 0],
~adc_data[27], adc_data[26:14]};
if (adc_pnseq_sel == 4'd0) begin
adc_pn_data_pn <= pn9(adc_pn_data_pn_s);
end else begin
adc_pn_data_pn <= pn23(adc_pn_data_pn_s);
end
end
// pn oos & pn err
ad_pnmon #(.DATA_WIDTH(28)) i_pnmon (
.adc_clk (adc_clk),
.adc_valid_in (1'b1),
.adc_data_in (adc_pn_data_in),
.adc_data_pn (adc_pn_data_pn),
.adc_pn_oos (adc_pn_oos),
.adc_pn_err (adc_pn_err));
endmodule
// ***************************************************************************
// ***************************************************************************