From c6ebab7393ef04fd54864b215f8acd709cef7b0d Mon Sep 17 00:00:00 2001 From: Rejeesh Kutty Date: Mon, 1 Jun 2015 13:37:07 -0400 Subject: [PATCH] library- drp moved to up clock --- library/axi_ad9122/axi_ad9122.v | 50 ++- library/axi_ad9122/axi_ad9122_core.v | 50 ++- library/axi_ad9122/axi_ad9122_if.v | 58 ++- library/axi_ad9144/axi_ad9144_core.v | 16 +- library/axi_ad9265/axi_ad9265.v | 16 +- library/axi_ad9680/axi_ad9680.v | 16 +- library/axi_clkgen/axi_clkgen.v | 53 ++- library/axi_clkgen/axi_clkgen_constr.xdc | 45 --- library/axi_clkgen/axi_clkgen_ip.tcl | 1 - library/axi_jesd_gt/axi_jesd_gt.v | 419 ++++++++++----------- library/axi_jesd_gt/axi_jesd_gt_constr.xdc | 89 ----- library/axi_jesd_gt/axi_jesd_gt_ip.tcl | 11 +- 12 files changed, 317 insertions(+), 507 deletions(-) diff --git a/library/axi_ad9122/axi_ad9122.v b/library/axi_ad9122/axi_ad9122.v index 29d91bcf1..29ff3cddb 100644 --- a/library/axi_ad9122/axi_ad9122.v +++ b/library/axi_ad9122/axi_ad9122.v @@ -34,8 +34,6 @@ // THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // *************************************************************************** // *************************************************************************** -// *************************************************************************** -// *************************************************************************** `timescale 1ns/100ps @@ -154,7 +152,6 @@ module axi_ad9122 ( wire dac_rst; wire mmcm_rst; - wire drp_rst; wire up_clk; wire up_rstn; @@ -177,13 +174,13 @@ module axi_ad9122 ( wire dac_frame_q3_s; wire [15:0] dac_data_q3_s; wire dac_status_s; - wire drp_sel_s; - wire drp_wr_s; - wire [11:0] drp_addr_s; - wire [15:0] drp_wdata_s; - wire [15:0] drp_rdata_s; - wire drp_ready_s; - wire drp_locked_s; + wire up_drp_sel_s; + wire up_drp_wr_s; + wire [11:0] up_drp_addr_s; + wire [15:0] up_drp_wdata_s; + wire [15:0] up_drp_rdata_s; + wire up_drp_ready_s; + wire up_drp_locked_s; wire up_wreq_s; wire [13:0] up_waddr_s; wire [31:0] up_wdata_s; @@ -234,15 +231,15 @@ module axi_ad9122 ( .dac_frame_q3 (dac_frame_q3_s), .dac_data_q3 (dac_data_q3_s), .mmcm_rst (mmcm_rst), - .drp_clk (up_clk), - .drp_rst (drp_rst), - .drp_sel (drp_sel_s), - .drp_wr (drp_wr_s), - .drp_addr (drp_addr_s), - .drp_wdata (drp_wdata_s), - .drp_rdata (drp_rdata_s), - .drp_ready (drp_ready_s), - .drp_locked (drp_locked_s)); + .up_clk (up_clk), + .up_rstn (up_rstn), + .up_drp_sel (up_drp_sel_s), + .up_drp_wr (up_drp_wr_s), + .up_drp_addr (up_drp_addr_s), + .up_drp_wdata (up_drp_wdata_s), + .up_drp_rdata (up_drp_rdata_s), + .up_drp_ready (up_drp_ready_s), + .up_drp_locked (up_drp_locked_s)); // core @@ -277,14 +274,13 @@ module axi_ad9122 ( .dac_dovf (dac_dovf), .dac_dunf (dac_dunf), .mmcm_rst (mmcm_rst), - .drp_rst (drp_rst), - .drp_sel (drp_sel_s), - .drp_wr (drp_wr_s), - .drp_addr (drp_addr_s), - .drp_wdata (drp_wdata_s), - .drp_rdata (drp_rdata_s), - .drp_ready (drp_ready_s), - .drp_locked (drp_locked_s), + .up_drp_sel (up_drp_sel_s), + .up_drp_wr (up_drp_wr_s), + .up_drp_addr (up_drp_addr_s), + .up_drp_wdata (up_drp_wdata_s), + .up_drp_rdata (up_drp_rdata_s), + .up_drp_ready (up_drp_ready_s), + .up_drp_locked (up_drp_locked_s), .up_rstn (up_rstn), .up_clk (up_clk), .up_wreq (up_wreq_s), diff --git a/library/axi_ad9122/axi_ad9122_core.v b/library/axi_ad9122/axi_ad9122_core.v index 23b97645e..c9245e64b 100644 --- a/library/axi_ad9122/axi_ad9122_core.v +++ b/library/axi_ad9122/axi_ad9122_core.v @@ -34,8 +34,6 @@ // THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // *************************************************************************** // *************************************************************************** -// *************************************************************************** -// *************************************************************************** `timescale 1ns/100ps @@ -85,14 +83,14 @@ module axi_ad9122_core ( // drp interface - drp_rst, - drp_sel, - drp_wr, - drp_addr, - drp_wdata, - drp_rdata, - drp_ready, - drp_locked, + up_drp_rst, + up_drp_sel, + up_drp_wr, + up_drp_addr, + up_drp_wdata, + up_drp_rdata, + up_drp_ready, + up_drp_locked, // processor interface @@ -156,14 +154,14 @@ module axi_ad9122_core ( // drp interface - output drp_rst; - output drp_sel; - output drp_wr; - output [11:0] drp_addr; - output [15:0] drp_wdata; - input [15:0] drp_rdata; - input drp_ready; - input drp_locked; + output up_drp_rst; + output up_drp_sel; + output up_drp_wr; + output [11:0] up_drp_addr; + output [15:0] up_drp_wdata; + input [15:0] up_drp_rdata; + input up_drp_ready; + input up_drp_locked; // processor interface @@ -291,15 +289,13 @@ module axi_ad9122_core ( .dac_status_ovf (dac_dovf), .dac_status_unf (dac_dunf), .dac_clk_ratio (32'd4), - .drp_clk (up_clk), - .drp_rst (drp_rst), - .drp_sel (drp_sel), - .drp_wr (drp_wr), - .drp_addr (drp_addr), - .drp_wdata (drp_wdata), - .drp_rdata (drp_rdata), - .drp_ready (drp_ready), - .drp_locked (drp_locked), + .up_drp_sel (up_drp_sel), + .up_drp_wr (up_drp_wr), + .up_drp_addr (up_drp_addr), + .up_drp_wdata (up_drp_wdata), + .up_drp_rdata (up_drp_rdata), + .up_drp_ready (up_drp_ready), + .up_drp_locked (up_drp_locked), .up_usr_chanmax (), .dac_usr_chanmax (8'd3), .up_dac_gpio_in (32'd0), diff --git a/library/axi_ad9122/axi_ad9122_if.v b/library/axi_ad9122/axi_ad9122_if.v index 9700aae83..72f0f5262 100644 --- a/library/axi_ad9122/axi_ad9122_if.v +++ b/library/axi_ad9122/axi_ad9122_if.v @@ -34,8 +34,6 @@ // THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // *************************************************************************** // *************************************************************************** -// *************************************************************************** -// *************************************************************************** // This is the dac physical interface (drives samples from the low speed clock to the // dac clock domain. @@ -87,15 +85,15 @@ module axi_ad9122_if ( // drp interface - drp_clk, - drp_rst, - drp_sel, - drp_wr, - drp_addr, - drp_wdata, - drp_rdata, - drp_ready, - drp_locked); + up_clk, + up_rstn, + up_drp_sel, + up_drp_wr, + up_drp_addr, + up_drp_wdata, + up_drp_rdata, + up_drp_ready, + up_drp_locked); // parameters @@ -148,15 +146,15 @@ module axi_ad9122_if ( // drp interface - input drp_clk; - input drp_rst; - input drp_sel; - input drp_wr; - input [11:0] drp_addr; - input [15:0] drp_wdata; - output [15:0] drp_rdata; - output drp_ready; - output drp_locked; + input up_clk; + input up_rstn; + input up_drp_sel; + input up_drp_wr; + input [11:0] up_drp_addr; + input [15:0] up_drp_wdata; + output [15:0] up_drp_rdata; + output up_drp_ready; + output up_drp_locked; // internal registers @@ -170,7 +168,7 @@ module axi_ad9122_if ( dac_status_m1 <= 1'd0; dac_status <= 1'd0; end else begin - dac_status_m1 <= drp_locked; + dac_status_m1 <= up_drp_locked; dac_status <= dac_status_m1; end end @@ -255,15 +253,15 @@ module axi_ad9122_if ( .clk_in_n (dac_clk_in_n), .clk (dac_clk), .div_clk (dac_div_clk), - .drp_clk (drp_clk), - .drp_rst (drp_rst), - .drp_sel (drp_sel), - .drp_wr (drp_wr), - .drp_addr (drp_addr), - .drp_wdata (drp_wdata), - .drp_rdata (drp_rdata), - .drp_ready (drp_ready), - .drp_locked (drp_locked)); + .up_clk (up_clk), + .up_rstn (up_rstn), + .up_drp_sel (up_drp_sel), + .up_drp_wr (up_drp_wr), + .up_drp_addr (up_drp_addr), + .up_drp_wdata (up_drp_wdata), + .up_drp_rdata (up_drp_rdata), + .up_drp_ready (up_drp_ready), + .up_drp_locked (up_drp_locked)); endmodule diff --git a/library/axi_ad9144/axi_ad9144_core.v b/library/axi_ad9144/axi_ad9144_core.v index 1c3e4a838..1d4e2b1f3 100644 --- a/library/axi_ad9144/axi_ad9144_core.v +++ b/library/axi_ad9144/axi_ad9144_core.v @@ -296,15 +296,13 @@ module axi_ad9144_core ( .dac_status_ovf (dac_dovf), .dac_status_unf (dac_dunf), .dac_clk_ratio (32'd40), - .drp_clk (up_clk), - .drp_rst (), - .drp_sel (), - .drp_wr (), - .drp_addr (), - .drp_wdata (), - .drp_rdata (16'd0), - .drp_ready (1'd0), - .drp_locked (1'd1), + .up_drp_sel (), + .up_drp_wr (), + .up_drp_addr (), + .up_drp_wdata (), + .up_drp_rdata (16'd0), + .up_drp_ready (1'd0), + .up_drp_locked (1'd1), .up_usr_chanmax (), .dac_usr_chanmax (8'd3), .up_dac_gpio_in (32'd0), diff --git a/library/axi_ad9265/axi_ad9265.v b/library/axi_ad9265/axi_ad9265.v index c8c587fd8..c36994fbb 100644 --- a/library/axi_ad9265/axi_ad9265.v +++ b/library/axi_ad9265/axi_ad9265.v @@ -290,15 +290,13 @@ module axi_ad9265 ( .up_status_pn_err (up_status_pn_err), .up_status_pn_oos (up_status_pn_oos), .up_status_or (up_status_or), - .drp_clk (1'd0), - .drp_rst (), - .drp_sel (), - .drp_wr (), - .drp_addr (), - .drp_wdata (), - .drp_rdata (16'd0), - .drp_ready (1'd0), - .drp_locked (1'd1), + .up_drp_sel (), + .up_drp_wr (), + .up_drp_addr (), + .up_drp_wdata (), + .up_drp_rdata (16'd0), + .up_drp_ready (1'd0), + .up_drp_locked (1'd1), .up_usr_chanmax (), .adc_usr_chanmax (8'd0), .up_adc_gpio_in (32'd0), diff --git a/library/axi_ad9680/axi_ad9680.v b/library/axi_ad9680/axi_ad9680.v index f5a70f2a5..34f4a2673 100644 --- a/library/axi_ad9680/axi_ad9680.v +++ b/library/axi_ad9680/axi_ad9680.v @@ -269,15 +269,13 @@ module axi_ad9680 ( .up_status_pn_err (up_status_pn_err), .up_status_pn_oos (up_status_pn_oos), .up_status_or (up_status_or), - .drp_clk (1'd0), - .drp_rst (), - .drp_sel (), - .drp_wr (), - .drp_addr (), - .drp_wdata (), - .drp_rdata (16'd0), - .drp_ready (1'd0), - .drp_locked (1'd1), + .up_drp_sel (), + .up_drp_wr (), + .up_drp_addr (), + .up_drp_wdata (), + .up_drp_rdata (16'd0), + .up_drp_ready (1'd0), + .up_drp_locked (1'd1), .up_usr_chanmax (), .adc_usr_chanmax (8'd1), .up_adc_gpio_in (32'd0), diff --git a/library/axi_clkgen/axi_clkgen.v b/library/axi_clkgen/axi_clkgen.v index a4c915272..92caa870b 100644 --- a/library/axi_clkgen/axi_clkgen.v +++ b/library/axi_clkgen/axi_clkgen.v @@ -34,8 +34,6 @@ // THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // *************************************************************************** // *************************************************************************** -// *************************************************************************** -// *************************************************************************** // software programmable clock generator (still needs a reference input!) module axi_clkgen ( @@ -45,7 +43,6 @@ module axi_clkgen ( clk, clk_0, clk_1, - drp_clk, // axi interface @@ -84,7 +81,6 @@ module axi_clkgen ( input clk; output clk_0; output clk_1; - input drp_clk; // axi interface @@ -111,19 +107,18 @@ module axi_clkgen ( // reset and clocks wire mmcm_rst; - wire drp_rst; wire up_rstn; wire up_clk; // internal signals - wire drp_sel_s; - wire drp_wr_s; - wire [11:0] drp_addr_s; - wire [15:0] drp_wdata_s; - wire [15:0] drp_rdata_s; - wire drp_ready_s; - wire drp_locked_s; + wire up_drp_sel_s; + wire up_drp_wr_s; + wire [11:0] up_drp_addr_s; + wire [15:0] up_drp_wdata_s; + wire [15:0] up_drp_rdata_s; + wire up_drp_ready_s; + wire up_drp_locked_s; wire up_wreq_s; wire [13:0] up_waddr_s; wire [31:0] up_wdata_s; @@ -173,15 +168,13 @@ module axi_clkgen ( up_clkgen i_up_clkgen ( .mmcm_rst (mmcm_rst), - .drp_clk (drp_clk), - .drp_rst (drp_rst), - .drp_sel (drp_sel_s), - .drp_wr (drp_wr_s), - .drp_addr (drp_addr_s), - .drp_wdata (drp_wdata_s), - .drp_rdata (drp_rdata_s), - .drp_ready (drp_ready_s), - .drp_locked (drp_locked_s), + .up_drp_sel (up_drp_sel_s), + .up_drp_wr (up_drp_wr_s), + .up_drp_addr (up_drp_addr_s), + .up_drp_wdata (up_drp_wdata_s), + .up_drp_rdata (up_drp_rdata_s), + .up_drp_ready (up_drp_ready_s), + .up_drp_locked (up_drp_locked_s), .up_rstn (up_rstn), .up_clk (up_clk), .up_wreq (up_wreq_s), @@ -207,15 +200,15 @@ module axi_clkgen ( .mmcm_rst (mmcm_rst), .mmcm_clk_0 (clk_0), .mmcm_clk_1 (clk_1), - .drp_clk (drp_clk), - .drp_rst (drp_rst), - .drp_sel (drp_sel_s), - .drp_wr (drp_wr_s), - .drp_addr (drp_addr_s), - .drp_wdata (drp_wdata_s), - .drp_rdata (drp_rdata_s), - .drp_ready (drp_ready_s), - .drp_locked (drp_locked_s)); + .up_clk (up_clk), + .up_rstn (up_rstn), + .up_drp_sel (up_drp_sel_s), + .up_drp_wr (up_drp_wr_s), + .up_drp_addr (up_drp_addr_s), + .up_drp_wdata (up_drp_wdata_s), + .up_drp_rdata (up_drp_rdata_s), + .up_drp_ready (up_drp_ready_s), + .up_drp_locked (up_drp_locked_s)); endmodule diff --git a/library/axi_clkgen/axi_clkgen_constr.xdc b/library/axi_clkgen/axi_clkgen_constr.xdc index 00bb3229a..e69de29bb 100644 --- a/library/axi_clkgen/axi_clkgen_constr.xdc +++ b/library/axi_clkgen/axi_clkgen_constr.xdc @@ -1,45 +0,0 @@ -set up_clk [get_clocks -of_objects [get_ports s_axi_aclk]] -set delay_clk [get_clocks -of_objects [get_ports drp_clk]] - -set_property ASYNC_REG TRUE \ - [get_cells -hier *up_drp_locked_m1_reg*] \ - [get_cells -hier *up_drp_ack_t_m1_reg*] \ - [get_cells -hier *up_drp_ack_t_m2_reg*] \ - [get_cells -hier *drp_sel_t_m1_reg*] \ - [get_cells -hier *drp_sel_t_m2_reg*] \ - [get_cells -hier *drp_locked_m1_reg*] \ - [get_cells -hier *drp_locked_reg*] - -set_false_path \ - -from [get_cells -hier up_drp_sel_t_reg* -filter {primitive_subgroup == flop}] \ - -to [get_cells -hier drp_sel_t_m1_reg* -filter {primitive_subgroup == flop}] -set_max_delay -datapath_only \ - -from [get_cells -hier up_drp_rwn_reg* -filter {primitive_subgroup == flop}] \ - -to [get_cells -hier drp_wr_reg* -filter {primitive_subgroup == flop}] \ - [get_property PERIOD $delay_clk] -set_max_delay -datapath_only \ - -from [get_cells -hier up_drp_addr_reg* -filter {primitive_subgroup == flop}] \ - -to [get_cells -hier drp_addr_reg* -filter {primitive_subgroup == flop}] \ - [get_property PERIOD $delay_clk] -set_max_delay -datapath_only \ - -from [get_cells -hier up_drp_wdata_reg* -filter {primitive_subgroup == flop}] \ - -to [get_cells -hier drp_wdata_reg* -filter {primitive_subgroup == flop}] \ - [get_property PERIOD $delay_clk] -set_false_path \ - -from [get_cells -hier drp_locked_reg* -filter {primitive_subgroup == flop}] \ - -to [get_cells -hier up_drp_locked_m1_reg* -filter {primitive_subgroup == flop}] -set_false_path \ - -from [get_cells -hier drp_ack_t_reg* -filter {primitive_subgroup == flop}] \ - -to [get_cells -hier up_drp_ack_t_m1_reg* -filter {primitive_subgroup == flop}] -set_max_delay -datapath_only \ - -from [get_cells -hier drp_rdata_int_reg* -filter {primitive_subgroup == flop}] \ - -to [get_cells -hier up_drp_rdata_reg* -filter {primitive_subgroup == flop}] \ - [get_property PERIOD $up_clk] - -set_max_delay -datapath_only \ - -from [get_cells -hier drp_rdata_reg* -filter {primitive_subgroup == flop}] \ - -to [get_cells -hier drp_rdata_int_reg* -filter {primitive_subgroup == flop}] \ - [get_property PERIOD $delay_clk] - -set_false_path \ - -to [get_pins -hier */PRE -filter {NAME =~ *i_*rst_reg*}] diff --git a/library/axi_clkgen/axi_clkgen_ip.tcl b/library/axi_clkgen/axi_clkgen_ip.tcl index 36811ff7a..1436c1b27 100644 --- a/library/axi_clkgen/axi_clkgen_ip.tcl +++ b/library/axi_clkgen/axi_clkgen_ip.tcl @@ -8,7 +8,6 @@ adi_ip_files axi_clkgen [list \ "$ad_hdl_dir/library/common/ad_rst.v" \ "$ad_hdl_dir/library/common/ad_mmcm_drp.v" \ "$ad_hdl_dir/library/common/up_axi.v" \ - "$ad_hdl_dir/library/common/up_drp_cntrl.v" \ "$ad_hdl_dir/library/common/up_clkgen.v" \ "axi_clkgen_constr.xdc" \ "axi_clkgen.v" ] diff --git a/library/axi_jesd_gt/axi_jesd_gt.v b/library/axi_jesd_gt/axi_jesd_gt.v index fe83a69a1..1f86bdbcf 100644 --- a/library/axi_jesd_gt/axi_jesd_gt.v +++ b/library/axi_jesd_gt/axi_jesd_gt.v @@ -86,10 +86,13 @@ module axi_jesd_gt ( tx_ip_sof, tx_ip_data, - // axi interface + // axi - clock & reset + + axi_aclk, + axi_aresetn, + + // axi-lite (slave) - s_axi_aclk, - s_axi_aresetn, s_axi_awvalid, s_axi_awaddr, s_axi_awready, @@ -108,10 +111,8 @@ module axi_jesd_gt ( s_axi_rresp, s_axi_rready, - // master interface + // axi (master) - m_axi_aclk, - m_axi_aresetn, m_axi_awvalid, m_axi_awaddr, m_axi_awprot, @@ -130,24 +131,7 @@ module axi_jesd_gt ( m_axi_rvalid, m_axi_rdata, m_axi_rresp, - m_axi_rready, - - // drp clock - - drp_clk, - - // es debug interface - - es_dbg_data, - es_dbg_trigger, - - // jesd debug interface - - rx_mon_data, - rx_mon_trigger, - - tx_mon_data, - tx_mon_trigger); + m_axi_rready); parameter PCORE_ID = 0; parameter PCORE_DEVICE_TYPE = 0; @@ -224,10 +208,11 @@ module axi_jesd_gt ( input [ 3:0] tx_ip_sof; output [((PCORE_NUM_OF_TX_LANES*32)-1):0] tx_ip_data; + input axi_aclk; + input axi_aresetn; + // axi interface - input s_axi_aclk; - input s_axi_aresetn; input s_axi_awvalid; input [ 31:0] s_axi_awaddr; output s_axi_awready; @@ -248,8 +233,6 @@ module axi_jesd_gt ( // master interface - input m_axi_aclk; - input m_axi_aresetn; output m_axi_awvalid; output [ 31:0] m_axi_awaddr; output [ 2:0] m_axi_awprot; @@ -270,23 +253,6 @@ module axi_jesd_gt ( input [ 1:0] m_axi_rresp; output m_axi_rready; - // drp clock - - input drp_clk; - - // es debug interface - - output [275:0] es_dbg_data; - output [ 7:0] es_dbg_trigger; - - // jesd debug interface - - output [((PCORE_NUM_OF_RX_LANES*82)+5):0] rx_mon_data; - output [((PCORE_NUM_OF_RX_LANES* 1)+1):0] rx_mon_trigger; - - output [((PCORE_NUM_OF_TX_LANES*36)+5):0] tx_mon_data; - output [ 5:0] tx_mon_trigger; - // reset and clocks wire gt_pll_rst; @@ -300,11 +266,9 @@ module axi_jesd_gt ( wire [ 7:0] qpll_ref_clk; wire [((PCORE_NUM_OF_LANES* 1)-1):0] rx_out_clk; wire [((PCORE_NUM_OF_LANES* 1)-1):0] tx_out_clk; - wire axi_rstn; - wire axi_clk; wire up_rstn; wire up_clk; - wire drp_rst; + wire up_drp_rst; // internal signals @@ -315,9 +279,9 @@ module axi_jesd_gt ( wire [ 8:0] tx_pll_locked_extn_s; wire [((PCORE_NUM_OF_LANES* 1)-1):0] rx_mon_trigger_s; wire [((PCORE_NUM_OF_LANES*50)-1):0] rx_mon_data_s; - wire [ 15:0] drp_rdata_gt_s[15:0]; - wire drp_ready_gt_s[15:0]; - wire [ 7:0] drp_rx_rate_gt_s[15:0]; + wire [ 15:0] up_drp_rdata_gt_s[15:0]; + wire up_drp_ready_gt_s[15:0]; + wire [ 7:0] up_drp_rxrate_gt_s[15:0]; wire [((PCORE_NUM_OF_LANES* 1)-1):0] rx_data_p_s; wire [((PCORE_NUM_OF_LANES* 1)-1):0] rx_data_n_s; wire [((PCORE_NUM_OF_LANES*32)-1):0] rx_data_s; @@ -326,6 +290,11 @@ module axi_jesd_gt ( wire [((PCORE_NUM_OF_LANES* 4)-1):0] rx_gt_disperr_s; wire [((PCORE_NUM_OF_LANES* 4)-1):0] rx_gt_notintable_s; wire [((PCORE_NUM_OF_LANES*32)-1):0] rx_gt_data_s; + wire [((PCORE_NUM_OF_LANES* 4)-1):0] rx_ilas_f_s; + wire [((PCORE_NUM_OF_LANES* 4)-1):0] rx_ilas_q_s; + wire [((PCORE_NUM_OF_LANES* 4)-1):0] rx_ilas_a_s; + wire [((PCORE_NUM_OF_LANES* 4)-1):0] rx_ilas_r_s; + wire [((PCORE_NUM_OF_LANES* 4)-1):0] rx_cgs_k_s; wire [((PCORE_NUM_OF_LANES*32)-1):0] rx_ip_data_s; wire [((PCORE_NUM_OF_LANES* 1)-1):0] tx_data_p_s; wire [((PCORE_NUM_OF_LANES* 1)-1):0] tx_data_n_s; @@ -350,45 +319,45 @@ module axi_jesd_gt ( wire [ 2:0] up_rx_out_clk_sel_s; wire [ 1:0] up_tx_sys_clk_sel_s; wire [ 2:0] up_tx_out_clk_sel_s; - wire drp_sel_s; - wire drp_wr_s; - wire [ 11:0] drp_addr_s; - wire [ 15:0] drp_wdata_s; - wire [ 15:0] drp_rdata_s; - wire drp_ready_s; - wire [ 7:0] drp_lanesel_s; - wire [ 7:0] drp_rx_rate_s; - wire es_sel_s; - wire es_wr_s; - wire [ 11:0] es_addr_s; - wire [ 15:0] es_wdata_s; - wire [ 15:0] es_rdata_s; - wire es_ready_s; - wire es_start_s; - wire es_stop_s; - wire es_init_s; - wire es_lpm_dfe_n_s; - wire [ 15:0] es_sdata0_s; - wire [ 15:0] es_sdata1_s; - wire [ 15:0] es_sdata2_s; - wire [ 15:0] es_sdata3_s; - wire [ 15:0] es_sdata4_s; - wire [ 15:0] es_qdata0_s; - wire [ 15:0] es_qdata1_s; - wire [ 15:0] es_qdata2_s; - wire [ 15:0] es_qdata3_s; - wire [ 15:0] es_qdata4_s; - wire [ 4:0] es_prescale_s; - wire [ 11:0] es_hoffset_min_s; - wire [ 11:0] es_hoffset_max_s; - wire [ 11:0] es_hoffset_step_s; - wire [ 7:0] es_voffset_min_s; - wire [ 7:0] es_voffset_max_s; - wire [ 7:0] es_voffset_step_s; - wire [ 1:0] es_voffset_range_s; - wire [ 31:0] es_start_addr_s; - wire es_dmaerr_s; - wire es_status_s; + wire up_drp_sel_s; + wire up_drp_wr_s; + wire [ 11:0] up_drp_addr_s; + wire [ 15:0] up_drp_wdata_s; + wire [ 15:0] up_drp_rdata_s; + wire up_drp_ready_s; + wire [ 7:0] up_drp_lanesel_s; + wire [ 7:0] up_drp_rxrate_s; + wire up_es_drp_sel_s; + wire up_es_drp_wr_s; + wire [ 11:0] up_es_drp_addr_s; + wire [ 15:0] up_es_drp_wdata_s; + wire [ 15:0] up_es_drp_rdata_s; + wire up_es_drp_ready_s; + wire up_es_start_s; + wire up_es_stop_s; + wire up_es_init_s; + wire up_es_lpm_dfe_n_s; + wire [ 15:0] up_es_sdata0_s; + wire [ 15:0] up_es_sdata1_s; + wire [ 15:0] up_es_sdata2_s; + wire [ 15:0] up_es_sdata3_s; + wire [ 15:0] up_es_sdata4_s; + wire [ 15:0] up_es_qdata0_s; + wire [ 15:0] up_es_qdata1_s; + wire [ 15:0] up_es_qdata2_s; + wire [ 15:0] up_es_qdata3_s; + wire [ 15:0] up_es_qdata4_s; + wire [ 4:0] up_es_prescale_s; + wire [ 11:0] up_es_hoffset_min_s; + wire [ 11:0] up_es_hoffset_max_s; + wire [ 11:0] up_es_hoffset_step_s; + wire [ 7:0] up_es_voffset_min_s; + wire [ 7:0] up_es_voffset_max_s; + wire [ 7:0] up_es_voffset_step_s; + wire [ 1:0] up_es_voffset_range_s; + wire [ 31:0] up_es_start_addr_s; + wire up_es_dmaerr_s; + wire up_es_status_s; wire up_wreq_s; wire [ 13:0] up_waddr_s; wire [ 31:0] up_wdata_s; @@ -408,10 +377,8 @@ module axi_jesd_gt ( // signal name changes - assign axi_rstn = m_axi_aresetn; - assign axi_clk = m_axi_aclk; - assign up_rstn = s_axi_aresetn; - assign up_clk = s_axi_aclk; + assign up_rstn = axi_aresetn; + assign up_clk = axi_aclk; // drp is simply over-defined to avoid errors with singluar entries @@ -421,32 +388,32 @@ module axi_jesd_gt ( assign tx_rst_done_extn_s = {up_status_extn_s[8:PCORE_NUM_OF_LANES], tx_rst_done_s}; assign tx_pll_locked_extn_s = {up_status_extn_s[8:PCORE_NUM_OF_LANES], tx_pll_locked_s}; - assign drp_rdata_s = drp_rdata_gt_s[15] | drp_rdata_gt_s[14] | - drp_rdata_gt_s[13] | drp_rdata_gt_s[12] | - drp_rdata_gt_s[11] | drp_rdata_gt_s[10] | - drp_rdata_gt_s[ 9] | drp_rdata_gt_s[ 8] | - drp_rdata_gt_s[ 7] | drp_rdata_gt_s[ 6] | - drp_rdata_gt_s[ 5] | drp_rdata_gt_s[ 4] | - drp_rdata_gt_s[ 3] | drp_rdata_gt_s[ 2] | - drp_rdata_gt_s[ 1] | drp_rdata_gt_s[ 0]; + assign up_drp_rdata_s = up_drp_rdata_gt_s[15] | up_drp_rdata_gt_s[14] | + up_drp_rdata_gt_s[13] | up_drp_rdata_gt_s[12] | + up_drp_rdata_gt_s[11] | up_drp_rdata_gt_s[10] | + up_drp_rdata_gt_s[ 9] | up_drp_rdata_gt_s[ 8] | + up_drp_rdata_gt_s[ 7] | up_drp_rdata_gt_s[ 6] | + up_drp_rdata_gt_s[ 5] | up_drp_rdata_gt_s[ 4] | + up_drp_rdata_gt_s[ 3] | up_drp_rdata_gt_s[ 2] | + up_drp_rdata_gt_s[ 1] | up_drp_rdata_gt_s[ 0]; - assign drp_ready_s = drp_ready_gt_s[15] | drp_ready_gt_s[14] | - drp_ready_gt_s[13] | drp_ready_gt_s[12] | - drp_ready_gt_s[11] | drp_ready_gt_s[10] | - drp_ready_gt_s[ 9] | drp_ready_gt_s[ 8] | - drp_ready_gt_s[ 7] | drp_ready_gt_s[ 6] | - drp_ready_gt_s[ 5] | drp_ready_gt_s[ 4] | - drp_ready_gt_s[ 3] | drp_ready_gt_s[ 2] | - drp_ready_gt_s[ 1] | drp_ready_gt_s[ 0]; + assign up_drp_ready_s = up_drp_ready_gt_s[15] | up_drp_ready_gt_s[14] | + up_drp_ready_gt_s[13] | up_drp_ready_gt_s[12] | + up_drp_ready_gt_s[11] | up_drp_ready_gt_s[10] | + up_drp_ready_gt_s[ 9] | up_drp_ready_gt_s[ 8] | + up_drp_ready_gt_s[ 7] | up_drp_ready_gt_s[ 6] | + up_drp_ready_gt_s[ 5] | up_drp_ready_gt_s[ 4] | + up_drp_ready_gt_s[ 3] | up_drp_ready_gt_s[ 2] | + up_drp_ready_gt_s[ 1] | up_drp_ready_gt_s[ 0]; - assign drp_rx_rate_s = drp_rx_rate_gt_s[15] | drp_rx_rate_gt_s[14] | - drp_rx_rate_gt_s[13] | drp_rx_rate_gt_s[12] | - drp_rx_rate_gt_s[11] | drp_rx_rate_gt_s[10] | - drp_rx_rate_gt_s[ 9] | drp_rx_rate_gt_s[ 8] | - drp_rx_rate_gt_s[ 7] | drp_rx_rate_gt_s[ 6] | - drp_rx_rate_gt_s[ 5] | drp_rx_rate_gt_s[ 4] | - drp_rx_rate_gt_s[ 3] | drp_rx_rate_gt_s[ 2] | - drp_rx_rate_gt_s[ 1] | drp_rx_rate_gt_s[ 0]; + assign up_drp_rxrate_s = up_drp_rxrate_gt_s[15] | up_drp_rxrate_gt_s[14] | + up_drp_rxrate_gt_s[13] | up_drp_rxrate_gt_s[12] | + up_drp_rxrate_gt_s[11] | up_drp_rxrate_gt_s[10] | + up_drp_rxrate_gt_s[ 9] | up_drp_rxrate_gt_s[ 8] | + up_drp_rxrate_gt_s[ 7] | up_drp_rxrate_gt_s[ 6] | + up_drp_rxrate_gt_s[ 5] | up_drp_rxrate_gt_s[ 4] | + up_drp_rxrate_gt_s[ 3] | up_drp_rxrate_gt_s[ 2] | + up_drp_rxrate_gt_s[ 1] | up_drp_rxrate_gt_s[ 0]; // asymmetric widths -- receive @@ -565,15 +532,15 @@ module axi_jesd_gt ( .qpll_clk (qpll_clk_0), .qpll_ref_clk (qpll_ref_clk_0), .qpll_locked (qpll_locked_0_s), - .drp_clk (drp_clk), - .drp_sel (drp_sel_s), - .drp_addr (drp_addr_s), - .drp_wr (drp_wr_s), - .drp_wdata (drp_wdata_s), - .drp_rdata (drp_rdata_gt_s[14]), - .drp_ready (drp_ready_gt_s[14]), - .drp_lanesel (drp_lanesel_s), - .drp_rx_rate (drp_rx_rate_gt_s[14])); + .up_clk (up_clk), + .up_drp_sel (up_drp_sel_s), + .up_drp_addr (up_drp_addr_s), + .up_drp_wr (up_drp_wr_s), + .up_drp_wdata (up_drp_wdata_s), + .up_drp_rdata (up_drp_rdata_gt_s[14]), + .up_drp_ready (up_drp_ready_gt_s[14]), + .up_drp_lanesel (up_drp_lanesel_s), + .up_drp_rxrate (up_drp_rxrate_gt_s[14])); ad_gt_common_1 #( .DRP_ID (15), @@ -588,23 +555,23 @@ module axi_jesd_gt ( .qpll_clk (qpll_clk_1), .qpll_ref_clk (qpll_ref_clk_1), .qpll_locked (qpll_locked_1_s), - .drp_clk (drp_clk), - .drp_sel (drp_sel_s), - .drp_addr (drp_addr_s), - .drp_wr (drp_wr_s), - .drp_wdata (drp_wdata_s), - .drp_rdata (drp_rdata_gt_s[15]), - .drp_ready (drp_ready_gt_s[15]), - .drp_lanesel (drp_lanesel_s), - .drp_rx_rate (drp_rx_rate_gt_s[15])); + .up_clk (up_clk), + .up_drp_sel (up_drp_sel_s), + .up_drp_addr (up_drp_addr_s), + .up_drp_wr (up_drp_wr_s), + .up_drp_wdata (up_drp_wdata_s), + .up_drp_rdata (up_drp_rdata_gt_s[15]), + .up_drp_ready (up_drp_ready_gt_s[15]), + .up_drp_lanesel (up_drp_lanesel_s), + .up_drp_rxrate (up_drp_rxrate_gt_s[15])); genvar n; generate for (n = PCORE_NUM_OF_LANES; n < 14; n = n + 1) begin: g_unused_1 - assign drp_rdata_gt_s[n] = 'd0; - assign drp_ready_gt_s[n] = 'd0; - assign drp_rx_rate_gt_s[n] = 'd0; + assign up_drp_rdata_gt_s[n] = 'd0; + assign up_drp_ready_gt_s[n] = 'd0; + assign up_drp_rxrate_gt_s[n] = 'd0; end for (n = 0; n < PCORE_NUM_OF_LANES; n = n + 1) begin: g_lane_1 @@ -648,6 +615,11 @@ module axi_jesd_gt ( .rx_notintable (rx_gt_notintable_s[n*4+3:n*4]), .rx_data (rx_gt_data_s[n*32+31:n*32]), .rx_comma_align_enb (rx_ip_comma_align), + .rx_ilas_f (rx_ilas_f_s[n*4+3:n*4]), + .rx_ilas_q (rx_ilas_q_s[n*4+3:n*4]), + .rx_ilas_a (rx_ilas_a_s[n*4+3:n*4]), + .rx_ilas_r (rx_ilas_r_s[n*4+3:n*4]), + .rx_cgs_k (rx_cgs_k_s[n*4+3:n*4]), .tx_rst (gt_tx_rst), .tx_p (tx_data_p_s[n]), .tx_n (tx_data_n_s[n]), @@ -659,33 +631,29 @@ module axi_jesd_gt ( .tx_clk (tx_clk), .tx_charisk (tx_gt_charisk_mux_s[n*4+3:n*4]), .tx_data (tx_gt_data_mux_s[n*32+31:n*32]), - .drp_clk (drp_clk), - .drp_sel (drp_sel_s), - .drp_addr (drp_addr_s), - .drp_wr (drp_wr_s), - .drp_wdata (drp_wdata_s), - .drp_rdata (drp_rdata_gt_s[n]), - .drp_ready (drp_ready_gt_s[n]), - .drp_lanesel (drp_lanesel_s), - .drp_rx_rate (drp_rx_rate_gt_s[n]), - .rx_mon_trigger (rx_mon_trigger_s[n]), - .rx_mon_data (rx_mon_data_s[n*50+49:n*50])); + .up_clk (up_clk), + .up_drp_sel (up_drp_sel_s), + .up_drp_addr (up_drp_addr_s), + .up_drp_wr (up_drp_wr_s), + .up_drp_wdata (up_drp_wdata_s), + .up_drp_rdata (up_drp_rdata_gt_s[n]), + .up_drp_ready (up_drp_ready_gt_s[n]), + .up_drp_lanesel (up_drp_lanesel_s), + .up_drp_rxrate (up_drp_rxrate_gt_s[n])); end endgenerate // eye scan ad_gt_es #(.GTH_GTX_N(PCORE_DEVICE_TYPE)) i_gt_es ( - .drp_rst (drp_rst), - .drp_clk (drp_clk), - .es_sel (es_sel_s), - .es_wr (es_wr_s), - .es_addr (es_addr_s), - .es_wdata (es_wdata_s), - .es_rdata (es_rdata_s), - .es_ready (es_ready_s), - .axi_rstn (axi_rstn), - .axi_clk (axi_clk), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_es_drp_sel (up_es_drp_sel_s), + .up_es_drp_wr (up_es_drp_wr_s), + .up_es_drp_addr (up_es_drp_addr_s), + .up_es_drp_wdata (up_es_drp_wdata_s), + .up_es_drp_rdata (up_es_drp_rdata_s), + .up_es_drp_ready (up_es_drp_ready_s), .axi_awvalid (m_axi_awvalid), .axi_awaddr (m_axi_awaddr), .axi_awprot (m_axi_awprot), @@ -705,33 +673,31 @@ module axi_jesd_gt ( .axi_rdata (m_axi_rdata), .axi_rresp (m_axi_rresp), .axi_rready (m_axi_rready), - .es_start (es_start_s), - .es_stop (es_stop_s), - .es_init (es_init_s), - .es_lpm_dfe_n (es_lpm_dfe_n_s), - .es_sdata0 (es_sdata0_s), - .es_sdata1 (es_sdata1_s), - .es_sdata2 (es_sdata2_s), - .es_sdata3 (es_sdata3_s), - .es_sdata4 (es_sdata4_s), - .es_qdata0 (es_qdata0_s), - .es_qdata1 (es_qdata1_s), - .es_qdata2 (es_qdata2_s), - .es_qdata3 (es_qdata3_s), - .es_qdata4 (es_qdata4_s), - .es_prescale (es_prescale_s), - .es_hoffset_min (es_hoffset_min_s), - .es_hoffset_max (es_hoffset_max_s), - .es_hoffset_step (es_hoffset_step_s), - .es_voffset_min (es_voffset_min_s), - .es_voffset_max (es_voffset_max_s), - .es_voffset_step (es_voffset_step_s), - .es_voffset_range (es_voffset_range_s), - .es_start_addr (es_start_addr_s), - .es_dmaerr (es_dmaerr_s), - .es_status (es_status_s), - .es_dbg_trigger (es_dbg_trigger), - .es_dbg_data (es_dbg_data)); + .up_lpm_dfe_n (up_lpm_dfe_n_s), + .up_es_start (up_es_start_s), + .up_es_stop (up_es_stop_s), + .up_es_init (up_es_init_s), + .up_es_sdata0 (up_es_sdata0_s), + .up_es_sdata1 (up_es_sdata1_s), + .up_es_sdata2 (up_es_sdata2_s), + .up_es_sdata3 (up_es_sdata3_s), + .up_es_sdata4 (up_es_sdata4_s), + .up_es_qdata0 (up_es_qdata0_s), + .up_es_qdata1 (up_es_qdata1_s), + .up_es_qdata2 (up_es_qdata2_s), + .up_es_qdata3 (up_es_qdata3_s), + .up_es_qdata4 (up_es_qdata4_s), + .up_es_prescale (up_es_prescale_s), + .up_es_hoffset_min (up_es_hoffset_min_s), + .up_es_hoffset_max (up_es_hoffset_max_s), + .up_es_hoffset_step (up_es_hoffset_step_s), + .up_es_voffset_min (up_es_voffset_min_s), + .up_es_voffset_max (up_es_voffset_max_s), + .up_es_voffset_step (up_es_voffset_step_s), + .up_es_voffset_range (up_es_voffset_range_s), + .up_es_start_addr (up_es_start_addr_s), + .up_es_dmaerr (up_es_dmaerr_s), + .up_es_status (up_es_status_s)); // processor @@ -767,47 +733,44 @@ module axi_jesd_gt ( .tx_pll_locked (tx_pll_locked_extn_s[7:0]), .tx_error (1'd0), .tx_rst_done_up (tx_rst_done), - .drp_clk (drp_clk), - .drp_rst (drp_rst), - .drp_sel (drp_sel_s), - .drp_wr (drp_wr_s), - .drp_addr (drp_addr_s), - .drp_wdata (drp_wdata_s), - .drp_rdata (drp_rdata_s), - .drp_ready (drp_ready_s), - .drp_lanesel (drp_lanesel_s), - .drp_rx_rate (drp_rx_rate_s), - .es_sel (es_sel_s), - .es_wr (es_wr_s), - .es_addr (es_addr_s), - .es_wdata (es_wdata_s), - .es_rdata (es_rdata_s), - .es_ready (es_ready_s), - .es_start (es_start_s), - .es_stop (es_stop_s), - .es_init (es_init_s), - .es_lpm_dfe_n (es_lpm_dfe_n_s), - .es_prescale (es_prescale_s), - .es_voffset_range (es_voffset_range_s), - .es_voffset_step (es_voffset_step_s), - .es_voffset_max (es_voffset_max_s), - .es_voffset_min (es_voffset_min_s), - .es_hoffset_max (es_hoffset_max_s), - .es_hoffset_min (es_hoffset_min_s), - .es_hoffset_step (es_hoffset_step_s), - .es_start_addr (es_start_addr_s), - .es_sdata0 (es_sdata0_s), - .es_sdata1 (es_sdata1_s), - .es_sdata2 (es_sdata2_s), - .es_sdata3 (es_sdata3_s), - .es_sdata4 (es_sdata4_s), - .es_qdata0 (es_qdata0_s), - .es_qdata1 (es_qdata1_s), - .es_qdata2 (es_qdata2_s), - .es_qdata3 (es_qdata3_s), - .es_qdata4 (es_qdata4_s), - .es_dmaerr (es_dmaerr_s), - .es_status (es_status_s), + .up_drp_sel (up_drp_sel_s), + .up_drp_wr (up_drp_wr_s), + .up_drp_addr (up_drp_addr_s), + .up_drp_wdata (up_drp_wdata_s), + .up_drp_rdata (up_drp_rdata_s), + .up_drp_ready (up_drp_ready_s), + .up_drp_lanesel (up_drp_lanesel_s), + .up_drp_rxrate (up_drp_rxrate_s), + .up_es_drp_sel (up_es_drp_sel_s), + .up_es_drp_wr (up_es_drp_wr_s), + .up_es_drp_addr (up_es_drp_addr_s), + .up_es_drp_wdata (up_es_drp_wdata_s), + .up_es_drp_rdata (up_es_drp_rdata_s), + .up_es_drp_ready (up_es_drp_ready_s), + .up_es_start (up_es_start_s), + .up_es_stop (up_es_stop_s), + .up_es_init (up_es_init_s), + .up_es_prescale (up_es_prescale_s), + .up_es_voffset_range (up_es_voffset_range_s), + .up_es_voffset_step (up_es_voffset_step_s), + .up_es_voffset_max (up_es_voffset_max_s), + .up_es_voffset_min (up_es_voffset_min_s), + .up_es_hoffset_max (up_es_hoffset_max_s), + .up_es_hoffset_min (up_es_hoffset_min_s), + .up_es_hoffset_step (up_es_hoffset_step_s), + .up_es_start_addr (up_es_start_addr_s), + .up_es_sdata0 (up_es_sdata0_s), + .up_es_sdata1 (up_es_sdata1_s), + .up_es_sdata2 (up_es_sdata2_s), + .up_es_sdata3 (up_es_sdata3_s), + .up_es_sdata4 (up_es_sdata4_s), + .up_es_qdata0 (up_es_qdata0_s), + .up_es_qdata1 (up_es_qdata1_s), + .up_es_qdata2 (up_es_qdata2_s), + .up_es_qdata3 (up_es_qdata3_s), + .up_es_qdata4 (up_es_qdata4_s), + .up_es_dmaerr (up_es_dmaerr_s), + .up_es_status (up_es_status_s), .up_rstn (up_rstn), .up_clk (up_clk), .up_wreq (up_wreq_s), diff --git a/library/axi_jesd_gt/axi_jesd_gt_constr.xdc b/library/axi_jesd_gt/axi_jesd_gt_constr.xdc index 1aa7b56bc..e69de29bb 100644 --- a/library/axi_jesd_gt/axi_jesd_gt_constr.xdc +++ b/library/axi_jesd_gt/axi_jesd_gt_constr.xdc @@ -1,89 +0,0 @@ -set up_clk [get_clocks -of_objects [get_ports s_axi_aclk]] -set master_clk [get_clocks -of_objects [get_ports m_axi_aclk]] -set delay_clk [get_clocks -of_objects [get_ports drp_clk]] - -set_property ASYNC_REG TRUE \ - [get_cells -hier *toggle_m1_reg*] \ - [get_cells -hier *toggle_m2_reg*] \ - [get_cells -hier *state_m1_reg*] \ - [get_cells -hier *state_m2_reg*] \ - [get_cells -hier *axi_req_toggle_m1_reg*] \ - [get_cells -hier *axi_req_toggle_m2_reg*] \ - [get_cells -hier *es_dma_ack_toggle_m1_reg*] \ - [get_cells -hier *es_dma_ack_toggle_m2_reg*] \ - [get_cells -hier *rx_sysref_m1_reg*] \ - [get_cells -hier *rx_sysref_m2_reg*] \ - [get_cells -hier *tx_sysref_m1_reg*] \ - [get_cells -hier *tx_sysref_m2_reg*] \ - [get_cells -hier *rx_sync_m1_reg*] \ - [get_cells -hier *rx_sync_m2_reg*] \ - [get_cells -hier *tx_ip_sync_m1_reg*] \ - [get_cells -hier *tx_ip_sync_m2_reg*] \ - [get_cells -hier *up_rx_status_m1_reg*] \ - [get_cells -hier *up_tx_status_m1_reg*] \ - [get_cells -hier *up_rx_rst_done_m1_reg*] \ - [get_cells -hier *up_tx_rst_done_m1_reg*] - -set_false_path \ - -from [get_cells -hier es_dma_req_toggle_reg* -filter {primitive_subgroup == flop}] \ - -to [get_cells -hier axi_req_toggle_m1_reg* -filter {primitive_subgroup == flop}] -set_false_path \ - -from [get_cells -hier axi_ack_toggle_reg* -filter {primitive_subgroup == flop}] \ - -to [get_cells -hier es_dma_ack_toggle_m1_reg* -filter {primitive_subgroup == flop}] -set_max_delay -datapath_only \ - -from [get_cells -hier es_dma_data_reg* -filter {primitive_subgroup == flop}] \ - -to [get_cells -hier axi_wdata_reg* -filter {primitive_subgroup == flop}] \ - [get_property PERIOD $master_clk] -set_max_delay -datapath_only \ - -from [get_cells -hier es_dma_addr_reg* -filter {primitive_subgroup == flop}] \ - -to [get_cells -hier axi_awaddr_reg* -filter {primitive_subgroup == flop}] \ - [get_property PERIOD $master_clk] - -set_false_path \ - -from [get_cells -hier up_rx_sysref_sel_reg* -filter {primitive_subgroup == flop}] \ - -to [get_cells -hier rx_sysref_m1_reg* -filter {primitive_subgroup == flop}] -set_false_path \ - -from [get_cells -hier up_rx_sysref_reg* -filter {primitive_subgroup == flop}] \ - -to [get_cells -hier rx_sysref_m1_reg* -filter {primitive_subgroup == flop}] -#set_false_path \ -# -from [get_cells -hier tx_sysref_reg* -filter {primitive_subgroup == flop}] \ -# -to [get_cells -hier tx_sysref_m1_reg* -filter {primitive_subgroup == flop}] -set_false_path \ - -from [get_cells -hier up_rx_sync_reg* -filter {primitive_subgroup == flop}] \ - -to [get_cells -hier rx_sync_m1_reg* -filter {primitive_subgroup == flop}] -set_false_path \ - -from [get_cells -hier rx_sync_reg* -filter {primitive_subgroup == flop}] \ - -to [get_cells -hier up_rx_status_m1_reg* -filter {primitive_subgroup == flop}] - -set_false_path \ - -from [get_cells -hier up_xfer_toggle_reg* -filter {primitive_subgroup == flop}] \ - -to [get_cells -hier d_xfer_toggle_m1_reg* -filter {primitive_subgroup == flop}] -set_false_path \ - -from [get_cells -hier d_xfer_toggle_reg* -filter {primitive_subgroup == flop}] \ - -to [get_cells -hier up_xfer_state_m1_reg* -filter {primitive_subgroup == flop}] -set_max_delay -datapath_only \ - -from [get_cells -hier up_xfer_data_reg* -filter {primitive_subgroup == flop}] \ - -to [get_cells -hier d_data_cntrl_reg* -filter {primitive_subgroup == flop}] \ - [get_property PERIOD $delay_clk] - -set_false_path \ - -from [get_cells -hier d_xfer_toggle_reg* -filter {primitive_subgroup == flop}] \ - -to [get_cells -hier up_xfer_toggle_m1_reg* -filter {primitive_subgroup == flop}] -set_false_path \ - -from [get_cells -hier up_xfer_toggle_reg* -filter {primitive_subgroup == flop}] \ - -to [get_cells -hier d_xfer_state_m1_reg* -filter {primitive_subgroup == flop}] -set_max_delay -datapath_only \ - -from [get_cells -hier d_xfer_data_reg* -filter {primitive_subgroup == flop}] \ - -to [get_cells -hier up_data_status_reg* -filter {primitive_subgroup == flop}] \ - [get_property PERIOD $up_clk] - -set_false_path \ - -from [get_pins -hier *RXUSRCLK2* ] \ - -to [get_pins -hier up_rx_rst_done_m1_reg*/D ] - -set_false_path \ - -from [get_pins -hier *TXUSRCLK2* ] \ - -to [get_pins -hier up_tx_rst_done_m1_reg*/D ] - -set_false_path \ - -to [get_pins -hier */PRE -filter {NAME =~ *i_*rst_reg*}] diff --git a/library/axi_jesd_gt/axi_jesd_gt_ip.tcl b/library/axi_jesd_gt/axi_jesd_gt_ip.tcl index d56175fea..0ece35965 100644 --- a/library/axi_jesd_gt/axi_jesd_gt_ip.tcl +++ b/library/axi_jesd_gt/axi_jesd_gt_ip.tcl @@ -11,9 +11,6 @@ adi_ip_files axi_jesd_gt [list \ "$ad_hdl_dir/library/common/ad_jesd_align.v" \ "$ad_hdl_dir/library/common/ad_rst.v" \ "$ad_hdl_dir/library/common/up_axi.v" \ - "$ad_hdl_dir/library/common/up_xfer_cntrl.v" \ - "$ad_hdl_dir/library/common/up_xfer_status.v" \ - "$ad_hdl_dir/library/common/up_drp_cntrl.v" \ "$ad_hdl_dir/library/common/up_gt.v" \ "axi_jesd_gt.v" \ "axi_jesd_gt_constr.xdc" ] @@ -23,5 +20,13 @@ adi_ip_properties axi_jesd_gt adi_ip_constraints axi_jesd_gt [list \ "axi_jesd_gt_constr.xdc" ] +set_property value m_axi:s_axi [ipx::get_bus_parameters ASSOCIATED_BUSIF \ + -of_objects [ipx::get_bus_interfaces axi_signal_clock \ + -of_objects [ipx::current_core]]] + +set_property value axi_aresetn [ipx::get_bus_parameters ASSOCIATED_RESET \ + -of_objects [ipx::get_bus_interfaces axi_signal_clock \ + -of_objects [ipx::current_core]]] + ipx::save_core [ipx::current_core]