axi_adrv9001: Add status bit for Tx clocking
If Tx source synchronous clock is not routed through clock capable pins the interface and driving logic must run on the Rx interface clock. This introduces a dependency, Rx interface must be bring up before the Tx. In this mode a Tx only operation is not possible. This is done through a synthesis parameter. Expose this parameter to the software so it can query if the limitations exists in the implementation.main
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c9ca1ac00a
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c718ba91f1
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@ -377,6 +377,7 @@ module axi_adrv9001 #(
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.ID (ID),
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.NUM_LANES (NUM_LANES),
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.CMOS_LVDS_N (CMOS_LVDS_N),
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.USE_RX_CLK_FOR_TX (USE_RX_CLK_FOR_TX),
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.DRP_WIDTH (DRP_WIDTH),
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.TDD_DISABLE (TDD_DISABLE),
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.DDS_DISABLE (DDS_DISABLE),
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@ -38,6 +38,7 @@
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module axi_ad9001_core #(
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parameter ID = 0,
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parameter CMOS_LVDS_N = 0,
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parameter USE_RX_CLK_FOR_TX = 0,
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parameter NUM_LANES = 3,
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parameter DRP_WIDTH = 5,
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parameter TDD_DISABLE = 0,
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@ -399,6 +400,7 @@ module axi_ad9001_core #(
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.ID (ID),
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.ENABLED (1),
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.CMOS_LVDS_N (CMOS_LVDS_N),
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.USE_RX_CLK_FOR_TX (USE_RX_CLK_FOR_TX),
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.COMMON_BASE_ADDR ('h08),
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.CHANNEL_BASE_ADDR ('h09),
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.MODE_R1 (COMMON_2R2T_SUPPORT==0),
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@ -451,6 +453,7 @@ module axi_ad9001_core #(
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.ID (ID),
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.ENABLED (INDEPENDENT_1R1T_SUPPORT),
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.CMOS_LVDS_N (CMOS_LVDS_N),
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.USE_RX_CLK_FOR_TX (USE_RX_CLK_FOR_TX),
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.COMMON_BASE_ADDR ('h10),
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.CHANNEL_BASE_ADDR ('h11),
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.MODE_R1 (1),
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@ -39,6 +39,7 @@ module axi_adrv9001_tx #(
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parameter ID = 0,
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parameter ENABLED = 1,
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parameter CMOS_LVDS_N = 0,
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parameter USE_RX_CLK_FOR_TX = 0,
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parameter COMMON_BASE_ADDR = 'h10,
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parameter CHANNEL_BASE_ADDR = 'h11,
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parameter MODE_R1 = 1,
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@ -131,7 +132,8 @@ end else begin : core_enabled
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// configuration settings
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localparam CONFIG = (CMOS_LVDS_N * 128) +
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localparam CONFIG = (USE_RX_CLK_FOR_TX * 1024) +
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(CMOS_LVDS_N * 128) +
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(MODE_R1 * 16) +
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(DDS_DISABLE * 64) +
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(IQCORRECTION_DISABLE * 1);
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