arradio/c5soc- remove qsys files
Rejeesh Kutty
parent
589e6b53d8
commit
c7351f3ce3
|
|
@ -1,390 +0,0 @@
|
|||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<system name="$${FILENAME}">
|
||||
<component
|
||||
name="$${FILENAME}"
|
||||
displayName="$${FILENAME}"
|
||||
version="1.0"
|
||||
description=""
|
||||
tags=""
|
||||
categories="System" />
|
||||
<parameter name="bonusData"><![CDATA[bonusData
|
||||
{
|
||||
element arradio
|
||||
{
|
||||
datum _sortIndex
|
||||
{
|
||||
value = "2";
|
||||
type = "int";
|
||||
}
|
||||
}
|
||||
element arradio.axi_ad9361_s_axi
|
||||
{
|
||||
datum baseAddress
|
||||
{
|
||||
value = "131072";
|
||||
type = "String";
|
||||
}
|
||||
}
|
||||
element arradio.axi_dmac_adc_s_axi
|
||||
{
|
||||
datum baseAddress
|
||||
{
|
||||
value = "0";
|
||||
type = "String";
|
||||
}
|
||||
}
|
||||
element arradio.axi_dmac_dac_s_axi
|
||||
{
|
||||
datum baseAddress
|
||||
{
|
||||
value = "16384";
|
||||
type = "String";
|
||||
}
|
||||
}
|
||||
element arradio.gpio_s1
|
||||
{
|
||||
datum baseAddress
|
||||
{
|
||||
value = "36864";
|
||||
type = "String";
|
||||
}
|
||||
}
|
||||
element arradio.spi_ad9361_spi_control_port
|
||||
{
|
||||
datum baseAddress
|
||||
{
|
||||
value = "32768";
|
||||
type = "String";
|
||||
}
|
||||
}
|
||||
element c5soc
|
||||
{
|
||||
datum _sortIndex
|
||||
{
|
||||
value = "1";
|
||||
type = "int";
|
||||
}
|
||||
}
|
||||
element sys_clk
|
||||
{
|
||||
datum _sortIndex
|
||||
{
|
||||
value = "0";
|
||||
type = "int";
|
||||
}
|
||||
}
|
||||
element system_bd
|
||||
{
|
||||
datum _originalDeviceFamily
|
||||
{
|
||||
value = "Cyclone V";
|
||||
type = "String";
|
||||
}
|
||||
}
|
||||
element system_bd
|
||||
{
|
||||
datum _originalDeviceFamily
|
||||
{
|
||||
value = "Cyclone V";
|
||||
type = "String";
|
||||
}
|
||||
}
|
||||
element system_bd
|
||||
{
|
||||
datum _originalDeviceFamily
|
||||
{
|
||||
value = "Cyclone V";
|
||||
type = "String";
|
||||
}
|
||||
}
|
||||
element system_bd
|
||||
{
|
||||
datum _originalDeviceFamily
|
||||
{
|
||||
value = "Cyclone V";
|
||||
type = "String";
|
||||
}
|
||||
}
|
||||
element system_bd
|
||||
{
|
||||
datum _originalDeviceFamily
|
||||
{
|
||||
value = "Cyclone V";
|
||||
type = "String";
|
||||
}
|
||||
}
|
||||
}
|
||||
]]></parameter>
|
||||
<parameter name="clockCrossingAdapter" value="FIFO" />
|
||||
<parameter name="device" value="5CSXFC6D6F31C8ES" />
|
||||
<parameter name="deviceFamily" value="Cyclone V" />
|
||||
<parameter name="deviceSpeedGrade" value="8_H6" />
|
||||
<parameter name="fabricMode" value="QSYS" />
|
||||
<parameter name="generateLegacySim" value="false" />
|
||||
<parameter name="generationId" value="0" />
|
||||
<parameter name="globalResetBus" value="false" />
|
||||
<parameter name="hdlLanguage" value="VERILOG" />
|
||||
<parameter name="hideFromIPCatalog" value="false" />
|
||||
<parameter name="lockedInterfaceDefinition" value="" />
|
||||
<parameter name="maxAdditionalLatency" value="2" />
|
||||
<parameter name="projectName" value="arradio_c5soc.qpf" />
|
||||
<parameter name="sopcBorderPoints" value="false" />
|
||||
<parameter name="systemHash" value="0" />
|
||||
<parameter name="testBenchDutName" value="" />
|
||||
<parameter name="timeStamp" value="0" />
|
||||
<parameter name="useTestBenchNamingPattern" value="false" />
|
||||
<instanceScript></instanceScript>
|
||||
<interface
|
||||
name="axi_ad9361_delay_clk"
|
||||
internal="arradio.axi_ad9361_delay_clk"
|
||||
type="clock"
|
||||
dir="end" />
|
||||
<interface
|
||||
name="axi_ad9361_device_clock"
|
||||
internal="arradio.axi_ad9361_device_clock" />
|
||||
<interface
|
||||
name="axi_ad9361_device_if"
|
||||
internal="arradio.axi_ad9361_device_if"
|
||||
type="conduit"
|
||||
dir="end" />
|
||||
<interface name="axi_ad9361_l_clk" internal="arradio.axi_ad9361_l_clk" />
|
||||
<interface
|
||||
name="axi_ad9361_up_enable"
|
||||
internal="arradio.axi_ad9361_up_enable"
|
||||
type="conduit"
|
||||
dir="end" />
|
||||
<interface
|
||||
name="axi_ad9361_up_txnrx"
|
||||
internal="arradio.axi_ad9361_up_txnrx"
|
||||
type="conduit"
|
||||
dir="end" />
|
||||
<interface
|
||||
name="gpio"
|
||||
internal="arradio.gpio_external_connection"
|
||||
type="conduit"
|
||||
dir="end" />
|
||||
<interface
|
||||
name="spi"
|
||||
internal="arradio.spi_ad9361_external"
|
||||
type="conduit"
|
||||
dir="end" />
|
||||
<interface name="sys_clk" internal="sys_clk.clk_in" type="clock" dir="end" />
|
||||
<interface
|
||||
name="sys_gpio"
|
||||
internal="c5soc.sys_gpio_external_connection"
|
||||
type="conduit"
|
||||
dir="end" />
|
||||
<interface
|
||||
name="sys_hps_io"
|
||||
internal="c5soc.sys_hps_hps_io"
|
||||
type="conduit"
|
||||
dir="end" />
|
||||
<interface
|
||||
name="sys_hps_mem"
|
||||
internal="c5soc.sys_hps_memory"
|
||||
type="conduit"
|
||||
dir="end" />
|
||||
<interface
|
||||
name="sys_hps_reset"
|
||||
internal="c5soc.sys_hps_h2f_reset"
|
||||
type="reset"
|
||||
dir="start" />
|
||||
<interface name="sys_hps_spim0" internal="c5soc.sys_hps_spim0" />
|
||||
<interface name="sys_hps_spim0_sclk_out" internal="c5soc.sys_hps_spim0_sclk_out" />
|
||||
<interface
|
||||
name="sys_reset"
|
||||
internal="sys_clk.clk_in_reset"
|
||||
type="reset"
|
||||
dir="end" />
|
||||
<interface
|
||||
name="vga_clk"
|
||||
internal="c5soc.vga_pixel_clock_bridge_out_clk"
|
||||
type="clock"
|
||||
dir="start" />
|
||||
<interface
|
||||
name="vga_if"
|
||||
internal="c5soc.vga_clock_video_output_clocked_video"
|
||||
type="conduit"
|
||||
dir="end" />
|
||||
<module name="arradio" kind="arradio_bd" version="1.0" enabled="1">
|
||||
<parameter name="AUTO_AXI_AD9361_DELAY_CLK_CLOCK_DOMAIN" value="1" />
|
||||
<parameter name="AUTO_AXI_AD9361_DELAY_CLK_CLOCK_RATE" value="0" />
|
||||
<parameter name="AUTO_AXI_AD9361_DELAY_CLK_RESET_DOMAIN" value="1" />
|
||||
<parameter name="AUTO_AXI_DMAC_ADC_M_DEST_AXI_ADDRESS_MAP"><![CDATA[<address-map><slave name='c5soc_sys_hps_bridges.f2h_sdram1_data' start='0x0' end='0x100000000' /></address-map>]]></parameter>
|
||||
<parameter
|
||||
name="AUTO_AXI_DMAC_ADC_M_DEST_AXI_ADDRESS_WIDTH"
|
||||
value="AddressWidth = 32" />
|
||||
<parameter name="AUTO_AXI_DMAC_DAC_M_SRC_AXI_ADDRESS_MAP"><![CDATA[<address-map><slave name='c5soc_sys_hps_bridges.f2h_sdram2_data' start='0x0' end='0x100000000' /></address-map>]]></parameter>
|
||||
<parameter
|
||||
name="AUTO_AXI_DMAC_DAC_M_SRC_AXI_ADDRESS_WIDTH"
|
||||
value="AddressWidth = 32" />
|
||||
<parameter name="AUTO_DEVICE" value="5CSXFC6D6F31C8ES" />
|
||||
<parameter name="AUTO_DEVICE_FAMILY" value="Cyclone V" />
|
||||
<parameter name="AUTO_DEVICE_SPEEDGRADE" value="8_H6" />
|
||||
<parameter name="AUTO_GENERATION_ID" value="0" />
|
||||
<parameter name="AUTO_MEM_CLK_CLOCK_DOMAIN" value="6" />
|
||||
<parameter name="AUTO_MEM_CLK_CLOCK_RATE" value="80000000" />
|
||||
<parameter name="AUTO_MEM_CLK_RESET_DOMAIN" value="6" />
|
||||
<parameter name="AUTO_SYS_CLK_CLOCK_DOMAIN" value="2" />
|
||||
<parameter name="AUTO_SYS_CLK_CLOCK_RATE" value="50000000" />
|
||||
<parameter name="AUTO_SYS_CLK_RESET_DOMAIN" value="2" />
|
||||
<parameter name="AUTO_UNIQUE_ID">$${FILENAME}_arradio</parameter>
|
||||
</module>
|
||||
<module name="c5soc" kind="c5soc_system_bd" version="1.0" enabled="1">
|
||||
<parameter name="AUTO_DEVICE" value="5CSXFC6D6F31C8ES" />
|
||||
<parameter name="AUTO_DEVICE_FAMILY" value="Cyclone V" />
|
||||
<parameter name="AUTO_DEVICE_SPEEDGRADE" value="8_H6" />
|
||||
<parameter name="AUTO_GENERATION_ID" value="0" />
|
||||
<parameter name="AUTO_SYS_CLK_CLOCK_DOMAIN" value="2" />
|
||||
<parameter name="AUTO_SYS_CLK_CLOCK_RATE" value="50000000" />
|
||||
<parameter name="AUTO_SYS_CLK_RESET_DOMAIN" value="2" />
|
||||
<parameter name="AUTO_SYS_CPU_INTERCONNECT_M0_ADDRESS_MAP"><![CDATA[<address-map><slave name='arradio_axi_dmac_adc.s_axi' start='0x0' end='0x4000' /><slave name='arradio_axi_dmac_dac.s_axi' start='0x4000' end='0x8000' /><slave name='arradio_spi_ad9361.spi_control_port' start='0x8000' end='0x8020' /><slave name='arradio_gpio.s1' start='0x9000' end='0x9010' /><slave name='arradio_axi_ad9361.s_axi' start='0x20000' end='0x30000' /></address-map>]]></parameter>
|
||||
<parameter
|
||||
name="AUTO_SYS_CPU_INTERCONNECT_M0_ADDRESS_WIDTH"
|
||||
value="AddressWidth = 18" />
|
||||
<parameter name="AUTO_SYS_INTR_INTERRUPTS_USED" value="7" />
|
||||
<parameter name="AUTO_UNIQUE_ID" value="$${FILENAME}_c5soc" />
|
||||
</module>
|
||||
<module name="sys_clk" kind="clock_source" version="15.1" enabled="1">
|
||||
<parameter name="clockFrequency" value="50000000" />
|
||||
<parameter name="clockFrequencyKnown" value="true" />
|
||||
<parameter name="inputClockFrequency" value="0" />
|
||||
<parameter name="resetSynchronousEdges" value="NONE" />
|
||||
</module>
|
||||
<connection
|
||||
kind="avalon"
|
||||
version="15.1"
|
||||
start="arradio.axi_dmac_adc_m_dest_axi"
|
||||
end="c5soc.sys_mem_interconnect_axi0_s0">
|
||||
<parameter name="arbitrationPriority" value="1" />
|
||||
<parameter name="baseAddress" value="0x0000" />
|
||||
<parameter name="defaultConnection" value="false" />
|
||||
</connection>
|
||||
<connection
|
||||
kind="avalon"
|
||||
version="15.1"
|
||||
start="arradio.axi_dmac_dac_m_src_axi"
|
||||
end="c5soc.sys_mem_interconnect_axi1_s0">
|
||||
<parameter name="arbitrationPriority" value="1" />
|
||||
<parameter name="baseAddress" value="0x0000" />
|
||||
<parameter name="defaultConnection" value="false" />
|
||||
</connection>
|
||||
<connection
|
||||
kind="avalon"
|
||||
version="15.1"
|
||||
start="c5soc.sys_cpu_interconnect_m0"
|
||||
end="arradio.axi_ad9361_s_axi">
|
||||
<parameter name="arbitrationPriority" value="1" />
|
||||
<parameter name="baseAddress" value="0x00020000" />
|
||||
<parameter name="defaultConnection" value="false" />
|
||||
</connection>
|
||||
<connection
|
||||
kind="avalon"
|
||||
version="15.1"
|
||||
start="c5soc.sys_cpu_interconnect_m0"
|
||||
end="arradio.axi_dmac_adc_s_axi">
|
||||
<parameter name="arbitrationPriority" value="1" />
|
||||
<parameter name="baseAddress" value="0x0000" />
|
||||
<parameter name="defaultConnection" value="false" />
|
||||
</connection>
|
||||
<connection
|
||||
kind="avalon"
|
||||
version="15.1"
|
||||
start="c5soc.sys_cpu_interconnect_m0"
|
||||
end="arradio.axi_dmac_dac_s_axi">
|
||||
<parameter name="arbitrationPriority" value="1" />
|
||||
<parameter name="baseAddress" value="0x4000" />
|
||||
<parameter name="defaultConnection" value="false" />
|
||||
</connection>
|
||||
<connection
|
||||
kind="avalon"
|
||||
version="15.1"
|
||||
start="c5soc.sys_cpu_interconnect_m0"
|
||||
end="arradio.gpio_s1">
|
||||
<parameter name="arbitrationPriority" value="1" />
|
||||
<parameter name="baseAddress" value="0x9000" />
|
||||
<parameter name="defaultConnection" value="false" />
|
||||
</connection>
|
||||
<connection
|
||||
kind="avalon"
|
||||
version="15.1"
|
||||
start="c5soc.sys_cpu_interconnect_m0"
|
||||
end="arradio.spi_ad9361_spi_control_port">
|
||||
<parameter name="arbitrationPriority" value="1" />
|
||||
<parameter name="baseAddress" value="0x8000" />
|
||||
<parameter name="defaultConnection" value="false" />
|
||||
</connection>
|
||||
<connection kind="clock" version="15.1" start="sys_clk.clk" end="c5soc.sys_clk" />
|
||||
<connection kind="clock" version="15.1" start="sys_clk.clk" end="arradio.sys_clk" />
|
||||
<connection
|
||||
kind="clock"
|
||||
version="15.1"
|
||||
start="c5soc.mem_clk"
|
||||
end="arradio.mem_clk" />
|
||||
<connection
|
||||
kind="interrupt"
|
||||
version="15.1"
|
||||
start="c5soc.sys_intr"
|
||||
end="arradio.axi_dmac_adc_intr">
|
||||
<parameter name="irqNumber" value="2" />
|
||||
</connection>
|
||||
<connection
|
||||
kind="interrupt"
|
||||
version="15.1"
|
||||
start="c5soc.sys_intr"
|
||||
end="arradio.axi_dmac_dac_intr">
|
||||
<parameter name="irqNumber" value="1" />
|
||||
</connection>
|
||||
<connection
|
||||
kind="interrupt"
|
||||
version="15.1"
|
||||
start="c5soc.sys_intr"
|
||||
end="arradio.spi_ad9361_irq">
|
||||
<parameter name="irqNumber" value="0" />
|
||||
</connection>
|
||||
<connection
|
||||
kind="reset"
|
||||
version="15.1"
|
||||
start="sys_clk.clk_reset"
|
||||
end="c5soc.sys_rst" />
|
||||
<connection
|
||||
kind="reset"
|
||||
version="15.1"
|
||||
start="sys_clk.clk_reset"
|
||||
end="arradio.sys_rst" />
|
||||
<connection
|
||||
kind="reset"
|
||||
version="15.1"
|
||||
start="c5soc.mem_rst"
|
||||
end="arradio.mem_rst" />
|
||||
<interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="FIFO" />
|
||||
<interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="2" />
|
||||
<interconnectRequirement
|
||||
for="mm_interconnect_0|cmd_mux"
|
||||
name="qsys_mm.postTransform.pipelineCount"
|
||||
value="0" />
|
||||
<interconnectRequirement
|
||||
for="mm_interconnect_2|cmd_mux"
|
||||
name="qsys_mm.postTransform.pipelineCount"
|
||||
value="0" />
|
||||
<interconnectRequirement
|
||||
for="mm_interconnect_3|cmd_mux"
|
||||
name="qsys_mm.postTransform.pipelineCount"
|
||||
value="0" />
|
||||
<interconnectRequirement
|
||||
for="mm_interconnect_3|cmd_mux_001"
|
||||
name="qsys_mm.postTransform.pipelineCount"
|
||||
value="0" />
|
||||
<interconnectRequirement
|
||||
for="mm_interconnect_4|axi_dmac_dac_m_src_axi_agent.write_cp/router.sink"
|
||||
name="qsys_mm.postTransform.pipelineCount"
|
||||
value="0" />
|
||||
<interconnectRequirement
|
||||
for="mm_interconnect_4|cmd_mux"
|
||||
name="qsys_mm.postTransform.pipelineCount"
|
||||
value="0" />
|
||||
<interconnectRequirement
|
||||
for="mm_interconnect_4|cmd_mux_001"
|
||||
name="qsys_mm.postTransform.pipelineCount"
|
||||
value="0" />
|
||||
</system>
|
||||
|
|
@ -1,936 +0,0 @@
|
|||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<system name="$${FILENAME}">
|
||||
<component
|
||||
name="$${FILENAME}"
|
||||
displayName="$${FILENAME}"
|
||||
version="1.0"
|
||||
description=""
|
||||
tags=""
|
||||
categories="System" />
|
||||
<parameter name="bonusData"><![CDATA[bonusData
|
||||
{
|
||||
element arradio_bd
|
||||
{
|
||||
datum _originalDeviceFamily
|
||||
{
|
||||
value = "Cyclone V";
|
||||
type = "String";
|
||||
}
|
||||
}
|
||||
element arradio_bd
|
||||
{
|
||||
datum _originalDeviceFamily
|
||||
{
|
||||
value = "Cyclone V";
|
||||
type = "String";
|
||||
}
|
||||
}
|
||||
element arradio_bd
|
||||
{
|
||||
datum _originalDeviceFamily
|
||||
{
|
||||
value = "Cyclone V";
|
||||
type = "String";
|
||||
}
|
||||
}
|
||||
element arradio_bd
|
||||
{
|
||||
datum _originalDeviceFamily
|
||||
{
|
||||
value = "Cyclone V";
|
||||
type = "String";
|
||||
}
|
||||
}
|
||||
element arradio_bd
|
||||
{
|
||||
datum _originalDeviceFamily
|
||||
{
|
||||
value = "Cyclone V";
|
||||
type = "String";
|
||||
}
|
||||
}
|
||||
element arradio_bd
|
||||
{
|
||||
datum _originalDeviceFamily
|
||||
{
|
||||
value = "Cyclone V";
|
||||
type = "String";
|
||||
}
|
||||
}
|
||||
element arradio_bd
|
||||
{
|
||||
datum _originalDeviceFamily
|
||||
{
|
||||
value = "Cyclone V";
|
||||
type = "String";
|
||||
}
|
||||
}
|
||||
element arradio_bd
|
||||
{
|
||||
datum _originalDeviceFamily
|
||||
{
|
||||
value = "Cyclone V";
|
||||
type = "String";
|
||||
}
|
||||
}
|
||||
element arradio_bd
|
||||
{
|
||||
datum _originalDeviceFamily
|
||||
{
|
||||
value = "Cyclone V";
|
||||
type = "String";
|
||||
}
|
||||
}
|
||||
element arradio_bd
|
||||
{
|
||||
datum _originalDeviceFamily
|
||||
{
|
||||
value = "Cyclone V";
|
||||
type = "String";
|
||||
}
|
||||
}
|
||||
element axi_ad9361
|
||||
{
|
||||
datum _sortIndex
|
||||
{
|
||||
value = "4";
|
||||
type = "int";
|
||||
}
|
||||
datum sopceditor_expanded
|
||||
{
|
||||
value = "1";
|
||||
type = "boolean";
|
||||
}
|
||||
}
|
||||
element axi_ad9361.s_axi
|
||||
{
|
||||
datum baseAddress
|
||||
{
|
||||
value = "131072";
|
||||
type = "String";
|
||||
}
|
||||
}
|
||||
element axi_adc_dma
|
||||
{
|
||||
datum _sortIndex
|
||||
{
|
||||
value = "9";
|
||||
type = "int";
|
||||
}
|
||||
datum sopceditor_expanded
|
||||
{
|
||||
value = "1";
|
||||
type = "boolean";
|
||||
}
|
||||
}
|
||||
element axi_adc_dma.s_axi
|
||||
{
|
||||
datum baseAddress
|
||||
{
|
||||
value = "0";
|
||||
type = "String";
|
||||
}
|
||||
}
|
||||
element axi_dac_dma
|
||||
{
|
||||
datum _sortIndex
|
||||
{
|
||||
value = "10";
|
||||
type = "int";
|
||||
}
|
||||
datum sopceditor_expanded
|
||||
{
|
||||
value = "1";
|
||||
type = "boolean";
|
||||
}
|
||||
}
|
||||
element axi_dac_dma.s_axi
|
||||
{
|
||||
datum baseAddress
|
||||
{
|
||||
value = "16384";
|
||||
type = "String";
|
||||
}
|
||||
}
|
||||
element gpio
|
||||
{
|
||||
datum _sortIndex
|
||||
{
|
||||
value = "12";
|
||||
type = "int";
|
||||
}
|
||||
}
|
||||
element mem_clk
|
||||
{
|
||||
datum _sortIndex
|
||||
{
|
||||
value = "2";
|
||||
type = "int";
|
||||
}
|
||||
}
|
||||
element mem_rst
|
||||
{
|
||||
datum _sortIndex
|
||||
{
|
||||
value = "3";
|
||||
type = "int";
|
||||
}
|
||||
}
|
||||
element spi_ad9361
|
||||
{
|
||||
datum _sortIndex
|
||||
{
|
||||
value = "11";
|
||||
type = "int";
|
||||
}
|
||||
datum sopceditor_expanded
|
||||
{
|
||||
value = "1";
|
||||
type = "boolean";
|
||||
}
|
||||
}
|
||||
element spi_ad9361.spi_control_port
|
||||
{
|
||||
datum baseAddress
|
||||
{
|
||||
value = "32768";
|
||||
type = "String";
|
||||
}
|
||||
}
|
||||
element sys_clk
|
||||
{
|
||||
datum _sortIndex
|
||||
{
|
||||
value = "0";
|
||||
type = "int";
|
||||
}
|
||||
}
|
||||
element sys_rst
|
||||
{
|
||||
datum _sortIndex
|
||||
{
|
||||
value = "1";
|
||||
type = "int";
|
||||
}
|
||||
}
|
||||
element util_adc_pack
|
||||
{
|
||||
datum _sortIndex
|
||||
{
|
||||
value = "7";
|
||||
type = "int";
|
||||
}
|
||||
datum sopceditor_expanded
|
||||
{
|
||||
value = "1";
|
||||
type = "boolean";
|
||||
}
|
||||
}
|
||||
element util_adc_wfifo
|
||||
{
|
||||
datum _sortIndex
|
||||
{
|
||||
value = "5";
|
||||
type = "int";
|
||||
}
|
||||
}
|
||||
element util_dac_rfifo
|
||||
{
|
||||
datum _sortIndex
|
||||
{
|
||||
value = "6";
|
||||
type = "int";
|
||||
}
|
||||
}
|
||||
element util_dac_upack
|
||||
{
|
||||
datum _sortIndex
|
||||
{
|
||||
value = "8";
|
||||
type = "int";
|
||||
}
|
||||
datum sopceditor_expanded
|
||||
{
|
||||
value = "1";
|
||||
type = "boolean";
|
||||
}
|
||||
}
|
||||
}
|
||||
]]></parameter>
|
||||
<parameter name="clockCrossingAdapter" value="FIFO" />
|
||||
<parameter name="device" value="5CSXFC6D6F31C8ES" />
|
||||
<parameter name="deviceFamily" value="Cyclone V" />
|
||||
<parameter name="deviceSpeedGrade" value="8_H6" />
|
||||
<parameter name="fabricMode" value="QSYS" />
|
||||
<parameter name="generateLegacySim" value="false" />
|
||||
<parameter name="generationId" value="0" />
|
||||
<parameter name="globalResetBus" value="false" />
|
||||
<parameter name="hdlLanguage" value="VERILOG" />
|
||||
<parameter name="hideFromIPCatalog" value="false" />
|
||||
<parameter name="lockedInterfaceDefinition" value="" />
|
||||
<parameter name="maxAdditionalLatency" value="2" />
|
||||
<parameter name="projectName" value="" />
|
||||
<parameter name="sopcBorderPoints" value="false" />
|
||||
<parameter name="systemHash" value="0" />
|
||||
<parameter name="testBenchDutName" value="" />
|
||||
<parameter name="timeStamp" value="0" />
|
||||
<parameter name="useTestBenchNamingPattern" value="false" />
|
||||
<instanceScript></instanceScript>
|
||||
<interface
|
||||
name="axi_ad9361_delay_clk"
|
||||
internal="axi_ad9361.if_delay_clk"
|
||||
type="clock"
|
||||
dir="end" />
|
||||
<interface name="axi_ad9361_device_clock" internal="axi_ad9361.device_clock" />
|
||||
<interface
|
||||
name="axi_ad9361_device_if"
|
||||
internal="axi_ad9361.device_if"
|
||||
type="conduit"
|
||||
dir="end" />
|
||||
<interface
|
||||
name="axi_ad9361_s_axi"
|
||||
internal="axi_ad9361.s_axi"
|
||||
type="axi4lite"
|
||||
dir="end" />
|
||||
<interface
|
||||
name="axi_ad9361_up_enable"
|
||||
internal="axi_ad9361.if_up_enable"
|
||||
type="conduit"
|
||||
dir="end" />
|
||||
<interface
|
||||
name="axi_ad9361_up_txnrx"
|
||||
internal="axi_ad9361.if_up_txnrx"
|
||||
type="conduit"
|
||||
dir="end" />
|
||||
<interface
|
||||
name="axi_dmac_adc_fifo_wr_clock"
|
||||
internal="axi_adc_dma.fifo_wr_clock" />
|
||||
<interface name="axi_dmac_adc_fifo_wr_if" internal="axi_adc_dma.fifo_wr_if" />
|
||||
<interface
|
||||
name="axi_dmac_adc_intr"
|
||||
internal="axi_adc_dma.interrupt_sender"
|
||||
type="interrupt"
|
||||
dir="end" />
|
||||
<interface
|
||||
name="axi_dmac_adc_m_dest_axi"
|
||||
internal="axi_adc_dma.m_dest_axi"
|
||||
type="axi4"
|
||||
dir="start" />
|
||||
<interface
|
||||
name="axi_dmac_adc_s_axi"
|
||||
internal="axi_adc_dma.s_axi"
|
||||
type="axi4lite"
|
||||
dir="end" />
|
||||
<interface
|
||||
name="axi_dmac_dac_fifo_rd_clock"
|
||||
internal="axi_dac_dma.fifo_rd_clock" />
|
||||
<interface name="axi_dmac_dac_fifo_rd_if" internal="axi_dac_dma.fifo_rd_if" />
|
||||
<interface
|
||||
name="axi_dmac_dac_intr"
|
||||
internal="axi_dac_dma.interrupt_sender"
|
||||
type="interrupt"
|
||||
dir="end" />
|
||||
<interface
|
||||
name="axi_dmac_dac_m_src_axi"
|
||||
internal="axi_dac_dma.m_src_axi"
|
||||
type="axi4"
|
||||
dir="start" />
|
||||
<interface
|
||||
name="axi_dmac_dac_s_axi"
|
||||
internal="axi_dac_dma.s_axi"
|
||||
type="axi4lite"
|
||||
dir="end" />
|
||||
<interface
|
||||
name="gpio_external_connection"
|
||||
internal="gpio.external_connection"
|
||||
type="conduit"
|
||||
dir="end" />
|
||||
<interface name="gpio_s1" internal="gpio.s1" type="avalon" dir="end" />
|
||||
<interface name="mem_clk" internal="mem_clk.in_clk" type="clock" dir="end" />
|
||||
<interface name="mem_rst" internal="mem_rst.in_reset" type="reset" dir="end" />
|
||||
<interface
|
||||
name="spi_ad9361_external"
|
||||
internal="spi_ad9361.external"
|
||||
type="conduit"
|
||||
dir="end" />
|
||||
<interface
|
||||
name="spi_ad9361_irq"
|
||||
internal="spi_ad9361.irq"
|
||||
type="interrupt"
|
||||
dir="end" />
|
||||
<interface
|
||||
name="spi_ad9361_spi_control_port"
|
||||
internal="spi_ad9361.spi_control_port"
|
||||
type="avalon"
|
||||
dir="end" />
|
||||
<interface name="sys_clk" internal="sys_clk.in_clk" type="clock" dir="end" />
|
||||
<interface name="sys_rst" internal="sys_rst.in_reset" type="reset" dir="end" />
|
||||
<module name="axi_ad9361" kind="axi_ad9361" version="1.0" enabled="1">
|
||||
<parameter name="ADC_DATAPATH_DISABLE" value="0" />
|
||||
<parameter name="CMOS_OR_LVDS_N" value="0" />
|
||||
<parameter name="DAC_DATAPATH_DISABLE" value="0" />
|
||||
<parameter name="DEVICE_FAMILY" value="Cyclone V" />
|
||||
<parameter name="DEVICE_TYPE" value="1" />
|
||||
<parameter name="ID" value="0" />
|
||||
</module>
|
||||
<module name="axi_adc_dma" kind="axi_dmac" version="1.0" enabled="1">
|
||||
<parameter name="ASYNC_CLK_DEST_REQ" value="1" />
|
||||
<parameter name="ASYNC_CLK_REQ_SRC" value="1" />
|
||||
<parameter name="ASYNC_CLK_SRC_DEST" value="1" />
|
||||
<parameter name="AXI_SLICE_DEST" value="0" />
|
||||
<parameter name="AXI_SLICE_SRC" value="0" />
|
||||
<parameter name="CYCLIC" value="0" />
|
||||
<parameter name="DMA_2D_TRANSFER" value="0" />
|
||||
<parameter name="DMA_DATA_WIDTH_DEST" value="64" />
|
||||
<parameter name="DMA_DATA_WIDTH_SRC" value="64" />
|
||||
<parameter name="DMA_LENGTH_WIDTH" value="24" />
|
||||
<parameter name="DMA_TYPE_DEST" value="0" />
|
||||
<parameter name="DMA_TYPE_SRC" value="2" />
|
||||
<parameter name="FIFO_SIZE" value="4" />
|
||||
<parameter name="ID" value="0" />
|
||||
<parameter name="SYNC_TRANSFER_START" value="1" />
|
||||
</module>
|
||||
<module name="axi_dac_dma" kind="axi_dmac" version="1.0" enabled="1">
|
||||
<parameter name="ASYNC_CLK_DEST_REQ" value="1" />
|
||||
<parameter name="ASYNC_CLK_REQ_SRC" value="1" />
|
||||
<parameter name="ASYNC_CLK_SRC_DEST" value="1" />
|
||||
<parameter name="AXI_SLICE_DEST" value="0" />
|
||||
<parameter name="AXI_SLICE_SRC" value="0" />
|
||||
<parameter name="CYCLIC" value="1" />
|
||||
<parameter name="DMA_2D_TRANSFER" value="0" />
|
||||
<parameter name="DMA_DATA_WIDTH_DEST" value="64" />
|
||||
<parameter name="DMA_DATA_WIDTH_SRC" value="64" />
|
||||
<parameter name="DMA_LENGTH_WIDTH" value="24" />
|
||||
<parameter name="DMA_TYPE_DEST" value="2" />
|
||||
<parameter name="DMA_TYPE_SRC" value="0" />
|
||||
<parameter name="FIFO_SIZE" value="4" />
|
||||
<parameter name="ID" value="0" />
|
||||
<parameter name="SYNC_TRANSFER_START" value="0" />
|
||||
</module>
|
||||
<module name="gpio" kind="altera_avalon_pio" version="15.1" enabled="1">
|
||||
<parameter name="bitClearingEdgeCapReg" value="false" />
|
||||
<parameter name="bitModifyingOutReg" value="false" />
|
||||
<parameter name="captureEdge" value="false" />
|
||||
<parameter name="clockRate" value="50000000" />
|
||||
<parameter name="direction" value="Output" />
|
||||
<parameter name="edgeType" value="RISING" />
|
||||
<parameter name="generateIRQ" value="false" />
|
||||
<parameter name="irqType" value="LEVEL" />
|
||||
<parameter name="resetValue" value="0" />
|
||||
<parameter name="simDoTestBenchWiring" value="false" />
|
||||
<parameter name="simDrivenValue" value="0" />
|
||||
<parameter name="width" value="5" />
|
||||
</module>
|
||||
<module name="mem_clk" kind="altera_clock_bridge" version="15.1" enabled="1">
|
||||
<parameter name="DERIVED_CLOCK_RATE" value="0" />
|
||||
<parameter name="EXPLICIT_CLOCK_RATE" value="0" />
|
||||
<parameter name="NUM_CLOCK_OUTPUTS" value="1" />
|
||||
</module>
|
||||
<module name="mem_rst" kind="altera_reset_bridge" version="15.1" enabled="1">
|
||||
<parameter name="ACTIVE_LOW_RESET" value="0" />
|
||||
<parameter name="AUTO_CLK_CLOCK_RATE" value="-1" />
|
||||
<parameter name="NUM_RESET_OUTPUTS" value="1" />
|
||||
<parameter name="SYNCHRONOUS_EDGES" value="none" />
|
||||
<parameter name="USE_RESET_REQUEST" value="0" />
|
||||
</module>
|
||||
<module name="spi_ad9361" kind="altera_avalon_spi" version="15.1" enabled="1">
|
||||
<parameter name="avalonSpec" value="2.0" />
|
||||
<parameter name="clockPhase" value="0" />
|
||||
<parameter name="clockPolarity" value="1" />
|
||||
<parameter name="dataWidth" value="8" />
|
||||
<parameter name="disableAvalonFlowControl" value="false" />
|
||||
<parameter name="inputClockRate" value="50000000" />
|
||||
<parameter name="insertDelayBetweenSlaveSelectAndSClk" value="false" />
|
||||
<parameter name="insertSync" value="false" />
|
||||
<parameter name="lsbOrderedFirst" value="false" />
|
||||
<parameter name="masterSPI" value="true" />
|
||||
<parameter name="numberOfSlaves" value="1" />
|
||||
<parameter name="syncRegDepth" value="2" />
|
||||
<parameter name="targetClockRate" value="50000000" />
|
||||
<parameter name="targetSlaveSelectToSClkDelay" value="0.0" />
|
||||
</module>
|
||||
<module name="sys_clk" kind="altera_clock_bridge" version="15.1" enabled="1">
|
||||
<parameter name="DERIVED_CLOCK_RATE" value="0" />
|
||||
<parameter name="EXPLICIT_CLOCK_RATE" value="50000000" />
|
||||
<parameter name="NUM_CLOCK_OUTPUTS" value="1" />
|
||||
</module>
|
||||
<module name="sys_rst" kind="altera_reset_bridge" version="15.1" enabled="1">
|
||||
<parameter name="ACTIVE_LOW_RESET" value="0" />
|
||||
<parameter name="AUTO_CLK_CLOCK_RATE" value="-1" />
|
||||
<parameter name="NUM_RESET_OUTPUTS" value="1" />
|
||||
<parameter name="SYNCHRONOUS_EDGES" value="none" />
|
||||
<parameter name="USE_RESET_REQUEST" value="0" />
|
||||
</module>
|
||||
<module name="util_adc_pack" kind="util_cpack" version="1.0" enabled="1">
|
||||
<parameter name="CHANNEL_DATA_WIDTH" value="16" />
|
||||
<parameter name="NUM_OF_CHANNELS" value="4" />
|
||||
</module>
|
||||
<module name="util_adc_wfifo" kind="util_wfifo" version="1.0" enabled="1">
|
||||
<parameter name="DIN_ADDRESS_WIDTH" value="5" />
|
||||
<parameter name="DIN_DATA_WIDTH" value="16" />
|
||||
<parameter name="DOUT_DATA_WIDTH" value="16" />
|
||||
<parameter name="NUM_OF_CHANNELS" value="4" />
|
||||
</module>
|
||||
<module name="util_dac_rfifo" kind="util_rfifo" version="1.0" enabled="1">
|
||||
<parameter name="DIN_ADDRESS_WIDTH" value="5" />
|
||||
<parameter name="DIN_DATA_WIDTH" value="16" />
|
||||
<parameter name="DOUT_DATA_WIDTH" value="16" />
|
||||
<parameter name="NUM_OF_CHANNELS" value="4" />
|
||||
</module>
|
||||
<module name="util_dac_upack" kind="util_upack" version="1.0" enabled="1">
|
||||
<parameter name="CHANNEL_DATA_WIDTH" value="16" />
|
||||
<parameter name="NUM_OF_CHANNELS" value="4" />
|
||||
</module>
|
||||
<connection
|
||||
kind="clock"
|
||||
version="15.1"
|
||||
start="axi_ad9361.if_l_clk"
|
||||
end="axi_ad9361.if_clk" />
|
||||
<connection
|
||||
kind="clock"
|
||||
version="15.1"
|
||||
start="axi_ad9361.if_l_clk"
|
||||
end="util_adc_wfifo.if_din_clk" />
|
||||
<connection
|
||||
kind="clock"
|
||||
version="15.1"
|
||||
start="axi_ad9361.if_l_clk"
|
||||
end="util_dac_rfifo.if_dout_clk" />
|
||||
<connection
|
||||
kind="clock"
|
||||
version="15.1"
|
||||
start="sys_clk.out_clk"
|
||||
end="spi_ad9361.clk" />
|
||||
<connection kind="clock" version="15.1" start="sys_clk.out_clk" end="gpio.clk" />
|
||||
<connection
|
||||
kind="clock"
|
||||
version="15.1"
|
||||
start="mem_clk.out_clk"
|
||||
end="util_adc_pack.if_adc_clk" />
|
||||
<connection
|
||||
kind="clock"
|
||||
version="15.1"
|
||||
start="mem_clk.out_clk"
|
||||
end="util_dac_upack.if_dac_clk" />
|
||||
<connection
|
||||
kind="clock"
|
||||
version="15.1"
|
||||
start="mem_clk.out_clk"
|
||||
end="util_dac_rfifo.if_din_clk" />
|
||||
<connection
|
||||
kind="clock"
|
||||
version="15.1"
|
||||
start="mem_clk.out_clk"
|
||||
end="util_adc_wfifo.if_dout_clk" />
|
||||
<connection
|
||||
kind="clock"
|
||||
version="15.1"
|
||||
start="mem_clk.out_clk"
|
||||
end="axi_dac_dma.if_fifo_rd_clk" />
|
||||
<connection
|
||||
kind="clock"
|
||||
version="15.1"
|
||||
start="mem_clk.out_clk"
|
||||
end="axi_adc_dma.if_fifo_wr_clk" />
|
||||
<connection
|
||||
kind="clock"
|
||||
version="15.1"
|
||||
start="mem_clk.out_clk"
|
||||
end="axi_adc_dma.m_dest_axi_clock" />
|
||||
<connection
|
||||
kind="clock"
|
||||
version="15.1"
|
||||
start="mem_clk.out_clk"
|
||||
end="axi_dac_dma.m_src_axi_clock" />
|
||||
<connection
|
||||
kind="clock"
|
||||
version="15.1"
|
||||
start="sys_clk.out_clk"
|
||||
end="axi_ad9361.s_axi_clock" />
|
||||
<connection
|
||||
kind="clock"
|
||||
version="15.1"
|
||||
start="sys_clk.out_clk"
|
||||
end="axi_adc_dma.s_axi_clock" />
|
||||
<connection
|
||||
kind="clock"
|
||||
version="15.1"
|
||||
start="sys_clk.out_clk"
|
||||
end="axi_dac_dma.s_axi_clock" />
|
||||
<connection
|
||||
kind="conduit"
|
||||
version="15.1"
|
||||
start="axi_ad9361.adc_ch_0"
|
||||
end="util_adc_wfifo.din_0">
|
||||
<parameter name="endPort" value="" />
|
||||
<parameter name="endPortLSB" value="0" />
|
||||
<parameter name="startPort" value="" />
|
||||
<parameter name="startPortLSB" value="0" />
|
||||
<parameter name="width" value="0" />
|
||||
</connection>
|
||||
<connection
|
||||
kind="conduit"
|
||||
version="15.1"
|
||||
start="axi_ad9361.adc_ch_1"
|
||||
end="util_adc_wfifo.din_1">
|
||||
<parameter name="endPort" value="" />
|
||||
<parameter name="endPortLSB" value="0" />
|
||||
<parameter name="startPort" value="" />
|
||||
<parameter name="startPortLSB" value="0" />
|
||||
<parameter name="width" value="0" />
|
||||
</connection>
|
||||
<connection
|
||||
kind="conduit"
|
||||
version="15.1"
|
||||
start="util_adc_pack.adc_ch_1"
|
||||
end="util_adc_wfifo.dout_1">
|
||||
<parameter name="endPort" value="" />
|
||||
<parameter name="endPortLSB" value="0" />
|
||||
<parameter name="startPort" value="" />
|
||||
<parameter name="startPortLSB" value="0" />
|
||||
<parameter name="width" value="0" />
|
||||
</connection>
|
||||
<connection
|
||||
kind="conduit"
|
||||
version="15.1"
|
||||
start="axi_ad9361.adc_ch_2"
|
||||
end="util_adc_wfifo.din_2">
|
||||
<parameter name="endPort" value="" />
|
||||
<parameter name="endPortLSB" value="0" />
|
||||
<parameter name="startPort" value="" />
|
||||
<parameter name="startPortLSB" value="0" />
|
||||
<parameter name="width" value="0" />
|
||||
</connection>
|
||||
<connection
|
||||
kind="conduit"
|
||||
version="15.1"
|
||||
start="util_adc_pack.adc_ch_2"
|
||||
end="util_adc_wfifo.dout_2">
|
||||
<parameter name="endPort" value="" />
|
||||
<parameter name="endPortLSB" value="0" />
|
||||
<parameter name="startPort" value="" />
|
||||
<parameter name="startPortLSB" value="0" />
|
||||
<parameter name="width" value="0" />
|
||||
</connection>
|
||||
<connection
|
||||
kind="conduit"
|
||||
version="15.1"
|
||||
start="axi_ad9361.adc_ch_3"
|
||||
end="util_adc_wfifo.din_3">
|
||||
<parameter name="endPort" value="" />
|
||||
<parameter name="endPortLSB" value="0" />
|
||||
<parameter name="startPort" value="" />
|
||||
<parameter name="startPortLSB" value="0" />
|
||||
<parameter name="width" value="0" />
|
||||
</connection>
|
||||
<connection
|
||||
kind="conduit"
|
||||
version="15.1"
|
||||
start="util_dac_upack.dac_ch_0"
|
||||
end="util_dac_rfifo.din_0">
|
||||
<parameter name="endPort" value="" />
|
||||
<parameter name="endPortLSB" value="0" />
|
||||
<parameter name="startPort" value="" />
|
||||
<parameter name="startPortLSB" value="0" />
|
||||
<parameter name="width" value="0" />
|
||||
</connection>
|
||||
<connection
|
||||
kind="conduit"
|
||||
version="15.1"
|
||||
start="util_dac_upack.dac_ch_1"
|
||||
end="util_dac_rfifo.din_1">
|
||||
<parameter name="endPort" value="" />
|
||||
<parameter name="endPortLSB" value="0" />
|
||||
<parameter name="startPort" value="" />
|
||||
<parameter name="startPortLSB" value="0" />
|
||||
<parameter name="width" value="0" />
|
||||
</connection>
|
||||
<connection
|
||||
kind="conduit"
|
||||
version="15.1"
|
||||
start="axi_ad9361.dac_ch_1"
|
||||
end="util_dac_rfifo.dout_1">
|
||||
<parameter name="endPort" value="" />
|
||||
<parameter name="endPortLSB" value="0" />
|
||||
<parameter name="startPort" value="" />
|
||||
<parameter name="startPortLSB" value="0" />
|
||||
<parameter name="width" value="0" />
|
||||
</connection>
|
||||
<connection
|
||||
kind="conduit"
|
||||
version="15.1"
|
||||
start="util_dac_upack.dac_ch_2"
|
||||
end="util_dac_rfifo.din_2">
|
||||
<parameter name="endPort" value="" />
|
||||
<parameter name="endPortLSB" value="0" />
|
||||
<parameter name="startPort" value="" />
|
||||
<parameter name="startPortLSB" value="0" />
|
||||
<parameter name="width" value="0" />
|
||||
</connection>
|
||||
<connection
|
||||
kind="conduit"
|
||||
version="15.1"
|
||||
start="util_dac_upack.dac_ch_3"
|
||||
end="util_dac_rfifo.din_3">
|
||||
<parameter name="endPort" value="" />
|
||||
<parameter name="endPortLSB" value="0" />
|
||||
<parameter name="startPort" value="" />
|
||||
<parameter name="startPortLSB" value="0" />
|
||||
<parameter name="width" value="0" />
|
||||
</connection>
|
||||
<connection
|
||||
kind="conduit"
|
||||
version="15.1"
|
||||
start="axi_ad9361.dac_ch_3"
|
||||
end="util_dac_rfifo.dout_3">
|
||||
<parameter name="endPort" value="" />
|
||||
<parameter name="endPortLSB" value="0" />
|
||||
<parameter name="startPort" value="" />
|
||||
<parameter name="startPortLSB" value="0" />
|
||||
<parameter name="width" value="0" />
|
||||
</connection>
|
||||
<connection
|
||||
kind="conduit"
|
||||
version="15.1"
|
||||
start="util_adc_wfifo.dout_0"
|
||||
end="util_adc_pack.adc_ch_0">
|
||||
<parameter name="endPort" value="" />
|
||||
<parameter name="endPortLSB" value="0" />
|
||||
<parameter name="startPort" value="" />
|
||||
<parameter name="startPortLSB" value="0" />
|
||||
<parameter name="width" value="0" />
|
||||
</connection>
|
||||
<connection
|
||||
kind="conduit"
|
||||
version="15.1"
|
||||
start="util_dac_rfifo.dout_0"
|
||||
end="axi_ad9361.dac_ch_0">
|
||||
<parameter name="endPort" value="" />
|
||||
<parameter name="endPortLSB" value="0" />
|
||||
<parameter name="startPort" value="" />
|
||||
<parameter name="startPortLSB" value="0" />
|
||||
<parameter name="width" value="0" />
|
||||
</connection>
|
||||
<connection
|
||||
kind="conduit"
|
||||
version="15.1"
|
||||
start="util_dac_rfifo.dout_2"
|
||||
end="axi_ad9361.dac_ch_2">
|
||||
<parameter name="endPort" value="" />
|
||||
<parameter name="endPortLSB" value="0" />
|
||||
<parameter name="startPort" value="" />
|
||||
<parameter name="startPortLSB" value="0" />
|
||||
<parameter name="width" value="0" />
|
||||
</connection>
|
||||
<connection
|
||||
kind="conduit"
|
||||
version="15.1"
|
||||
start="util_adc_wfifo.dout_3"
|
||||
end="util_adc_pack.adc_ch_3">
|
||||
<parameter name="endPort" value="" />
|
||||
<parameter name="endPortLSB" value="0" />
|
||||
<parameter name="startPort" value="" />
|
||||
<parameter name="startPortLSB" value="0" />
|
||||
<parameter name="width" value="0" />
|
||||
</connection>
|
||||
<connection
|
||||
kind="conduit"
|
||||
version="15.1"
|
||||
start="util_adc_pack.if_adc_data"
|
||||
end="axi_adc_dma.if_fifo_wr_din">
|
||||
<parameter name="endPort" value="" />
|
||||
<parameter name="endPortLSB" value="0" />
|
||||
<parameter name="startPort" value="" />
|
||||
<parameter name="startPortLSB" value="0" />
|
||||
<parameter name="width" value="0" />
|
||||
</connection>
|
||||
<connection
|
||||
kind="conduit"
|
||||
version="15.1"
|
||||
start="util_adc_pack.if_adc_sync"
|
||||
end="axi_adc_dma.if_fifo_wr_sync">
|
||||
<parameter name="endPort" value="" />
|
||||
<parameter name="endPortLSB" value="0" />
|
||||
<parameter name="startPort" value="" />
|
||||
<parameter name="startPortLSB" value="0" />
|
||||
<parameter name="width" value="0" />
|
||||
</connection>
|
||||
<connection
|
||||
kind="conduit"
|
||||
version="15.1"
|
||||
start="util_adc_pack.if_adc_valid"
|
||||
end="axi_adc_dma.if_fifo_wr_en">
|
||||
<parameter name="endPort" value="" />
|
||||
<parameter name="endPortLSB" value="0" />
|
||||
<parameter name="startPort" value="" />
|
||||
<parameter name="startPortLSB" value="0" />
|
||||
<parameter name="width" value="0" />
|
||||
</connection>
|
||||
<connection
|
||||
kind="conduit"
|
||||
version="15.1"
|
||||
start="util_dac_upack.if_dac_data"
|
||||
end="axi_dac_dma.if_fifo_rd_dout">
|
||||
<parameter name="endPort" value="" />
|
||||
<parameter name="endPortLSB" value="0" />
|
||||
<parameter name="startPort" value="" />
|
||||
<parameter name="startPortLSB" value="0" />
|
||||
<parameter name="width" value="0" />
|
||||
</connection>
|
||||
<connection
|
||||
kind="conduit"
|
||||
version="15.1"
|
||||
start="util_adc_wfifo.if_din_ovf"
|
||||
end="axi_ad9361.if_adc_dovf">
|
||||
<parameter name="endPort" value="" />
|
||||
<parameter name="endPortLSB" value="0" />
|
||||
<parameter name="startPort" value="" />
|
||||
<parameter name="startPortLSB" value="0" />
|
||||
<parameter name="width" value="0" />
|
||||
</connection>
|
||||
<connection
|
||||
kind="conduit"
|
||||
version="15.1"
|
||||
start="util_dac_upack.if_dma_xfer_in"
|
||||
end="axi_dac_dma.if_fifo_rd_xfer_req">
|
||||
<parameter name="endPort" value="" />
|
||||
<parameter name="endPortLSB" value="0" />
|
||||
<parameter name="startPort" value="" />
|
||||
<parameter name="startPortLSB" value="0" />
|
||||
<parameter name="width" value="0" />
|
||||
</connection>
|
||||
<connection
|
||||
kind="conduit"
|
||||
version="15.1"
|
||||
start="util_dac_rfifo.if_dout_unf"
|
||||
end="axi_ad9361.if_dac_dunf">
|
||||
<parameter name="endPort" value="" />
|
||||
<parameter name="endPortLSB" value="0" />
|
||||
<parameter name="startPort" value="" />
|
||||
<parameter name="startPortLSB" value="0" />
|
||||
<parameter name="width" value="0" />
|
||||
</connection>
|
||||
<connection
|
||||
kind="conduit"
|
||||
version="15.1"
|
||||
start="axi_dac_dma.if_fifo_rd_en"
|
||||
end="util_dac_upack.if_dac_valid">
|
||||
<parameter name="endPort" value="" />
|
||||
<parameter name="endPortLSB" value="0" />
|
||||
<parameter name="startPort" value="" />
|
||||
<parameter name="startPortLSB" value="0" />
|
||||
<parameter name="width" value="0" />
|
||||
</connection>
|
||||
<connection
|
||||
kind="conduit"
|
||||
version="15.1"
|
||||
start="axi_dac_dma.if_fifo_rd_underflow"
|
||||
end="util_dac_rfifo.if_din_unf">
|
||||
<parameter name="endPort" value="" />
|
||||
<parameter name="endPortLSB" value="0" />
|
||||
<parameter name="startPort" value="" />
|
||||
<parameter name="startPortLSB" value="0" />
|
||||
<parameter name="width" value="0" />
|
||||
</connection>
|
||||
<connection
|
||||
kind="conduit"
|
||||
version="15.1"
|
||||
start="axi_adc_dma.if_fifo_wr_overflow"
|
||||
end="util_adc_wfifo.if_dout_ovf">
|
||||
<parameter name="endPort" value="" />
|
||||
<parameter name="endPortLSB" value="0" />
|
||||
<parameter name="startPort" value="" />
|
||||
<parameter name="startPortLSB" value="0" />
|
||||
<parameter name="width" value="0" />
|
||||
</connection>
|
||||
<connection
|
||||
kind="reset"
|
||||
version="15.1"
|
||||
start="axi_ad9361.if_rst"
|
||||
end="util_adc_wfifo.if_din_rst" />
|
||||
<connection
|
||||
kind="reset"
|
||||
version="15.1"
|
||||
start="axi_ad9361.if_rst"
|
||||
end="util_dac_rfifo.if_dout_rst" />
|
||||
<connection
|
||||
kind="reset"
|
||||
version="15.1"
|
||||
start="mem_rst.out_reset"
|
||||
end="util_adc_pack.if_adc_rst" />
|
||||
<connection
|
||||
kind="reset"
|
||||
version="15.1"
|
||||
start="mem_rst.out_reset"
|
||||
end="util_dac_rfifo.if_din_rstn" />
|
||||
<connection
|
||||
kind="reset"
|
||||
version="15.1"
|
||||
start="mem_rst.out_reset"
|
||||
end="util_adc_wfifo.if_dout_rstn" />
|
||||
<connection
|
||||
kind="reset"
|
||||
version="15.1"
|
||||
start="mem_rst.out_reset"
|
||||
end="axi_adc_dma.m_dest_axi_reset" />
|
||||
<connection
|
||||
kind="reset"
|
||||
version="15.1"
|
||||
start="mem_rst.out_reset"
|
||||
end="axi_dac_dma.m_src_axi_reset" />
|
||||
<connection
|
||||
kind="reset"
|
||||
version="15.1"
|
||||
start="sys_rst.out_reset"
|
||||
end="spi_ad9361.reset" />
|
||||
<connection
|
||||
kind="reset"
|
||||
version="15.1"
|
||||
start="sys_rst.out_reset"
|
||||
end="gpio.reset" />
|
||||
<connection
|
||||
kind="reset"
|
||||
version="15.1"
|
||||
start="sys_rst.out_reset"
|
||||
end="axi_ad9361.s_axi_reset" />
|
||||
<connection
|
||||
kind="reset"
|
||||
version="15.1"
|
||||
start="sys_rst.out_reset"
|
||||
end="axi_adc_dma.s_axi_reset" />
|
||||
<connection
|
||||
kind="reset"
|
||||
version="15.1"
|
||||
start="sys_rst.out_reset"
|
||||
end="axi_dac_dma.s_axi_reset" />
|
||||
<interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="FIFO" />
|
||||
<interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="2" />
|
||||
<interconnectRequirement
|
||||
for="mm_interconnect_0|cmd_mux"
|
||||
name="qsys_mm.postTransform.pipelineCount"
|
||||
value="0" />
|
||||
<interconnectRequirement
|
||||
for="mm_interconnect_2|cmd_mux"
|
||||
name="qsys_mm.postTransform.pipelineCount"
|
||||
value="0" />
|
||||
<interconnectRequirement
|
||||
for="mm_interconnect_3|cmd_mux"
|
||||
name="qsys_mm.postTransform.pipelineCount"
|
||||
value="0" />
|
||||
<interconnectRequirement
|
||||
for="mm_interconnect_3|cmd_mux_001"
|
||||
name="qsys_mm.postTransform.pipelineCount"
|
||||
value="0" />
|
||||
<interconnectRequirement
|
||||
for="mm_interconnect_4|axi_dmac_dac_m_src_axi_agent.write_cp/router.sink"
|
||||
name="qsys_mm.postTransform.pipelineCount"
|
||||
value="0" />
|
||||
<interconnectRequirement
|
||||
for="mm_interconnect_4|cmd_mux"
|
||||
name="qsys_mm.postTransform.pipelineCount"
|
||||
value="0" />
|
||||
<interconnectRequirement
|
||||
for="mm_interconnect_4|cmd_mux_001"
|
||||
name="qsys_mm.postTransform.pipelineCount"
|
||||
value="0" />
|
||||
</system>
|
||||
File diff suppressed because one or more lines are too long
Loading…
Reference in New Issue