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fmcomms2: c5soc: Add false path between 50MHz and VGA PLL clock 

Otherwise we get timing errors for the reset signal that is generated in the
50MHz clock domain, but used in the VGA PLL clock domain.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
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Lars-Peter Clausen 2014-09-09 14:55:53 +02:00
parent 328205c31d
commit c7989925c5
1 changed files with 4 additions and 0 deletions
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4
projects/fmcomms2/c5soc/system_constr.sdc
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@ -8,12 +8,16 @@ derive_clock_uncertainty
set clk_125m [get_clocks {i_system_bd|axi_ad9361|i_ad9361|i_dev_if|i_rx|i_altlvds_rx|auto_generated|pll_sclk~PLL_OUTPUT_COUNTER|divclk}]
set clk_vga [get_clocks {i_system_bd|vga_pll|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}]
set_false_path -from clk_50m -to clk_80m
set_false_path -from clk_50m -to $clk_125m
set_false_path -from clk_80m -to clk_50m
set_false_path -from clk_80m -to $clk_125m
set_false_path -from $clk_125m -to clk_50m
set_false_path -from $clk_125m -to clk_80m
set_false_path -from clk_50m -to $clk_vga
set_false_path -from $clk_vga -to clk_50m
create_clock -period 4.0 -name v_rx_clk