From c7d9fe56fdd7fedd1c0a8b1bd7281efb214f77db Mon Sep 17 00:00:00 2001 From: AndreiGrozav Date: Mon, 17 Sep 2018 19:56:47 +0300 Subject: [PATCH] axi_hdmi_tx: Create s_axis interface --- library/axi_hdmi_tx/axi_hdmi_tx_ip.tcl | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/library/axi_hdmi_tx/axi_hdmi_tx_ip.tcl b/library/axi_hdmi_tx/axi_hdmi_tx_ip.tcl index 919f08b19..cd5803a41 100644 --- a/library/axi_hdmi_tx/axi_hdmi_tx_ip.tcl +++ b/library/axi_hdmi_tx/axi_hdmi_tx_ip.tcl @@ -54,6 +54,14 @@ set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.INTERFACE set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.INTERFACE')) == "16_BIT_EMBEDDED_SYNC"} \ [ipx::get_ports *hdmi_16_es_data* -of_objects [ipx::current_core]] +adi_add_bus "s_axis" "slave" \ + "xilinx.com:interface:axis_rtl:1.0" \ + "xilinx.com:interface:axis:1.0" \ + [list {"vdma_ready" "TREADY"} \ + {"vdma_valid" "TVALID"} \ + {"vdma_data" "TDATA"} \ + {"vdma_end_of_frame" "TLAST"} ] + ipx::infer_bus_interface hdmi_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] ipx::infer_bus_interface hdmi_out_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] ipx::infer_bus_interface vdma_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]