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data_offload: Delete fifo_dst_rlast

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Istvan Csomortani 2021-03-23 19:19:49 +00:00 committed by Mihaita Nagy
parent 4026f2d414
commit c82b0fb420
3 changed files with 3 additions and 7 deletions
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7
library/data_offload/data_offload.v
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@ -122,7 +122,6 @@ module data_offload #(
output fifo_dst_resetn, output fifo_dst_resetn,
output [DST_ADDR_WIDTH-1:0] fifo_dst_raddr, output [DST_ADDR_WIDTH-1:0] fifo_dst_raddr,
input [DST_DATA_WIDTH-1:0] fifo_dst_rdata, input [DST_DATA_WIDTH-1:0] fifo_dst_rdata,
output fifo_dst_rlast,
// Status and monitor // Status and monitor
@ -179,7 +178,6 @@ module data_offload #(
wire m_axis_valid_s; wire m_axis_valid_s;
wire m_axis_last_s; wire m_axis_last_s;
wire [DST_DATA_WIDTH-1:0] m_axis_data_s; wire [DST_DATA_WIDTH-1:0] m_axis_data_s;
wire dst_mem_last_s;
wire dst_mem_valid_s; wire dst_mem_valid_s;
wire dst_mem_valid_int_s; wire dst_mem_valid_int_s;
wire m_axis_reset_int_s; wire m_axis_reset_int_s;
@ -208,7 +206,6 @@ module data_offload #(
end end
endgenerate endgenerate
assign fifo_src_wlast = src_wr_last_s; assign fifo_src_wlast = src_wr_last_s;
assign fifo_dst_rlast = dst_mem_last_s;
// Offload FSM and control // Offload FSM and control
data_offload_fsm #( data_offload_fsm #(
@ -233,7 +230,7 @@ module data_offload #(
.rd_ready (fifo_dst_ready_int_s), .rd_ready (fifo_dst_ready_int_s),
.rd_valid (dst_mem_valid_s), .rd_valid (dst_mem_valid_s),
.rd_addr (fifo_dst_raddr), .rd_addr (fifo_dst_raddr),
.rd_last (dst_mem_last_s), .rd_last (),
.rd_tkeep (m_axis_tkeep), .rd_tkeep (m_axis_tkeep),
.rd_oneshot (oneshot_s), .rd_oneshot (oneshot_s),
.init_req (init_req), .init_req (init_req),
@ -273,7 +270,7 @@ module data_offload #(
.rst (m_axis_reset_int_s), .rst (m_axis_reset_int_s),
.valid (dst_mem_valid_int_s), .valid (dst_mem_valid_int_s),
.data (fifo_dst_rdata), .data (fifo_dst_rdata),
.last (dst_mem_last_s), .last (1'b0),
.inf_valid (m_axis_valid_s), .inf_valid (m_axis_valid_s),
.inf_last (m_axis_last_s), .inf_last (m_axis_last_s),
.inf_data (m_axis_data_s), .inf_data (m_axis_data_s),

2
library/data_offload/data_offload_fsm.v
View File

@ -238,7 +238,7 @@ module data_offload_fsm #(
if (wr_resetn_in == 1'b0) begin if (wr_resetn_in == 1'b0) begin
wr_last_addr <= {WR_ADDRESS_WIDTH{1'b1}}; wr_last_addr <= {WR_ADDRESS_WIDTH{1'b1}};
end else begin end else begin
wr_last_addr <= (wr_last && wr_valid_out) ? wr_addr : wr_last_addr; wr_last_addr <= (wr_valid_out) ? wr_addr : wr_last_addr;
end end
end end

1
projects/common/xilinx/data_offload_bd.tcl
View File

@ -105,7 +105,6 @@ proc ad_data_offload_create {instance_name datapath_type mem_type mem_size sourc
ad_connect fifo2axi_bridge/fifo_dst_ren i_data_offload/fifo_dst_ren ad_connect fifo2axi_bridge/fifo_dst_ren i_data_offload/fifo_dst_ren
ad_connect fifo2axi_bridge/fifo_dst_raddr i_data_offload/fifo_dst_raddr ad_connect fifo2axi_bridge/fifo_dst_raddr i_data_offload/fifo_dst_raddr
ad_connect fifo2axi_bridge/fifo_dst_rdata i_data_offload/fifo_dst_rdata ad_connect fifo2axi_bridge/fifo_dst_rdata i_data_offload/fifo_dst_rdata
ad_connect fifo2axi_bridge/fifo_dst_rlast i_data_offload/fifo_dst_rlast
ad_connect fifo2axi_bridge/fifo_dst_ready i_data_offload/fifo_dst_ready ad_connect fifo2axi_bridge/fifo_dst_ready i_data_offload/fifo_dst_ready
} }