From c83239b0140c3c9ee0cc4fa63ee6141234069f31 Mon Sep 17 00:00:00 2001 From: Istvan Csomortani Date: Fri, 9 Oct 2015 13:19:09 +0300 Subject: [PATCH] fmcomms2/zc706pr: Update PR design + Add system_top.v to design + Add pr specific constraints --- projects/fmcomms2/zc706pr/system_bd.tcl | 1 + projects/fmcomms2/zc706pr/system_constr.xdc | 44 +++ projects/fmcomms2/zc706pr/system_project.tcl | 11 +- projects/fmcomms2/zc706pr/system_top.v | 343 +++++++++++++++++++ projects/scripts/adi_project.tcl | 1 + 5 files changed, 395 insertions(+), 5 deletions(-) create mode 100644 projects/fmcomms2/zc706pr/system_constr.xdc create mode 100644 projects/fmcomms2/zc706pr/system_top.v diff --git a/projects/fmcomms2/zc706pr/system_bd.tcl b/projects/fmcomms2/zc706pr/system_bd.tcl index 07554df73..e4f0c9a3f 100755 --- a/projects/fmcomms2/zc706pr/system_bd.tcl +++ b/projects/fmcomms2/zc706pr/system_bd.tcl @@ -1,3 +1,4 @@ source ../zc706/system_bd.tcl +source ../common/prcfg_bd.tcl diff --git a/projects/fmcomms2/zc706pr/system_constr.xdc b/projects/fmcomms2/zc706pr/system_constr.xdc new file mode 100644 index 000000000..53377ada7 --- /dev/null +++ b/projects/fmcomms2/zc706pr/system_constr.xdc @@ -0,0 +1,44 @@ + +set_false_path -from [get_cells -hierarchical -filter {name =~ i_prcfg* && IS_SEQUENTIAL}] \ + -to [get_cells -hierarchical -filter {name =~ i_system* && IS_SEQUENTIAL}] +set_false_path -from [get_cells -hierarchical -filter {name =~ i_system* && IS_SEQUENTIAL}] \ + -to [get_cells -hierarchical -filter {name =~ i_prcfg* && IS_SEQUENTIAL}] + +set_false_path -from [get_cells -hierarchical -filter {name =~ i_prcfg* && IS_SEQUENTIAL}] \ + -to [get_cells -hierarchical -filter {name =~ i_prcfg*i_pn_mon* && IS_SEQUENTIAL}] + +set_false_path -from [get_cells -hierarchical -filter {name =~ i_prcfg*input_pipeline_phase* && IS_SEQUENTIAL}] \ + -to [get_cells -hierarchical -filter {name =~ i_prcfg*ddata_reg* && IS_SEQUENTIAL}] + +set_false_path -from [get_cells -hierarchical -filter {name =~ i_prcfg*FIR_Decimation* && IS_SEQUENTIAL}] \ + -to [get_cells -hierarchical -filter {name =~ i_prcfg*dst_adc_ddata_reg*}] +set_false_path -from [get_cells -hierarchical -filter {name =~ i_prcfg*FIR_Interpolation* && IS_SEQUENTIAL}] \ + -to [get_cells -hierarchical -filter {name =~ i_prcfg*dst_dac_ddata_reg*}] + +set_false_path -from [get_cells -hierarchical -filter {name =~ i_prcfg*FIR_Decimation*}] \ + -to [get_cells -hierarchical -filter {name =~ i_prcfg*FIR_Decimation*regout_re_reg* && IS_SEQUENTIAL}] +set_false_path -from [get_cells -hierarchical -filter {name =~ i_prcfg*FIR_Decimation*}] \ + -to [get_cells -hierarchical -filter {name =~ i_prcfg*FIR_Decimation*regout_im_reg* && IS_SEQUENTIAL}] + +set_false_path -from [get_cells -hierarchical -filter {name =~ i_prcfg*FIR_Interpolation*cur_count_reg*}] \ + -to [get_cells -hierarchical -filter {name =~ i_prcfg*FIR_Interpolation*regout_re_reg* && IS_SEQUENTIAL}] +set_false_path -from [get_cells -hierarchical -filter {name =~ i_prcfg*FIR_Interpolation*cur_count_reg*}] \ + -to [get_cells -hierarchical -filter {name =~ i_prcfg*FIR_Interpolation*regout_im_reg* && IS_SEQUENTIAL}] + +set_false_path -from [get_cells -hierarchical -filter {name =~ i_prcfg*prcfg_dac*mode_reg*}] \ + -to [get_cells -hierarchical -filter {name =~ i_prcfg*FIR_Interpolation* && IS_SEQUENTIAL}] +set_false_path -from [get_cells -hierarchical -filter {name =~ i_prcfg*prcfg_dac*mode_reg*}] \ + -to [get_cells -hierarchical -filter {name =~ i_prcfg*dst_dac_ddata_reg* && IS_SEQUENTIAL}] + +set_false_path -from [get_cells -hierarchical -filter {name =~ i_prcfg*pn_data_reg*}] \ + -to [get_cells -hierarchical -filter {name =~ i_prcfg*FIR_Interpolation*regout_re_reg* && IS_SEQUENTIAL}] +set_false_path -from [get_cells -hierarchical -filter {name =~ i_prcfg*pn_data_reg*}] \ + -to [get_cells -hierarchical -filter {name =~ i_prcfg*FIR_Interpolation*regout_im_reg* && IS_SEQUENTIAL}] +set_false_path -from [get_cells -hierarchical -filter {name =~ i_prcfg*pn_data_reg*}] \ + -to [get_cells -hierarchical -filter {name =~ i_prcfg*dst_dac_ddata_reg* && IS_SEQUENTIAL}] + +set_false_path -from [get_cells -hierarchical -filter {name =~ i_prcfg*FIR_Interpolation*delay_pipeline_re_reg*}] \ + -to [get_cells -hierarchical -filter {name =~ i_prcfg*FIR_Interpolation*regout_re_reg* && IS_SEQUENTIAL}] +set_false_path -from [get_cells -hierarchical -filter {name =~ i_prcfg*FIR_Interpolation*delay_pipeline_im_reg*}] \ + -to [get_cells -hierarchical -filter {name =~ i_prcfg*FIR_Interpolation*regout_im_reg* && IS_SEQUENTIAL}] + diff --git a/projects/fmcomms2/zc706pr/system_project.tcl b/projects/fmcomms2/zc706pr/system_project.tcl index c7a4ba723..b781c51c6 100755 --- a/projects/fmcomms2/zc706pr/system_project.tcl +++ b/projects/fmcomms2/zc706pr/system_project.tcl @@ -7,7 +7,7 @@ source $ad_hdl_dir/projects/scripts/adi_board.tcl adi_project_create fmcomms2_zc706 1 adi_project_synth fmcomms2_zc706 "" \ - [list "../zc706/system_top.v" \ + [list "system_top.v" \ "$ad_hdl_dir/library/prcfg/common/prcfg_bb.v" \ "$ad_hdl_dir/library/common/ad_iobuf.v"] \ [list "../zc706/system_constr.xdc" \ @@ -18,7 +18,9 @@ adi_project_synth fmcomms2_zc706 "default" \ "$ad_hdl_dir/library/prcfg/common/prcfg_top.v" \ "$ad_hdl_dir/library/prcfg/default/prcfg_dac.v" \ "$ad_hdl_dir/library/prcfg/default/prcfg_adc.v"] -adi_project_impl fmcomms2_zc706 "default" "../common/prcfg.xdc" +adi_project_impl fmcomms2_zc706 "default" \ + [list "../common/prcfg.xdc" \ + "system_constr.xdc"] adi_project_synth fmcomms2_zc706 "bist" \ [list "../common/prcfg.v" \ @@ -26,7 +28,7 @@ adi_project_synth fmcomms2_zc706 "bist" \ "$ad_hdl_dir/library/common/ad_pnmon.v" \ "$ad_hdl_dir/library/prcfg/bist/prcfg_dac.v" \ "$ad_hdl_dir/library/prcfg/bist/prcfg_adc.v"] -adi_project_impl fmcomms2_zc706 "bist" +adi_project_impl fmcomms2_zc706 "bist" "system_constr.xdc" adi_project_synth fmcomms2_zc706 "qpsk" \ [list "../common/prcfg.v" \ @@ -42,8 +44,7 @@ adi_project_synth fmcomms2_zc706 "qpsk" \ "$ad_hdl_dir/library/prcfg/qpsk/FIR_Decimation.v" \ "$ad_hdl_dir/library/prcfg/qpsk/Raised_Cosine_Transmit_Filter.v" \ "$ad_hdl_dir/library/prcfg/qpsk/Raised_Cosine_Receive_Filter.v"] -adi_project_impl fmcomms2_zc706 "qpsk" +adi_project_impl fmcomms2_zc706 "qpsk" "system_constr.xdc" adi_project_verify fmcomms2_zc706 - diff --git a/projects/fmcomms2/zc706pr/system_top.v b/projects/fmcomms2/zc706pr/system_top.v new file mode 100644 index 000000000..57d44b383 --- /dev/null +++ b/projects/fmcomms2/zc706pr/system_top.v @@ -0,0 +1,343 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2011(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module system_top ( + + ddr_addr, + ddr_ba, + ddr_cas_n, + ddr_ck_n, + ddr_ck_p, + ddr_cke, + ddr_cs_n, + ddr_dm, + ddr_dq, + ddr_dqs_n, + ddr_dqs_p, + ddr_odt, + ddr_ras_n, + ddr_reset_n, + ddr_we_n, + + fixed_io_ddr_vrn, + fixed_io_ddr_vrp, + fixed_io_mio, + fixed_io_ps_clk, + fixed_io_ps_porb, + fixed_io_ps_srstb, + + gpio_bd, + + hdmi_out_clk, + hdmi_vsync, + hdmi_hsync, + hdmi_data_e, + hdmi_data, + + spdif, + + iic_scl, + iic_sda, + + rx_clk_in_p, + rx_clk_in_n, + rx_frame_in_p, + rx_frame_in_n, + rx_data_in_p, + rx_data_in_n, + tx_clk_out_p, + tx_clk_out_n, + tx_frame_out_p, + tx_frame_out_n, + tx_data_out_p, + tx_data_out_n, + + gpio_txnrx, + gpio_enable, + gpio_resetb, + gpio_sync, + gpio_en_agc, + gpio_ctl, + gpio_status, + + spi_csn, + spi_clk, + spi_mosi, + spi_miso); + + inout [14:0] ddr_addr; + inout [ 2:0] ddr_ba; + inout ddr_cas_n; + inout ddr_ck_n; + inout ddr_ck_p; + inout ddr_cke; + inout ddr_cs_n; + inout [ 3:0] ddr_dm; + inout [31:0] ddr_dq; + inout [ 3:0] ddr_dqs_n; + inout [ 3:0] ddr_dqs_p; + inout ddr_odt; + inout ddr_ras_n; + inout ddr_reset_n; + inout ddr_we_n; + + inout fixed_io_ddr_vrn; + inout fixed_io_ddr_vrp; + inout [53:0] fixed_io_mio; + inout fixed_io_ps_clk; + inout fixed_io_ps_porb; + inout fixed_io_ps_srstb; + + inout [14:0] gpio_bd; + + output hdmi_out_clk; + output hdmi_vsync; + output hdmi_hsync; + output hdmi_data_e; + output [23:0] hdmi_data; + + output spdif; + + inout iic_scl; + inout iic_sda; + + input rx_clk_in_p; + input rx_clk_in_n; + input rx_frame_in_p; + input rx_frame_in_n; + input [ 5:0] rx_data_in_p; + input [ 5:0] rx_data_in_n; + output tx_clk_out_p; + output tx_clk_out_n; + output tx_frame_out_p; + output tx_frame_out_n; + output [ 5:0] tx_data_out_p; + output [ 5:0] tx_data_out_n; + + inout gpio_txnrx; + inout gpio_enable; + inout gpio_resetb; + inout gpio_sync; + inout gpio_en_agc; + inout [ 3:0] gpio_ctl; + inout [ 7:0] gpio_status; + + output spi_csn; + output spi_clk; + output spi_mosi; + input spi_miso; + + // internal signals + + wire [63:0] gpio_i; + wire [63:0] gpio_o; + wire [63:0] gpio_t; + + wire clk; + wire dma_dac_dunf; + wire core_dac_dunf; + wire [63:0] dma_dac_ddata; + wire [63:0] core_dac_ddata; + wire dma_dac_en; + wire core_dac_en; + wire dma_dac_dvalid; + wire core_dac_dvalid; + + wire dma_adc_ovf; + wire core_adc_ovf; + wire [63:0] dma_adc_ddata; + wire [63:0] core_adc_ddata; + wire dma_adc_dwr; + wire core_adc_dwr; + wire dma_adc_dsync; + wire core_adc_dsync; + wire [31:0] adc_gpio_input; + wire [31:0] adc_gpio_output; + wire [31:0] dac_gpio_input; + wire [31:0] dac_gpio_output; + wire tdd_sync_t; + wire tdd_sync_o; + wire tdd_sync_i; + + // instantiations + + ad_iobuf #(.DATA_WIDTH(17)) i_iobuf ( + .dio_t ({gpio_t[50:49], gpio_t[46:32]}), + .dio_i ({gpio_o[50:49], gpio_o[46:32]}), + .dio_o ({gpio_i[50:49], gpio_i[46:32]}), + .dio_p ({ gpio_muxout_tx, // 50:50 + gpio_muxout_rx, // 49:49 + gpio_resetb, // 46:46 + gpio_sync, // 45:45 + gpio_en_agc, // 44:44 + gpio_ctl, // 43:40 + gpio_status})); // 39:32 + + ad_iobuf #(.DATA_WIDTH(15)) i_iobuf_bd ( + .dio_t (gpio_t[14:0]), + .dio_i (gpio_o[14:0]), + .dio_o (gpio_i[14:0]), + .dio_p (gpio_bd)); + + ad_iobuf #(.DATA_WIDTH(1)) i_iobuf_tdd_sync ( + .dio_t (tdd_sync_t), + .dio_i (tdd_sync_o), + .dio_o (tdd_sync_i), + .dio_p (tdd_sync)); + + // prcfg instance + prcfg i_prcfg ( + .clk(clk), + .adc_gpio_input(adc_gpio_input), + .adc_gpio_output(adc_gpio_output), + .dac_gpio_input(dac_gpio_input), + .dac_gpio_output(dac_gpio_output), + .dma_dac_en(dma_dac_en), + .dma_dac_dunf(dma_dac_dunf), + .dma_dac_ddata(dma_dac_ddata), + .dma_dac_dvalid(dma_dac_dvalid), + .core_dac_en(core_dac_en), + .core_dac_dunf(core_dac_dunf), + .core_dac_ddata(core_dac_ddata), + .core_dac_dvalid(core_dac_dvalid), + .core_adc_dwr(core_adc_dwr), + .core_adc_dsync(core_adc_dsync), + .core_adc_ddata(core_adc_ddata), + .core_adc_ovf(core_adc_ovf), + .dma_adc_dwr(dma_adc_dwr), + .dma_adc_dsync(dma_adc_dsync), + .dma_adc_ddata(dma_adc_ddata), + .dma_adc_ovf(dma_adc_ovf)); + + system_wrapper i_system_wrapper ( + .ddr_addr (ddr_addr), + .ddr_ba (ddr_ba), + .ddr_cas_n (ddr_cas_n), + .ddr_ck_n (ddr_ck_n), + .ddr_ck_p (ddr_ck_p), + .ddr_cke (ddr_cke), + .ddr_cs_n (ddr_cs_n), + .ddr_dm (ddr_dm), + .ddr_dq (ddr_dq), + .ddr_dqs_n (ddr_dqs_n), + .ddr_dqs_p (ddr_dqs_p), + .ddr_odt (ddr_odt), + .ddr_ras_n (ddr_ras_n), + .ddr_reset_n (ddr_reset_n), + .ddr_we_n (ddr_we_n), + .enable (enable), + .fixed_io_ddr_vrn (fixed_io_ddr_vrn), + .fixed_io_ddr_vrp (fixed_io_ddr_vrp), + .fixed_io_mio (fixed_io_mio), + .fixed_io_ps_clk (fixed_io_ps_clk), + .fixed_io_ps_porb (fixed_io_ps_porb), + .fixed_io_ps_srstb (fixed_io_ps_srstb), + .gpio_i (gpio_i), + .gpio_o (gpio_o), + .gpio_t (gpio_t), + .hdmi_data (hdmi_data), + .hdmi_data_e (hdmi_data_e), + .hdmi_hsync (hdmi_hsync), + .hdmi_out_clk (hdmi_out_clk), + .hdmi_vsync (hdmi_vsync), + .iic_main_scl_io (iic_scl), + .iic_main_sda_io (iic_sda), + .ps_intr_00 (1'b0), + .ps_intr_01 (1'b0), + .ps_intr_02 (1'b0), + .ps_intr_03 (1'b0), + .ps_intr_04 (1'b0), + .ps_intr_05 (1'b0), + .ps_intr_06 (1'b0), + .ps_intr_07 (1'b0), + .ps_intr_08 (1'b0), + .ps_intr_09 (1'b0), + .ps_intr_10 (1'b0), + .ps_intr_11 (1'b0), + .rx_clk_in_n (rx_clk_in_n), + .rx_clk_in_p (rx_clk_in_p), + .rx_data_in_n (rx_data_in_n), + .rx_data_in_p (rx_data_in_p), + .rx_frame_in_n (rx_frame_in_n), + .rx_frame_in_p (rx_frame_in_p), + .spdif (spdif), + .spi0_clk_i (1'b0), + .spi0_clk_o (spi_clk), + .spi0_csn_0_o (spi_csn), + .spi0_csn_1_o (), + .spi0_csn_2_o (), + .spi0_csn_i (1'b1), + .spi0_sdi_i (spi_miso), + .spi0_sdo_i (1'b0), + .spi0_sdo_o (spi_mosi), + + .tx_clk_out_n (tx_clk_out_n), + .tx_clk_out_p (tx_clk_out_p), + .tx_data_out_n (tx_data_out_n), + .tx_data_out_p (tx_data_out_p), + .tx_frame_out_n (tx_frame_out_n), + .tx_frame_out_p (tx_frame_out_p), + // pr related ports + .clk(clk), + .dma_dac_en(dma_dac_en), + .dma_dac_dunf(dma_dac_dunf), + .dma_dac_ddata(dma_dac_ddata), + .dma_dac_dvalid(dma_dac_dvalid), + .core_dac_en(core_dac_en), + .core_dac_dunf(core_dac_dunf), + .core_dac_ddata(core_dac_ddata), + .core_dac_dvalid(core_dac_dvalid), + .core_adc_dwr(core_adc_dwr), + .core_adc_dsync(core_adc_dsync), + .core_adc_ddata(core_adc_ddata), + .core_adc_ovf(core_adc_ovf), + .dma_adc_dwr(dma_adc_dwr), + .dma_adc_dsync(dma_adc_dsync), + .dma_adc_ddata(dma_adc_ddata), + .dma_adc_ovf(dma_adc_ovf), + .up_dac_gpio_in(dac_gpio_output), + .up_adc_gpio_in(adc_gpio_output), + .up_dac_gpio_out(dac_gpio_input), + .up_adc_gpio_out(adc_gpio_input) + ); + +endmodule + +// *************************************************************************** +// *************************************************************************** diff --git a/projects/scripts/adi_project.tcl b/projects/scripts/adi_project.tcl index 4f7b3c2f9..c1270a920 100644 --- a/projects/scripts/adi_project.tcl +++ b/projects/scripts/adi_project.tcl @@ -226,6 +226,7 @@ proc adi_project_impl {project_name prcfg_name {xdc_files ""}} { open_checkpoint $p_prefix.default_impl_bb.dcp -part $p_device lock_design -level routing read_checkpoint -cell i_prcfg $p_prefix.${prcfg_name}_synth.dcp + read_xdc $xdc_files opt_design > $p_prefix.${prcfg_name}_opt.rds place_design > $p_prefix.${prcfg_name}_place.rds route_design > $p_prefix.${prcfg_name}_route.rds