fmcomms2/zc706pr: Update PR design
+ Add system_top.v to design + Add pr specific constraintsmain
Istvan Csomortani
parent
df8ac2e726
commit
c83239b014
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@ -1,3 +1,4 @@
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source ../zc706/system_bd.tcl
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source ../common/prcfg_bd.tcl
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@ -0,0 +1,44 @@
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set_false_path -from [get_cells -hierarchical -filter {name =~ i_prcfg* && IS_SEQUENTIAL}] \
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-to [get_cells -hierarchical -filter {name =~ i_system* && IS_SEQUENTIAL}]
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set_false_path -from [get_cells -hierarchical -filter {name =~ i_system* && IS_SEQUENTIAL}] \
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-to [get_cells -hierarchical -filter {name =~ i_prcfg* && IS_SEQUENTIAL}]
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set_false_path -from [get_cells -hierarchical -filter {name =~ i_prcfg* && IS_SEQUENTIAL}] \
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-to [get_cells -hierarchical -filter {name =~ i_prcfg*i_pn_mon* && IS_SEQUENTIAL}]
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set_false_path -from [get_cells -hierarchical -filter {name =~ i_prcfg*input_pipeline_phase* && IS_SEQUENTIAL}] \
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-to [get_cells -hierarchical -filter {name =~ i_prcfg*ddata_reg* && IS_SEQUENTIAL}]
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set_false_path -from [get_cells -hierarchical -filter {name =~ i_prcfg*FIR_Decimation* && IS_SEQUENTIAL}] \
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-to [get_cells -hierarchical -filter {name =~ i_prcfg*dst_adc_ddata_reg*}]
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set_false_path -from [get_cells -hierarchical -filter {name =~ i_prcfg*FIR_Interpolation* && IS_SEQUENTIAL}] \
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-to [get_cells -hierarchical -filter {name =~ i_prcfg*dst_dac_ddata_reg*}]
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set_false_path -from [get_cells -hierarchical -filter {name =~ i_prcfg*FIR_Decimation*}] \
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-to [get_cells -hierarchical -filter {name =~ i_prcfg*FIR_Decimation*regout_re_reg* && IS_SEQUENTIAL}]
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set_false_path -from [get_cells -hierarchical -filter {name =~ i_prcfg*FIR_Decimation*}] \
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-to [get_cells -hierarchical -filter {name =~ i_prcfg*FIR_Decimation*regout_im_reg* && IS_SEQUENTIAL}]
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set_false_path -from [get_cells -hierarchical -filter {name =~ i_prcfg*FIR_Interpolation*cur_count_reg*}] \
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-to [get_cells -hierarchical -filter {name =~ i_prcfg*FIR_Interpolation*regout_re_reg* && IS_SEQUENTIAL}]
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set_false_path -from [get_cells -hierarchical -filter {name =~ i_prcfg*FIR_Interpolation*cur_count_reg*}] \
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-to [get_cells -hierarchical -filter {name =~ i_prcfg*FIR_Interpolation*regout_im_reg* && IS_SEQUENTIAL}]
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set_false_path -from [get_cells -hierarchical -filter {name =~ i_prcfg*prcfg_dac*mode_reg*}] \
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-to [get_cells -hierarchical -filter {name =~ i_prcfg*FIR_Interpolation* && IS_SEQUENTIAL}]
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set_false_path -from [get_cells -hierarchical -filter {name =~ i_prcfg*prcfg_dac*mode_reg*}] \
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-to [get_cells -hierarchical -filter {name =~ i_prcfg*dst_dac_ddata_reg* && IS_SEQUENTIAL}]
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set_false_path -from [get_cells -hierarchical -filter {name =~ i_prcfg*pn_data_reg*}] \
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-to [get_cells -hierarchical -filter {name =~ i_prcfg*FIR_Interpolation*regout_re_reg* && IS_SEQUENTIAL}]
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set_false_path -from [get_cells -hierarchical -filter {name =~ i_prcfg*pn_data_reg*}] \
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-to [get_cells -hierarchical -filter {name =~ i_prcfg*FIR_Interpolation*regout_im_reg* && IS_SEQUENTIAL}]
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set_false_path -from [get_cells -hierarchical -filter {name =~ i_prcfg*pn_data_reg*}] \
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-to [get_cells -hierarchical -filter {name =~ i_prcfg*dst_dac_ddata_reg* && IS_SEQUENTIAL}]
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set_false_path -from [get_cells -hierarchical -filter {name =~ i_prcfg*FIR_Interpolation*delay_pipeline_re_reg*}] \
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-to [get_cells -hierarchical -filter {name =~ i_prcfg*FIR_Interpolation*regout_re_reg* && IS_SEQUENTIAL}]
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set_false_path -from [get_cells -hierarchical -filter {name =~ i_prcfg*FIR_Interpolation*delay_pipeline_im_reg*}] \
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-to [get_cells -hierarchical -filter {name =~ i_prcfg*FIR_Interpolation*regout_im_reg* && IS_SEQUENTIAL}]
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@ -7,7 +7,7 @@ source $ad_hdl_dir/projects/scripts/adi_board.tcl
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adi_project_create fmcomms2_zc706 1
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adi_project_synth fmcomms2_zc706 "" \
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[list "../zc706/system_top.v" \
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[list "system_top.v" \
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"$ad_hdl_dir/library/prcfg/common/prcfg_bb.v" \
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"$ad_hdl_dir/library/common/ad_iobuf.v"] \
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[list "../zc706/system_constr.xdc" \
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@ -18,7 +18,9 @@ adi_project_synth fmcomms2_zc706 "default" \
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"$ad_hdl_dir/library/prcfg/common/prcfg_top.v" \
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"$ad_hdl_dir/library/prcfg/default/prcfg_dac.v" \
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"$ad_hdl_dir/library/prcfg/default/prcfg_adc.v"]
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adi_project_impl fmcomms2_zc706 "default" "../common/prcfg.xdc"
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adi_project_impl fmcomms2_zc706 "default" \
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[list "../common/prcfg.xdc" \
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"system_constr.xdc"]
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adi_project_synth fmcomms2_zc706 "bist" \
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[list "../common/prcfg.v" \
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@ -26,7 +28,7 @@ adi_project_synth fmcomms2_zc706 "bist" \
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"$ad_hdl_dir/library/common/ad_pnmon.v" \
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"$ad_hdl_dir/library/prcfg/bist/prcfg_dac.v" \
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"$ad_hdl_dir/library/prcfg/bist/prcfg_adc.v"]
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adi_project_impl fmcomms2_zc706 "bist"
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adi_project_impl fmcomms2_zc706 "bist" "system_constr.xdc"
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adi_project_synth fmcomms2_zc706 "qpsk" \
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[list "../common/prcfg.v" \
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@ -42,8 +44,7 @@ adi_project_synth fmcomms2_zc706 "qpsk" \
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"$ad_hdl_dir/library/prcfg/qpsk/FIR_Decimation.v" \
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"$ad_hdl_dir/library/prcfg/qpsk/Raised_Cosine_Transmit_Filter.v" \
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"$ad_hdl_dir/library/prcfg/qpsk/Raised_Cosine_Receive_Filter.v"]
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adi_project_impl fmcomms2_zc706 "qpsk"
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adi_project_impl fmcomms2_zc706 "qpsk" "system_constr.xdc"
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adi_project_verify fmcomms2_zc706
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@ -0,0 +1,343 @@
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// ***************************************************************************
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// ***************************************************************************
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// Copyright 2011(c) Analog Devices, Inc.
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//
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without modification,
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// are permitted provided that the following conditions are met:
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// - Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// - Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in
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// the documentation and/or other materials provided with the
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// distribution.
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// - Neither the name of Analog Devices, Inc. nor the names of its
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// contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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// - The use of this software may or may not infringe the patent rights
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// of one or more patent holders. This license does not release you
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// from the requirement that you obtain separate licenses from these
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// patent holders to use this software.
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// - Use of the software either in source or binary form, must be run
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// on or directly connected to an Analog Devices Inc. component.
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//
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// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
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// PARTICULAR PURPOSE ARE DISCLAIMED.
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//
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// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
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// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module system_top (
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ddr_addr,
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ddr_ba,
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ddr_cas_n,
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ddr_ck_n,
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ddr_ck_p,
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ddr_cke,
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ddr_cs_n,
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ddr_dm,
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ddr_dq,
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ddr_dqs_n,
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ddr_dqs_p,
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ddr_odt,
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ddr_ras_n,
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ddr_reset_n,
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ddr_we_n,
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fixed_io_ddr_vrn,
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fixed_io_ddr_vrp,
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fixed_io_mio,
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fixed_io_ps_clk,
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fixed_io_ps_porb,
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fixed_io_ps_srstb,
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gpio_bd,
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hdmi_out_clk,
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hdmi_vsync,
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hdmi_hsync,
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hdmi_data_e,
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hdmi_data,
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spdif,
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iic_scl,
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iic_sda,
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rx_clk_in_p,
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rx_clk_in_n,
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rx_frame_in_p,
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rx_frame_in_n,
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rx_data_in_p,
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rx_data_in_n,
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tx_clk_out_p,
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tx_clk_out_n,
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tx_frame_out_p,
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tx_frame_out_n,
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tx_data_out_p,
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tx_data_out_n,
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gpio_txnrx,
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gpio_enable,
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gpio_resetb,
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gpio_sync,
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gpio_en_agc,
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gpio_ctl,
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gpio_status,
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spi_csn,
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spi_clk,
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spi_mosi,
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spi_miso);
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inout [14:0] ddr_addr;
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inout [ 2:0] ddr_ba;
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inout ddr_cas_n;
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inout ddr_ck_n;
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inout ddr_ck_p;
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inout ddr_cke;
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inout ddr_cs_n;
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inout [ 3:0] ddr_dm;
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inout [31:0] ddr_dq;
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inout [ 3:0] ddr_dqs_n;
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inout [ 3:0] ddr_dqs_p;
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inout ddr_odt;
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inout ddr_ras_n;
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inout ddr_reset_n;
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inout ddr_we_n;
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inout fixed_io_ddr_vrn;
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inout fixed_io_ddr_vrp;
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inout [53:0] fixed_io_mio;
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inout fixed_io_ps_clk;
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inout fixed_io_ps_porb;
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inout fixed_io_ps_srstb;
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inout [14:0] gpio_bd;
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output hdmi_out_clk;
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output hdmi_vsync;
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output hdmi_hsync;
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output hdmi_data_e;
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output [23:0] hdmi_data;
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output spdif;
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inout iic_scl;
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inout iic_sda;
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input rx_clk_in_p;
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input rx_clk_in_n;
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input rx_frame_in_p;
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input rx_frame_in_n;
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input [ 5:0] rx_data_in_p;
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input [ 5:0] rx_data_in_n;
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output tx_clk_out_p;
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output tx_clk_out_n;
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output tx_frame_out_p;
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output tx_frame_out_n;
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output [ 5:0] tx_data_out_p;
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output [ 5:0] tx_data_out_n;
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inout gpio_txnrx;
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inout gpio_enable;
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inout gpio_resetb;
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inout gpio_sync;
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inout gpio_en_agc;
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inout [ 3:0] gpio_ctl;
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inout [ 7:0] gpio_status;
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output spi_csn;
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output spi_clk;
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output spi_mosi;
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input spi_miso;
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// internal signals
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wire [63:0] gpio_i;
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wire [63:0] gpio_o;
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wire [63:0] gpio_t;
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wire clk;
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wire dma_dac_dunf;
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wire core_dac_dunf;
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wire [63:0] dma_dac_ddata;
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wire [63:0] core_dac_ddata;
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wire dma_dac_en;
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wire core_dac_en;
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wire dma_dac_dvalid;
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wire core_dac_dvalid;
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wire dma_adc_ovf;
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wire core_adc_ovf;
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wire [63:0] dma_adc_ddata;
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wire [63:0] core_adc_ddata;
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wire dma_adc_dwr;
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wire core_adc_dwr;
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wire dma_adc_dsync;
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wire core_adc_dsync;
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wire [31:0] adc_gpio_input;
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wire [31:0] adc_gpio_output;
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wire [31:0] dac_gpio_input;
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wire [31:0] dac_gpio_output;
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wire tdd_sync_t;
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wire tdd_sync_o;
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wire tdd_sync_i;
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// instantiations
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ad_iobuf #(.DATA_WIDTH(17)) i_iobuf (
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.dio_t ({gpio_t[50:49], gpio_t[46:32]}),
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.dio_i ({gpio_o[50:49], gpio_o[46:32]}),
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.dio_o ({gpio_i[50:49], gpio_i[46:32]}),
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.dio_p ({ gpio_muxout_tx, // 50:50
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gpio_muxout_rx, // 49:49
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gpio_resetb, // 46:46
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gpio_sync, // 45:45
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gpio_en_agc, // 44:44
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gpio_ctl, // 43:40
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gpio_status})); // 39:32
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ad_iobuf #(.DATA_WIDTH(15)) i_iobuf_bd (
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.dio_t (gpio_t[14:0]),
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.dio_i (gpio_o[14:0]),
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.dio_o (gpio_i[14:0]),
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.dio_p (gpio_bd));
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ad_iobuf #(.DATA_WIDTH(1)) i_iobuf_tdd_sync (
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.dio_t (tdd_sync_t),
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.dio_i (tdd_sync_o),
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.dio_o (tdd_sync_i),
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.dio_p (tdd_sync));
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// prcfg instance
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prcfg i_prcfg (
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.clk(clk),
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.adc_gpio_input(adc_gpio_input),
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.adc_gpio_output(adc_gpio_output),
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.dac_gpio_input(dac_gpio_input),
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.dac_gpio_output(dac_gpio_output),
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.dma_dac_en(dma_dac_en),
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.dma_dac_dunf(dma_dac_dunf),
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.dma_dac_ddata(dma_dac_ddata),
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.dma_dac_dvalid(dma_dac_dvalid),
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.core_dac_en(core_dac_en),
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.core_dac_dunf(core_dac_dunf),
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.core_dac_ddata(core_dac_ddata),
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.core_dac_dvalid(core_dac_dvalid),
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.core_adc_dwr(core_adc_dwr),
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.core_adc_dsync(core_adc_dsync),
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.core_adc_ddata(core_adc_ddata),
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.core_adc_ovf(core_adc_ovf),
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.dma_adc_dwr(dma_adc_dwr),
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.dma_adc_dsync(dma_adc_dsync),
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.dma_adc_ddata(dma_adc_ddata),
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.dma_adc_ovf(dma_adc_ovf));
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system_wrapper i_system_wrapper (
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.ddr_addr (ddr_addr),
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.ddr_ba (ddr_ba),
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.ddr_cas_n (ddr_cas_n),
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.ddr_ck_n (ddr_ck_n),
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.ddr_ck_p (ddr_ck_p),
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.ddr_cke (ddr_cke),
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.ddr_cs_n (ddr_cs_n),
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.ddr_dm (ddr_dm),
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.ddr_dq (ddr_dq),
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.ddr_dqs_n (ddr_dqs_n),
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.ddr_dqs_p (ddr_dqs_p),
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.ddr_odt (ddr_odt),
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.ddr_ras_n (ddr_ras_n),
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.ddr_reset_n (ddr_reset_n),
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.ddr_we_n (ddr_we_n),
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.enable (enable),
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.fixed_io_ddr_vrn (fixed_io_ddr_vrn),
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.fixed_io_ddr_vrp (fixed_io_ddr_vrp),
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.fixed_io_mio (fixed_io_mio),
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.fixed_io_ps_clk (fixed_io_ps_clk),
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.fixed_io_ps_porb (fixed_io_ps_porb),
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.fixed_io_ps_srstb (fixed_io_ps_srstb),
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.gpio_i (gpio_i),
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.gpio_o (gpio_o),
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.gpio_t (gpio_t),
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.hdmi_data (hdmi_data),
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.hdmi_data_e (hdmi_data_e),
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.hdmi_hsync (hdmi_hsync),
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.hdmi_out_clk (hdmi_out_clk),
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.hdmi_vsync (hdmi_vsync),
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.iic_main_scl_io (iic_scl),
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.iic_main_sda_io (iic_sda),
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.ps_intr_00 (1'b0),
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.ps_intr_01 (1'b0),
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.ps_intr_02 (1'b0),
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.ps_intr_03 (1'b0),
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.ps_intr_04 (1'b0),
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.ps_intr_05 (1'b0),
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.ps_intr_06 (1'b0),
|
||||
.ps_intr_07 (1'b0),
|
||||
.ps_intr_08 (1'b0),
|
||||
.ps_intr_09 (1'b0),
|
||||
.ps_intr_10 (1'b0),
|
||||
.ps_intr_11 (1'b0),
|
||||
.rx_clk_in_n (rx_clk_in_n),
|
||||
.rx_clk_in_p (rx_clk_in_p),
|
||||
.rx_data_in_n (rx_data_in_n),
|
||||
.rx_data_in_p (rx_data_in_p),
|
||||
.rx_frame_in_n (rx_frame_in_n),
|
||||
.rx_frame_in_p (rx_frame_in_p),
|
||||
.spdif (spdif),
|
||||
.spi0_clk_i (1'b0),
|
||||
.spi0_clk_o (spi_clk),
|
||||
.spi0_csn_0_o (spi_csn),
|
||||
.spi0_csn_1_o (),
|
||||
.spi0_csn_2_o (),
|
||||
.spi0_csn_i (1'b1),
|
||||
.spi0_sdi_i (spi_miso),
|
||||
.spi0_sdo_i (1'b0),
|
||||
.spi0_sdo_o (spi_mosi),
|
||||
|
||||
.tx_clk_out_n (tx_clk_out_n),
|
||||
.tx_clk_out_p (tx_clk_out_p),
|
||||
.tx_data_out_n (tx_data_out_n),
|
||||
.tx_data_out_p (tx_data_out_p),
|
||||
.tx_frame_out_n (tx_frame_out_n),
|
||||
.tx_frame_out_p (tx_frame_out_p),
|
||||
// pr related ports
|
||||
.clk(clk),
|
||||
.dma_dac_en(dma_dac_en),
|
||||
.dma_dac_dunf(dma_dac_dunf),
|
||||
.dma_dac_ddata(dma_dac_ddata),
|
||||
.dma_dac_dvalid(dma_dac_dvalid),
|
||||
.core_dac_en(core_dac_en),
|
||||
.core_dac_dunf(core_dac_dunf),
|
||||
.core_dac_ddata(core_dac_ddata),
|
||||
.core_dac_dvalid(core_dac_dvalid),
|
||||
.core_adc_dwr(core_adc_dwr),
|
||||
.core_adc_dsync(core_adc_dsync),
|
||||
.core_adc_ddata(core_adc_ddata),
|
||||
.core_adc_ovf(core_adc_ovf),
|
||||
.dma_adc_dwr(dma_adc_dwr),
|
||||
.dma_adc_dsync(dma_adc_dsync),
|
||||
.dma_adc_ddata(dma_adc_ddata),
|
||||
.dma_adc_ovf(dma_adc_ovf),
|
||||
.up_dac_gpio_in(dac_gpio_output),
|
||||
.up_adc_gpio_in(adc_gpio_output),
|
||||
.up_dac_gpio_out(dac_gpio_input),
|
||||
.up_adc_gpio_out(adc_gpio_input)
|
||||
);
|
||||
|
||||
endmodule
|
||||
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
|
@ -226,6 +226,7 @@ proc adi_project_impl {project_name prcfg_name {xdc_files ""}} {
|
|||
open_checkpoint $p_prefix.default_impl_bb.dcp -part $p_device
|
||||
lock_design -level routing
|
||||
read_checkpoint -cell i_prcfg $p_prefix.${prcfg_name}_synth.dcp
|
||||
read_xdc $xdc_files
|
||||
opt_design > $p_prefix.${prcfg_name}_opt.rds
|
||||
place_design > $p_prefix.${prcfg_name}_place.rds
|
||||
route_design > $p_prefix.${prcfg_name}_route.rds
|
||||
|
|
|
|||
Loading…
Reference in New Issue