zcy
/
pluto_hdl_adi
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

ad7606x: Add dynamic configuration for AD7606X operation modes 

AD7606x operation mode configuration:
REG_CNTRL_3
bit 8 - 'b1 - set operation mode indicated in bits [7:0];
bit [7:0] - set desired operation mode: 0 - SIMPLE, 1 - CRC, 2 - STATUS_HEADER, 3 - CRC_STATUS
main
alin724 2023-03-08 13:44:03 +02:00 committed by Alin-Tudor Sferle
parent ae09b8a1bb
commit c8a131ec0a
8 changed files with 174 additions and 111 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

63
library/axi_ad7606x/axi_ad7606x.v
View File

@ -39,9 +39,8 @@ module axi_ad7606x #(
parameter ID = 0,
parameter DEV_CONFIG = 0,
parameter ADC_TO_DMA_N_BITS = 16,
parameter ADC_CH_DW = 16,
parameter ADC_N_BITS = 16,
parameter ADC_READ_MODE = 0,
parameter EXTERNAL_CLK = 0
) (
@ -88,14 +87,14 @@ module axi_ad7606x #(
output adc_clk,
output adc_valid,
output [ADC_TO_DMA_N_BITS-1:0] adc_data_0,
output [ADC_TO_DMA_N_BITS-1:0] adc_data_1,
output [ADC_TO_DMA_N_BITS-1:0] adc_data_2,
output [ADC_TO_DMA_N_BITS-1:0] adc_data_3,
output [ADC_TO_DMA_N_BITS-1:0] adc_data_4,
output [ADC_TO_DMA_N_BITS-1:0] adc_data_5,
output [ADC_TO_DMA_N_BITS-1:0] adc_data_6,
output [ADC_TO_DMA_N_BITS-1:0] adc_data_7,
output [ADC_CH_DW-1:0] adc_data_0,
output [ADC_CH_DW-1:0] adc_data_1,
output [ADC_CH_DW-1:0] adc_data_2,
output [ADC_CH_DW-1:0] adc_data_3,
output [ADC_CH_DW-1:0] adc_data_4,
output [ADC_CH_DW-1:0] adc_data_5,
output [ADC_CH_DW-1:0] adc_data_6,
output [ADC_CH_DW-1:0] adc_data_7,
output adc_enable_0,
output adc_enable_1,
output adc_enable_2,
@ -108,6 +107,8 @@ module axi_ad7606x #(
);
localparam [31:0] RD_RAW_CAP = 32'h2000;
localparam AD7606B = 1'b0;
localparam AD7606C_16 = 1'b1;
// internal registers
@ -134,6 +135,8 @@ module axi_ad7606x #(
wire [15:0] adc_crc;
wire [15:0] adc_crc_res;
wire adc_crc_err;
wire adc_mode_en;
wire [ 7:0] adc_custom_control;
wire adc_dfmt_enable_s[0:7];
wire adc_dfmt_type_s[0:7];
@ -143,7 +146,7 @@ module axi_ad7606x #(
wire [ 7:0] adc_enable;
wire adc_reset_s;
wire [(8*ADC_TO_DMA_N_BITS)-1:0] dma_data;
wire [(8*ADC_CH_DW)-1:0] dma_data;
wire dma_dvalid;
wire up_clk;
@ -284,13 +287,13 @@ module axi_ad7606x #(
for (k = 0;k < 8;k = k + 1) begin
ad_datafmt #(
.DATA_WIDTH (ADC_N_BITS),
.BITS_PER_SAMPLE (ADC_TO_DMA_N_BITS)
.BITS_PER_SAMPLE (ADC_CH_DW)
) i_datafmt (
.clk (adc_clk),
.valid (1'b1),
.data (adc_data_s[k*ADC_N_BITS+(ADC_N_BITS-1):k*ADC_N_BITS]),
.valid_out (dma_dvalid),
.data_out (dma_data[k*ADC_TO_DMA_N_BITS+(ADC_TO_DMA_N_BITS-1):k*ADC_TO_DMA_N_BITS]),
.data_out (dma_data[k*ADC_CH_DW+(ADC_CH_DW-1):k*ADC_CH_DW]),
.dfmt_enable (adc_dfmt_enable_s[k]),
.dfmt_type (adc_dfmt_type_s[k]),
.dfmt_se (adc_dfmt_se_s[k]));
@ -298,10 +301,8 @@ module axi_ad7606x #(
endgenerate
generate
if (DEV_CONFIG == 0 || DEV_CONFIG == 1) begin
axi_ad7606x_16b_pif #(
.ADC_READ_MODE (ADC_READ_MODE)
) i_ad7606_parallel_interface (
if (DEV_CONFIG == AD7606B || DEV_CONFIG == AD7606C_16) begin
axi_ad7606x_16b_pif i_ad7606_parallel_interface (
.cs_n (rx_cs_n),
.db_o (rx_db_o),
.db_i (rx_db_i),
@ -335,13 +336,13 @@ module axi_ad7606x #(
.rstn (up_rstn),
.adc_config_ctrl (adc_config_ctrl_s),
.adc_ctrl_status (adc_ctrl_status_s),
.adc_mode_en (adc_mode_en),
.adc_custom_control (adc_custom_control),
.wr_data (wr_data_s[15:0]),
.rd_data (rd_data_s),
.rd_valid (rd_valid_s));
end else begin
axi_ad7606x_18b_pif #(
.ADC_READ_MODE (ADC_READ_MODE)
) i_ad7606_parallel_interface (
axi_ad7606x_18b_pif i_ad7606_parallel_interface (
.cs_n (rx_cs_n),
.db_o (rx_db_o),
.db_i (rx_db_i),
@ -375,6 +376,8 @@ module axi_ad7606x #(
.rstn (up_rstn),
.adc_config_ctrl (adc_config_ctrl_s),
.adc_ctrl_status (adc_ctrl_status_s),
.adc_mode_en (adc_mode_en),
.adc_custom_control (adc_custom_control),
.wr_data (wr_data_s[15:0]),
.rd_data (rd_data_s),
.rd_valid (rd_valid_s));
@ -382,14 +385,14 @@ module axi_ad7606x #(
endgenerate
assign adc_data_s = {adc_data_0_s,adc_data_1_s,adc_data_2_s,adc_data_3_s,adc_data_4_s,adc_data_5_s,adc_data_6_s,adc_data_7_s};
assign adc_data_7 = dma_data[0*ADC_TO_DMA_N_BITS+(ADC_TO_DMA_N_BITS-1):0*ADC_TO_DMA_N_BITS];
assign adc_data_6 = dma_data[1*ADC_TO_DMA_N_BITS+(ADC_TO_DMA_N_BITS-1):1*ADC_TO_DMA_N_BITS];
assign adc_data_5 = dma_data[2*ADC_TO_DMA_N_BITS+(ADC_TO_DMA_N_BITS-1):2*ADC_TO_DMA_N_BITS];
assign adc_data_4 = dma_data[3*ADC_TO_DMA_N_BITS+(ADC_TO_DMA_N_BITS-1):3*ADC_TO_DMA_N_BITS];
assign adc_data_3 = dma_data[4*ADC_TO_DMA_N_BITS+(ADC_TO_DMA_N_BITS-1):4*ADC_TO_DMA_N_BITS];
assign adc_data_2 = dma_data[5*ADC_TO_DMA_N_BITS+(ADC_TO_DMA_N_BITS-1):5*ADC_TO_DMA_N_BITS];
assign adc_data_1 = dma_data[6*ADC_TO_DMA_N_BITS+(ADC_TO_DMA_N_BITS-1):6*ADC_TO_DMA_N_BITS];
assign adc_data_0 = dma_data[7*ADC_TO_DMA_N_BITS+(ADC_TO_DMA_N_BITS-1):7*ADC_TO_DMA_N_BITS];
assign adc_data_7 = dma_data[0*ADC_CH_DW+(ADC_CH_DW-1):0*ADC_CH_DW];
assign adc_data_6 = dma_data[1*ADC_CH_DW+(ADC_CH_DW-1):1*ADC_CH_DW];
assign adc_data_5 = dma_data[2*ADC_CH_DW+(ADC_CH_DW-1):2*ADC_CH_DW];
assign adc_data_4 = dma_data[3*ADC_CH_DW+(ADC_CH_DW-1):3*ADC_CH_DW];
assign adc_data_3 = dma_data[4*ADC_CH_DW+(ADC_CH_DW-1):4*ADC_CH_DW];
assign adc_data_2 = dma_data[5*ADC_CH_DW+(ADC_CH_DW-1):5*ADC_CH_DW];
assign adc_data_1 = dma_data[6*ADC_CH_DW+(ADC_CH_DW-1):6*ADC_CH_DW];
assign adc_data_0 = dma_data[7*ADC_CH_DW+(ADC_CH_DW-1):7*ADC_CH_DW];
up_adc_common #(
.ID (ID),
@ -412,8 +415,8 @@ module axi_ad7606x #(
.adc_ext_sync_disarm (),
.adc_ext_sync_manual_req (),
.adc_num_lanes (),
.adc_custom_control (),
.adc_crc_enable (),
.adc_custom_control (adc_custom_control),
.adc_crc_enable (adc_mode_en),
.adc_sdr_ddr_n (),
.adc_symb_op (),
.adc_symb_8_16b (),

85
library/axi_ad7606x/axi_ad7606x_16b_pif.v
View File

@ -36,7 +36,6 @@
`timescale 1ns/100ps
module axi_ad7606x_16b_pif #(
parameter ADC_READ_MODE = 0,
parameter NEG_EDGE = 1,
parameter POS_EDGE = 0
) (
@ -71,8 +70,8 @@ module axi_ad7606x_16b_pif #(
output reg [15:0] adc_data_7,
output reg [ 7:0] adc_status_7 = 'h0,
output adc_status,
output reg [15:0] adc_crc = 'h0,
output reg [15:0] adc_crc_res = 'h0,
output [15:0] adc_crc,
output [15:0] adc_crc_res,
output adc_crc_err,
output reg adc_valid,
@ -83,6 +82,8 @@ module axi_ad7606x_16b_pif #(
input [31:0] adc_config_ctrl,
output adc_ctrl_status,
input [15:0] wr_data,
input adc_mode_en,
input [7:0] adc_custom_control,
output reg [15:0] rd_data = 'hf,
output reg rd_valid
);
@ -95,8 +96,8 @@ module axi_ad7606x_16b_pif #(
localparam [ 2:0] CNTRL_HIGH = 3'h3;
localparam [ 2:0] CS_HIGH = 3'h4;
localparam [ 1:0] SIMPLE = 0;
localparam [ 1:0] STATUS_HEADER = 1;
localparam [ 1:0] CRC_ENABLED = 2;
localparam [ 1:0] STATUS_HEADER = 2;
localparam [ 1:0] CRC_ENABLED = 1;
localparam [ 1:0] CRC_STATUS = 3;
// internal registers
@ -114,9 +115,16 @@ module axi_ad7606x_16b_pif #(
reg read_ch_data = 1'd0;
reg [ 7:0] adc_status_er_ch_id = 8'h0;
reg [15:0] adc_crc_r = 16'h0;
reg [15:0] adc_crc_res_r = 16'h0;
reg [ 1:0] adc_config_mode_r = 2'h0;
// internal wires
wire rd_req_s;
wire wr_req_s;
wire end_of_conv;
wire start_transfer_s;
wire rd_valid_s;
@ -124,6 +132,7 @@ module axi_ad7606x_16b_pif #(
wire adc_config_enable;
wire adc_config_en;
wire adc_config_rd_wr;
wire [ 1:0] adc_config_mode;
wire [ 4:0] adc_status_er_5b;
wire adc_status_er;
@ -155,6 +164,30 @@ module axi_ad7606x_16b_pif #(
assign start_transfer_s = (end_of_conv | adc_config_en) ? 1'b1 : 1'b0;
always @(posedge clk) begin
if (rstn == 1'b0) begin
adc_config_mode_r <= 2'h0;
end else begin
if (adc_mode_en) begin
if (adc_custom_control == 'h0) begin
adc_config_mode_r <= SIMPLE;
end else if (adc_custom_control == 'h1) begin
adc_config_mode_r <= CRC_ENABLED;
end else if (adc_custom_control == 'h2) begin
adc_config_mode_r <= STATUS_HEADER;
end else if (adc_custom_control == 'h3) begin
adc_config_mode_r <= CRC_STATUS;
end else begin
adc_config_mode_r <= adc_config_mode;
end
end else begin
adc_config_mode_r <= adc_config_mode;
end
end
end
assign adc_config_mode = adc_config_mode_r;
always @(negedge clk) begin
if (transfer_state == IDLE) begin
rd_conv_d <= end_of_conv;
@ -187,28 +220,28 @@ module axi_ad7606x_16b_pif #(
end
always @(posedge clk) begin
if (ADC_READ_MODE == SIMPLE) begin
if (adc_config_mode == SIMPLE) begin
nr_rd_burst = 5'd8;
if ((first_data & ~cs_n) && ~adc_config_enable_d) begin
read_ch_data <= 1'b1;
end else if (channel_counter == 5'd8 && transfer_state == IDLE) begin
read_ch_data <= 1'b0;
end
end else if (ADC_READ_MODE == CRC_ENABLED) begin
end else if (adc_config_mode == CRC_ENABLED) begin
nr_rd_burst = 5'd9;
if ((first_data & ~cs_n) && ~adc_config_enable_d) begin
read_ch_data <= 1'b1;
end else if (channel_counter == 5'd9 && transfer_state == IDLE) begin
read_ch_data <= 1'b0;
end
end else if (ADC_READ_MODE == STATUS_HEADER) begin
end else if (adc_config_mode == STATUS_HEADER) begin
nr_rd_burst <= 5'd16;
if ((first_data & ~cs_n) && ~adc_config_enable_d) begin
read_ch_data <= 1'b1;
end else if (channel_counter == 5'd16 && transfer_state == IDLE) begin
read_ch_data <= 1'b0;
end
end else if (ADC_READ_MODE == CRC_STATUS) begin
end else if (adc_config_mode == CRC_STATUS) begin
nr_rd_burst <= 5'd17;
if ((first_data & ~cs_n) && ~adc_config_enable_d) begin
read_ch_data <= 1'b0;
@ -218,7 +251,7 @@ module axi_ad7606x_16b_pif #(
end else begin
read_ch_data <= 1'b1;
end
if (ADC_READ_MODE == SIMPLE || ADC_READ_MODE == CRC_ENABLED) begin
if (adc_config_mode == SIMPLE || adc_config_mode == CRC_ENABLED) begin
if (read_ch_data == 1'b1 && rd_new_data_s == 1'b1) begin
case (channel_counter)
5'd0 : begin
@ -246,12 +279,13 @@ module axi_ad7606x_16b_pif #(
adc_data_7 <= rd_data;
end
5'd8 : begin
adc_crc <= rd_data;
adc_crc_res <= crc_128({adc_data_0,adc_data_1,adc_data_2,adc_data_3,adc_data_4,adc_data_5,adc_data_6,adc_data_7});
adc_crc_r <= rd_data;
adc_crc_res_r <= crc_128({adc_data_0,adc_data_1,adc_data_2,adc_data_3,
adc_data_4,adc_data_5,adc_data_6,adc_data_7});
end
endcase
end
case (ADC_READ_MODE)
case (adc_config_mode)
SIMPLE: begin
adc_valid <= (channel_counter == 5'd8) ? rd_valid_d : 1'b0;
end
@ -259,7 +293,7 @@ module axi_ad7606x_16b_pif #(
adc_valid <= (channel_counter == 5'd9) ? rd_valid_d : 1'b0;
end
endcase
end else if (ADC_READ_MODE == STATUS_HEADER || ADC_READ_MODE == CRC_STATUS) begin
end else if (adc_config_mode == STATUS_HEADER || adc_config_mode == CRC_STATUS) begin
if (read_ch_data == 1'b1 && rd_new_data_s == 1'b1) begin
case (channel_counter)
5'd0: begin
@ -311,14 +345,16 @@ module axi_ad7606x_16b_pif #(
adc_status_7 <= rd_data[15:8];
end
5'd16: begin
adc_crc <= rd_data;
adc_crc_res <= crc_256({adc_data_0,8'b0,adc_status_0,adc_data_1,8'b0,adc_status_1,adc_data_2,8'b0,adc_status_2,adc_data_3,8'b0,adc_status_3,adc_data_4,8'b0,adc_status_4,adc_data_5,8'b0,adc_status_5,adc_data_6,8'b0,adc_status_6,adc_data_7,8'b0,adc_status_7});
adc_crc_r <= rd_data;
adc_crc_res_r <= crc_256({adc_data_0,8'b0,adc_status_0,adc_data_1,8'b0,adc_status_1,adc_data_2,8'b0,adc_status_2,
adc_data_3,8'b0,adc_status_3,adc_data_4,8'b0,adc_status_4,adc_data_5,8'b0,adc_status_5,
adc_data_6,8'b0,adc_status_6,adc_data_7,8'b0,adc_status_7});
end
endcase
end
if (ADC_READ_MODE == STATUS_HEADER) begin
if (adc_config_mode == STATUS_HEADER) begin
adc_valid <= (channel_counter == 5'd16) ? rd_valid_d : 1'b0;
end else if (ADC_READ_MODE == CRC_STATUS) begin
end else if (adc_config_mode == CRC_STATUS) begin
adc_valid <= (channel_counter == 5'd17) ? rd_valid_d : 1'b0;
end
end
@ -397,7 +433,7 @@ module axi_ad7606x_16b_pif #(
transfer_state_next <= (adc_config_enable_d | rd_conv_d) ? CS_HIGH : CNTRL_HIGH;
end
CS_HIGH : begin
transfer_state_next <= (channel_counter == nr_rd_burst || adc_config_enable_d == 1'b1) ? IDLE : CNTRL_LOW;
transfer_state_next <= (channel_counter == nr_rd_burst || adc_config_enable_d) ? IDLE : CNTRL_LOW;
end
default : begin
transfer_state_next <= IDLE;
@ -408,7 +444,7 @@ module axi_ad7606x_16b_pif #(
// data valid for the register access
assign rd_valid_s = (transfer_state == CNTRL_HIGH && rd_conv_d == 1'b1) ? 1'b1 : 1'b0;
assign adc_ctrl_status = (transfer_state == CNTRL_HIGH && adc_config_enable_d == 1'b1 && adc_config_rd_wr == 1'b1) ? 1'b1 : 1'b0;
assign adc_ctrl_status = (transfer_state == CNTRL_HIGH && (adc_config_enable_d == 1'b1 && adc_config_rd_wr == 1'b1)) ? 1'b1 : 1'b0;
// FSM output logic
@ -424,11 +460,16 @@ module axi_ad7606x_16b_pif #(
assign adc_status_er_5b = adc_status_0[7:3] | adc_status_1[7:3] | adc_status_2[7:3] | adc_status_3[7:3] | adc_status_4[7:3] | adc_status_5[7:3] | adc_status_6[7:3] | adc_status_7[7:3];
assign adc_status_er = adc_status_er_5b[0] | adc_status_er_5b[1] | adc_status_er_5b[2] | adc_status_er_5b[3] | adc_status_er_5b[4];
assign adc_status = (ADC_READ_MODE == STATUS_HEADER || ADC_READ_MODE == CRC_STATUS) ? (adc_status_er ? 1'b0 : 1'b1) : 1'b1;
assign adc_status = (adc_config_mode == STATUS_HEADER || adc_config_mode == CRC_STATUS) ? (adc_status_er ? 1'b0 : 1'b1) : 1'b1;
// clear adc_crc* signals if the adc_config_mode is STATUS_HEADER or SIMPLE
assign adc_crc = (adc_config_mode == STATUS_HEADER || adc_config_mode == SIMPLE) ? 16'h0 : adc_crc_r;
assign adc_crc_res = (adc_config_mode == STATUS_HEADER || adc_config_mode == SIMPLE) ? 16'h0 : adc_crc_res_r;
assign cs_n = (transfer_state == IDLE) ? 1'b1 : 1'b0;
assign db_t = (adc_config_enable_d == 1'b1 && adc_config_rd_wr == 1'b0) ? 1'b0 : 1'b1;
assign rd_n = (transfer_state == CNTRL_LOW) && (rd_conv_d == 1'b1 || (adc_config_enable_d == 1'b1 && adc_config_rd_wr == 1'b1)) ? 1'b0 : 1'b1;
assign wr_n = (transfer_state == CNTRL_LOW) && (adc_config_enable_d == 1'b1 && adc_config_rd_wr == 1'b0) ? 1'b0 : 1'b1;
endmodule
endmodule

98
library/axi_ad7606x/axi_ad7606x_18b_pif.v
View File

@ -36,7 +36,6 @@
`timescale 1ns/100ps
module axi_ad7606x_18b_pif #(
parameter ADC_READ_MODE = 0,
parameter NEG_EDGE = 1,
parameter POS_EDGE = 0
) (
@ -71,8 +70,8 @@ module axi_ad7606x_18b_pif #(
output reg [17:0] adc_data_7,
output reg [ 7:0] adc_status_7 = 'h0,
output adc_status,
output reg [15:0] adc_crc = 'h0,
output reg [15:0] adc_crc_res = 'h0,
output [15:0] adc_crc,
output [15:0] adc_crc_res,
output adc_crc_err,
output reg adc_valid,
@ -83,6 +82,8 @@ module axi_ad7606x_18b_pif #(
input [31:0] adc_config_ctrl,
output adc_ctrl_status,
input [15:0] wr_data,
input adc_mode_en,
input [7:0] adc_custom_control,
output reg [15:0] rd_data = 'hf,
output reg rd_valid
);
@ -95,8 +96,8 @@ module axi_ad7606x_18b_pif #(
localparam [ 2:0] CNTRL_HIGH = 3'h3;
localparam [ 2:0] CS_HIGH = 3'h4;
localparam [ 1:0] SIMPLE = 0;
localparam [ 1:0] STATUS_HEADER = 1;
localparam [ 1:0] CRC_ENABLED = 2;
localparam [ 1:0] STATUS_HEADER = 2;
localparam [ 1:0] CRC_ENABLED = 1;
localparam [ 1:0] CRC_STATUS = 3;
// internal registers
@ -114,6 +115,10 @@ module axi_ad7606x_18b_pif #(
reg read_ch_data = 1'd0;
reg [ 7:0] adc_status_er_ch_id = 8'h0;
reg [15:0] adc_crc_r = 16'h0;
reg [15:0] adc_crc_res_r = 16'h0;
reg [ 1:0] adc_config_mode_r = 2'h0;
// internal wires
@ -127,6 +132,7 @@ module axi_ad7606x_18b_pif #(
wire adc_config_enable;
wire adc_config_en;
wire adc_config_rd_wr;
wire [ 1:0] adc_config_mode;
wire [ 4:0] adc_status_er_5b;
wire adc_status_er;
@ -138,14 +144,6 @@ module axi_ad7606x_18b_pif #(
// instantiations
ad_edge_detect #(
.EDGE(NEG_EDGE)
) i_ad_edge_detect (
.clk (clk),
.rst (~rstn),
.signal_in (busy),
.signal_out (end_of_conv));
ad_edge_detect #(
.EDGE(POS_EDGE)
) i_ad_edge_detect_en (
@ -154,10 +152,42 @@ module axi_ad7606x_18b_pif #(
.signal_in (adc_config_enable),
.signal_out (adc_config_en));
ad_edge_detect #(
.EDGE(NEG_EDGE)
) i_ad_edge_detect (
.clk (clk),
.rst (~rstn),
.signal_in (busy),
.signal_out (end_of_conv));
// counters to control the RD_N and WR_N lines
assign start_transfer_s = (end_of_conv | adc_config_en) ? 1'b1 : 1'b0;
always @(posedge clk) begin
if (rstn == 1'b0) begin
adc_config_mode_r <= 2'h0;
end else begin
if (adc_mode_en) begin
if (adc_custom_control == 'h0) begin
adc_config_mode_r <= SIMPLE;
end else if (adc_custom_control == 'h1) begin
adc_config_mode_r <= CRC_ENABLED;
end else if (adc_custom_control == 'h2) begin
adc_config_mode_r <= STATUS_HEADER;
end else if (adc_custom_control == 'h3) begin
adc_config_mode_r <= CRC_STATUS;
end else begin
adc_config_mode_r <= adc_config_mode;
end
end else begin
adc_config_mode_r <= adc_config_mode;
end
end
end
assign adc_config_mode = adc_config_mode_r;
always @(negedge clk) begin
if (transfer_state == IDLE) begin
rd_conv_d <= end_of_conv;
@ -190,14 +220,14 @@ module axi_ad7606x_18b_pif #(
end
always @(posedge clk) begin
if (ADC_READ_MODE == SIMPLE || ADC_READ_MODE == STATUS_HEADER) begin
if (adc_config_mode == SIMPLE || adc_config_mode == STATUS_HEADER) begin
nr_rd_burst = 5'd16;
if ((first_data & ~cs_n) && ~adc_config_enable_d) begin
read_ch_data <= 1'b1;
end else if (channel_counter == 5'd16 && transfer_state == IDLE) begin
read_ch_data <= 1'b0;
end
end else if (ADC_READ_MODE == CRC_ENABLED || ADC_READ_MODE == CRC_STATUS) begin
end else if (adc_config_mode == CRC_ENABLED || adc_config_mode == CRC_STATUS) begin
nr_rd_burst = 5'd17;
if ((first_data & ~cs_n) && ~adc_config_enable_d) begin
read_ch_data <= 1'b1;
@ -214,7 +244,7 @@ module axi_ad7606x_18b_pif #(
end
5'd1 : begin
adc_data_0[1:0] <= rd_data[15:14];
if (ADC_READ_MODE == STATUS_HEADER || ADC_READ_MODE == CRC_STATUS) begin
if (adc_config_mode == STATUS_HEADER || adc_config_mode == CRC_STATUS) begin
adc_status_0 <= rd_data[7:0];
end
end
@ -223,7 +253,7 @@ module axi_ad7606x_18b_pif #(
end
5'd3 : begin
adc_data_1[1:0] <= rd_data[15:14];
if (ADC_READ_MODE == STATUS_HEADER || ADC_READ_MODE == CRC_STATUS) begin
if (adc_config_mode == STATUS_HEADER || adc_config_mode == CRC_STATUS) begin
adc_status_1 <= rd_data[7:0];
end
end
@ -232,7 +262,7 @@ module axi_ad7606x_18b_pif #(
end
5'd5 : begin
adc_data_2[1:0] <= rd_data[15:14];
if (ADC_READ_MODE == STATUS_HEADER || ADC_READ_MODE == CRC_STATUS) begin
if (adc_config_mode == STATUS_HEADER || adc_config_mode == CRC_STATUS) begin
adc_status_2 <= rd_data[7:0];
end
end
@ -241,7 +271,7 @@ module axi_ad7606x_18b_pif #(
end
5'd7 : begin
adc_data_3[1:0] <= rd_data[15:14];
if (ADC_READ_MODE == STATUS_HEADER || ADC_READ_MODE == CRC_STATUS) begin
if (adc_config_mode == STATUS_HEADER || adc_config_mode == CRC_STATUS) begin
adc_status_3 <= rd_data[7:0];
end
end
@ -250,7 +280,7 @@ module axi_ad7606x_18b_pif #(
end
5'd9 : begin
adc_data_4[1:0] <= rd_data[15:14];
if (ADC_READ_MODE == STATUS_HEADER || ADC_READ_MODE == CRC_STATUS) begin
if (adc_config_mode == STATUS_HEADER || adc_config_mode == CRC_STATUS) begin
adc_status_4 <= rd_data[7:0];
end
end
@ -259,7 +289,7 @@ module axi_ad7606x_18b_pif #(
end
5'd11 : begin
adc_data_5[1:0] <= rd_data[15:14];
if (ADC_READ_MODE == STATUS_HEADER || ADC_READ_MODE == CRC_STATUS) begin
if (adc_config_mode == STATUS_HEADER || adc_config_mode == CRC_STATUS) begin
adc_status_5 <= rd_data[7:0];
end
end
@ -268,7 +298,7 @@ module axi_ad7606x_18b_pif #(
end
5'd13 : begin
adc_data_6[1:0] <= rd_data[15:14];
if (ADC_READ_MODE == STATUS_HEADER || ADC_READ_MODE == CRC_STATUS) begin
if (adc_config_mode == STATUS_HEADER || adc_config_mode == CRC_STATUS) begin
adc_status_6 <= rd_data[7:0];
end
end
@ -277,21 +307,24 @@ module axi_ad7606x_18b_pif #(
end
5'd15 : begin
adc_data_7[1:0] <= rd_data[15:14];
if (ADC_READ_MODE == STATUS_HEADER || ADC_READ_MODE == CRC_STATUS) begin
if (adc_config_mode == STATUS_HEADER || adc_config_mode == CRC_STATUS) begin
adc_status_7 <= rd_data[7:0];
end
end
5'd16 : begin
adc_crc <= rd_data;
if (ADC_READ_MODE == CRC_ENABLED) begin
adc_crc_res <= crc_256({adc_data_0,14'b0,adc_data_1,14'b0,adc_data_2,14'b0,adc_data_3,14'b0,adc_data_4,14'b0,adc_data_5,14'b0,adc_data_6,14'b0,adc_data_7,14'b0});
end else if (ADC_READ_MODE == CRC_STATUS) begin
adc_crc_res <= crc_256({adc_data_0,6'b0,adc_status_0,adc_data_1,6'b0,adc_status_1,adc_data_2,6'b0,adc_status_2,adc_data_3,6'b0,adc_status_3,adc_data_4,6'b0,adc_status_4,adc_data_5,6'b0,adc_status_5,adc_data_6,6'b0,adc_status_6,adc_data_7,6'b0,adc_status_7});
adc_crc_r <= rd_data;
if (adc_config_mode == CRC_ENABLED) begin
adc_crc_res_r <= crc_256({adc_data_0,14'b0,adc_data_1,14'b0,adc_data_2,14'b0,adc_data_3,14'b0,
adc_data_4,14'b0,adc_data_5,14'b0,adc_data_6,14'b0,adc_data_7,14'b0});
end else if (adc_config_mode == CRC_STATUS) begin
adc_crc_res_r <= crc_256({adc_data_0,6'b0,adc_status_0,adc_data_1,6'b0,adc_status_1,adc_data_2,6'b0,adc_status_2,
adc_data_3,6'b0,adc_status_3,adc_data_4,6'b0,adc_status_4,adc_data_5,6'b0,adc_status_5,
adc_data_6,6'b0,adc_status_6,adc_data_7,6'b0,adc_status_7});
end
end
endcase
end
case (ADC_READ_MODE)
case (adc_config_mode)
SIMPLE: begin
adc_valid <= (channel_counter == 5'd16) ? rd_valid_d : 1'b0;
end
@ -384,7 +417,12 @@ module axi_ad7606x_18b_pif #(
assign adc_status_er_5b = adc_status_0[7:3] | adc_status_1[7:3] | adc_status_2[7:3] | adc_status_3[7:3] | adc_status_4[7:3] | adc_status_5[7:3] | adc_status_6[7:3] | adc_status_7[7:3];
assign adc_status_er = adc_status_er_5b[0] | adc_status_er_5b[1] | adc_status_er_5b[2] | adc_status_er_5b[3] | adc_status_er_5b[4];
assign adc_status = (ADC_READ_MODE == STATUS_HEADER || ADC_READ_MODE == CRC_STATUS) ? (adc_status_er ? 1'b0 : 1'b1) : 1'b1;
assign adc_status = (adc_config_mode == STATUS_HEADER || adc_config_mode == CRC_STATUS) ? (adc_status_er ? 1'b0 : 1'b1) : 1'b1;
// clear adc_crc* signals if the adc_config_mode is STATUS_HEADER or SIMPLE
assign adc_crc = (adc_config_mode == STATUS_HEADER || adc_config_mode == SIMPLE) ? 16'h0 : adc_crc_r;
assign adc_crc_res = (adc_config_mode == STATUS_HEADER || adc_config_mode == SIMPLE) ? 16'h0 : adc_crc_res_r;
assign cs_n = (transfer_state == IDLE) ? 1'b1 : 1'b0;
assign db_t = (adc_config_enable_d == 1'b1 && adc_config_rd_wr == 1'b0) ? 1'b0 : 1'b1;

16
library/axi_ad7606x/axi_ad7606x_ip.tcl
View File

@ -97,22 +97,6 @@ set_property -dict [list \
} \
] [ipx::get_user_parameters DEV_CONFIG -of_objects $cc]
ipgui::add_param -name "ADC_READ_MODE" -component $cc
set_property -dict [list \
"widget" "comboBox" \
"display_name" "ADC Read Mode Selection" \
] [ipgui::get_guiparamspec -name "ADC_READ_MODE" -component $cc]
set_property -dict [list \
"value_validation_type" "pairs" \
"value_validation_pairs" { \
"SIMPLE" "0" \
"STATUS_HEADER" "1" \
"CRC_ENABLED" "2" \
"CRC_STATUS" "3" \
} \
] [ipx::get_user_parameters ADC_READ_MODE -of_objects $cc]
adi_add_auto_fpga_spec_params
## save the modifications

11
projects/ad7606x_fmc/common/ad7606x_bd.tcl
View File

@ -6,13 +6,11 @@
# system level parameters
set DEV_CONFIG $ad_project_params(DEV_CONFIG)
set ADC_N_BITS [expr {$DEV_CONFIG == 2 ? 18 : 16}]
set ADC_TO_DMA_N_BITS [expr {$ADC_N_BITS == 16 ? 16 : 32}]
set SIMPLE_STATUS_CRC $ad_project_params(SIMPLE_STATUS_CRC)
set ADC_CH_DW [expr {$ADC_N_BITS == 16 ? 16 : 32}]
set EXT_CLK $ad_project_params(EXT_CLK)
set TOTAL_N_BITS_DMA [expr {$ADC_TO_DMA_N_BITS*8}]
set TOTAL_N_BITS_DMA [expr {$ADC_CH_DW*8}]
puts "build parameters: DEV_CONFIG: $DEV_CONFIG"
puts "build parameters: SIMPLE_STATUS_CRC: $SIMPLE_STATUS_CRC"
puts "build parameters: EXT_CLK: $EXT_CLK"
# data, read and write lines
@ -35,8 +33,7 @@ create_bd_port -dir I rx_first_data
ad_ip_instance axi_ad7606x axi_ad7606x
ad_ip_parameter axi_ad7606x CONFIG.DEV_CONFIG $DEV_CONFIG
ad_ip_parameter axi_ad7606x CONFIG.ADC_N_BITS $ADC_N_BITS
ad_ip_parameter axi_ad7606x CONFIG.ADC_TO_DMA_N_BITS $ADC_TO_DMA_N_BITS
ad_ip_parameter axi_ad7606x CONFIG.ADC_READ_MODE $SIMPLE_STATUS_CRC
ad_ip_parameter axi_ad7606x CONFIG.ADC_CH_DW $ADC_CH_DW
ad_ip_parameter axi_ad7606x CONFIG.EXTERNAL_CLK $EXT_CLK
ad_ip_instance axi_pwm_gen axi_pwm_gen
@ -60,7 +57,7 @@ ad_ip_parameter axi_ad7606x_dma CONFIG.DMA_DATA_WIDTH_DEST 64
ad_ip_instance util_cpack2 ad7606x_adc_pack
ad_ip_parameter ad7606x_adc_pack CONFIG.NUM_OF_CHANNELS 8
ad_ip_parameter ad7606x_adc_pack CONFIG.SAMPLE_DATA_WIDTH $ADC_TO_DMA_N_BITS
ad_ip_parameter ad7606x_adc_pack CONFIG.SAMPLE_DATA_WIDTH $ADC_CH_DW
if {$EXT_CLK == 1} {
# use Xilinx's clocking wizard in order to generate th clock from the CPU clock, this being then assigned to the adc_clk in the axi_ad7606x IP

2
projects/ad7606x_fmc/common/ad7606x_fmc.txt
View File

@ -32,3 +32,5 @@ H07 LA04_P OS1 adc_os[1] LVCMOS25 #N/A
H16 LA11_P OS2 adc_os[2] LVCMOS25 #N/A
C15 LA10_N STBY adc_stby LVCMOS25 #N/A
D15 LA09_N RANGE_1 adc_range LVCMOS25 #N/A
C18 LA14_P SERPAR adc_serpar LVCMOS25 #N/A
C19 LA14_N REFSEL adc_refsel LVCMOS25 #N/A

6
projects/ad7606x_fmc/zed/system_bd.tcl
View File

@ -8,10 +8,12 @@ source $ad_hdl_dir/projects/scripts/adi_pd.tcl
source ../common/ad7606x_bd.tcl
set mem_init_sys_path [get_env_param ADI_PROJECT_DIR ""]mem_init_sys.txt;
#system ID
ad_ip_parameter axi_sysid_0 CONFIG.ROM_ADDR_BITS 9
ad_ip_parameter rom_sys_0 CONFIG.PATH_TO_FILE "[pwd]/mem_init_sys.txt"
ad_ip_parameter rom_sys_0 CONFIG.PATH_TO_FILE "[pwd]/$mem_init_sys_path"
ad_ip_parameter rom_sys_0 CONFIG.ROM_ADDR_BITS 9
set sys_cstring "$DEV_CONFIG,$SIMPLE_STATUS_CRC,$EXT_CLK"
set sys_cstring "$DEV_CONFIG,$EXT_CLK"
sysid_gen_sys_init_file $sys_cstring

4
projects/ad7606x_fmc/zed/system_project.tcl
View File

@ -10,18 +10,14 @@ source $ad_hdl_dir/projects/scripts/adi_board.tcl
# Parameter description
# DEV_CONFIG - The device which will be used
# - Options : AD7606B(0)/C-16(1)/C-18(2)
# SIMPLE_STATUS_CRC - ADC read mode options
# - Options : SIMPLE(0), STATUS(1), CRC(2) CRC_STATUS(3)
# EXT_CLK - Use external clock as ADC clock
# - Options : No(0), Yes(1)
set DEV_CONFIG [get_env_param DEV_CONFIG 0]
set SIMPLE_STATUS_CRC [get_env_param SIMPLE_STATUS_CRC 0]
set EXT_CLK [get_env_param EXT_CLK 0]
adi_project ad7606x_fmc_zed 0 [list \
DEV_CONFIG $DEV_CONFIG \
SIMPLE_STATUS_CRC $SIMPLE_STATUS_CRC \
EXT_CLK $EXT_CLK \
]