usrpe31x- updates
Rejeesh Kutty
parent
7b958fed87
commit
c9ac870086
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@ -5,17 +5,65 @@
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####################################################################################
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####################################################################################
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.PHONY: all clean clean-all
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all:
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-make -C system_project.tcl all
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M_DEPS += system_top.v
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M_DEPS += system_project.tcl
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M_DEPS += system_constr.xdc
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M_DEPS += system_bd.tcl
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M_DEPS += ../scripts/adi_project.tcl
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M_DEPS += ../scripts/adi_env.tcl
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M_DEPS += ../scripts/adi_board.tcl
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M_DEPS += ../../library/xilinx/common/ad_iobuf.v
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M_DEPS += ../../library/axi_ad9361/axi_ad9361.xpr
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M_DEPS += ../../library/axi_dmac/axi_dmac.xpr
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M_DEPS += ../../library/util_cpack/util_cpack.xpr
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M_DEPS += ../../library/util_upack/util_upack.xpr
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M_DEPS += ../../library/util_tdd_sync/util_tdd_sync.xpr
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M_VIVADO := vivado -mode batch -source
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M_FLIST := *.cache
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M_FLIST += *.data
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M_FLIST += *.xpr
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M_FLIST += *.log
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M_FLIST += *.jou
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M_FLIST += xgui
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M_FLIST += *.runs
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M_FLIST += *.srcs
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M_FLIST += *.sdk
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M_FLIST += *.hw
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M_FLIST += *.sim
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M_FLIST += .Xil
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M_FLIST += *.ip_user_files
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.PHONY: all lib clean clean-all
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all: lib usrpe31x.sdk/system_top.hdf
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clean:
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make -C system_project.tcl clean
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rm -rf $(M_FLIST)
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clean-all:
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make -C system_project.tcl clean-all
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clean-all:clean
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make -C ../../library/axi_ad9361 clean
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make -C ../../library/axi_dmac clean
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make -C ../../library/util_cpack clean
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make -C ../../library/util_upack clean
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make -C ../../library/util_tdd_sync clean
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usrpe31x.sdk/system_top.hdf: $(M_DEPS)
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-rm -rf $(M_FLIST)
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$(M_VIVADO) system_project.tcl >> usrpe31x_vivado.log 2>&1
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lib:
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make -C ../../library/axi_ad9361
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make -C ../../library/axi_dmac
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make -C ../../library/util_cpack
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make -C ../../library/util_upack
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make -C ../../library/util_tdd_sync
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####################################################################################
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####################################################################################
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@ -4,19 +4,21 @@
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create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 ddr
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create_bd_intf_port -mode Master -vlnv xilinx.com:display_processing_system7:fixedio_rtl:1.0 fixed_io
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create_bd_port -dir O spi0_csn_2_o
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create_bd_port -dir O spi0_csn_1_o
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create_bd_port -dir O spi0_csn_0_o
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create_bd_port -dir I spi0_csn_i
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create_bd_port -dir I spi0_clk_i
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create_bd_port -dir O spi0_clk_o
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create_bd_port -dir I spi0_sdo_i
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create_bd_port -dir O spi0_sdo_o
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create_bd_port -dir I spi0_sdi_i
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create_bd_port -dir O spi0_csn_0
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create_bd_port -dir O spi0_csn_1
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create_bd_port -dir O spi0_csn_2
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create_bd_port -dir O spi0_clk
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create_bd_port -dir O spi0_mosi
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create_bd_port -dir I spi0_miso
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create_bd_port -dir I -from 16 -to 0 gpio_i
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create_bd_port -dir O -from 16 -to 0 gpio_o
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create_bd_port -dir O -from 16 -to 0 gpio_t
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create_bd_port -dir I spi1_csn
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create_bd_port -dir I spi1_clk
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create_bd_port -dir I spi1_mosi
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create_bd_port -dir O spi1_miso
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create_bd_port -dir I -from 63 -to 0 ps_gpio_i
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create_bd_port -dir O -from 63 -to 0 ps_gpio_o
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create_bd_port -dir O -from 63 -to 0 ps_gpio_t
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# interrupts
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@ -51,40 +53,52 @@ set_property -dict [list CONFIG.PCW_EN_CLK1_PORT {1}] $sys_ps7
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set_property -dict [list CONFIG.PCW_EN_RST1_PORT {1}] $sys_ps7
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set_property -dict [list CONFIG.PCW_FPGA0_PERIPHERAL_FREQMHZ {100.0}] $sys_ps7
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set_property -dict [list CONFIG.PCW_FPGA1_PERIPHERAL_FREQMHZ {200.0}] $sys_ps7
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set_property -dict [list CONFIG.PCW_GPIO_EMIO_GPIO_ENABLE {1}] $sys_ps7
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set_property -dict [list CONFIG.PCW_GPIO_EMIO_GPIO_IO {17}] $sys_ps7
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set_property -dict [list CONFIG.PCW_SPI1_PERIPHERAL_ENABLE {1}] $sys_ps7
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set_property -dict [list CONFIG.PCW_I2C0_PERIPHERAL_ENABLE {1}] $sys_ps7
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set_property -dict [list CONFIG.PCW_UART1_PERIPHERAL_ENABLE {1}] $sys_ps7
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set_property -dict [list CONFIG.PCW_UART1_UART1_IO {MIO 12 .. 13}] $sys_ps7
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set_property -dict [list CONFIG.PCW_I2C1_PERIPHERAL_ENABLE {0}] $sys_ps7
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set_property -dict [list CONFIG.PCW_QSPI_PERIPHERAL_ENABLE {1}] $sys_ps7
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set_property -dict [list CONFIG.PCW_QSPI_GRP_SINGLE_SS_ENABLE {1}] $sys_ps7
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set_property -dict [list CONFIG.PCW_SD0_PERIPHERAL_ENABLE {0}] $sys_ps7
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set_property -dict [list CONFIG.PCW_SPI0_PERIPHERAL_ENABLE {1}] $sys_ps7
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set_property -dict [list CONFIG.PCW_SPI0_SPI0_IO {EMIO}] $sys_ps7
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set_property -dict [list CONFIG.PCW_TTC0_PERIPHERAL_ENABLE {0}] $sys_ps7
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set_property -dict [list CONFIG.PCW_USE_FABRIC_INTERRUPT {1}] $sys_ps7
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set_property -dict [list CONFIG.PCW_USB0_PERIPHERAL_ENABLE {1}] $sys_ps7
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set_property -dict [list CONFIG.PCW_GPIO_MIO_GPIO_ENABLE {1}] $sys_ps7
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set_property -dict [list CONFIG.PCW_GPIO_MIO_GPIO_IO {MIO}] $sys_ps7
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set_property -dict [list CONFIG.PCW_USB0_RESET_IO {MIO 52}] $sys_ps7
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set_property -dict [list CONFIG.PCW_ENET0_PERIPHERAL_ENABLE {1}] $sys_ps7
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set_property -dict [list CONFIG.PCW_ENET0_ENET0_IO {MIO 16 .. 27}] $sys_ps7
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set_property -dict [list CONFIG.PCW_ENET0_RESET_ENABLE {1}] $sys_ps7
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set_property -dict [list CONFIG.PCW_ENET0_RESET_IO {MIO 11}] $sys_ps7
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set_property -dict [list CONFIG.PCW_ENET0_GRP_MDIO_ENABLE {1}] $sys_ps7
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set_property -dict [list CONFIG.PCW_ENET0_GRP_MDIO_IO {MIO 52 .. 53}] $sys_ps7
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set_property -dict [list CONFIG.PCW_USB0_PERIPHERAL_ENABLE {1}] $sys_ps7
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set_property -dict [list CONFIG.PCW_USB0_USB0_IO {MIO 28 .. 39}] $sys_ps7
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set_property -dict [list CONFIG.PCW_USB0_RESET_ENABLE {1}] $sys_ps7
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set_property -dict [list CONFIG.PCW_USB0_RESET_IO {MIO 9}] $sys_ps7
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set_property -dict [list CONFIG.PCW_SD0_PERIPHERAL_ENABLE {1}] $sys_ps7
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set_property -dict [list CONFIG.PCW_SD0_SD0_IO {MIO 40 .. 45}] $sys_ps7
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set_property -dict [list CONFIG.PCW_SD0_GRP_CD_ENABLE {1}] $sys_ps7
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set_property -dict [list CONFIG.PCW_SD0_GRP_CD_IO {MIO 0}] $sys_ps7
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set_property -dict [list CONFIG.PCW_SDIO_PERIPHERAL_FREQMHZ {50}] $sys_ps7
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set_property -dict [list CONFIG.PCW_SPI0_PERIPHERAL_ENABLE {1}] $sys_ps7
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set_property -dict [list CONFIG.PCW_SPI0_SPI0_IO {EMIO}] $sys_ps7
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set_property -dict [list CONFIG.PCW_SPI1_PERIPHERAL_ENABLE {1}] $sys_ps7
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set_property -dict [list CONFIG.PCW_SPI1_SPI1_IO {EMIO}] $sys_ps7
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set_property -dict [list CONFIG.PCW_UART0_PERIPHERAL_ENABLE {1}] $sys_ps7
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set_property -dict [list CONFIG.PCW_UART0_UART0_IO {MIO 14 .. 15}] $sys_ps7
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set_property -dict [list CONFIG.PCW_UART1_PERIPHERAL_ENABLE {1}] $sys_ps7
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set_property -dict [list CONFIG.PCW_UART1_UART1_IO {MIO 48 .. 49}] $sys_ps7
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set_property -dict [list CONFIG.PCW_I2C0_PERIPHERAL_ENABLE {1}] $sys_ps7
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set_property -dict [list CONFIG.PCW_I2C0_I2C0_IO {MIO 46 .. 47}] $sys_ps7
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set_property -dict [list CONFIG.PCW_GPIO_EMIO_GPIO_ENABLE {1}] $sys_ps7
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set_property -dict [list CONFIG.PCW_USE_FABRIC_INTERRUPT {1}] $sys_ps7
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set_property -dict [list CONFIG.PCW_IRQ_F2P_INTR {1}] $sys_ps7
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set_property -dict [list CONFIG.PCW_IRQ_F2P_MODE {REVERSE}] $sys_ps7
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# DDR MT41K256M16 HA-125 (32M, 16bit, 8banks)
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set_property -dict [list CONFIG.PCW_UIPARAM_DDR_PARTNO {MT41K256M16 RE-125}] $sys_ps7
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set_property -dict [list CONFIG.PCW_UIPARAM_DDR_BUS_WIDTH {16 Bit}] $sys_ps7
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set_property -dict [list CONFIG.PCW_UIPARAM_DDR_PARTNO {Custom}] $sys_ps7
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set_property -dict [list CONFIG.PCW_UIPARAM_DDR_BUS_WIDTH {32 Bit}] $sys_ps7
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set_property -dict [list CONFIG.PCW_UIPARAM_DDR_USE_INTERNAL_VREF {0}] $sys_ps7
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set_property -dict [list CONFIG.PCW_UIPARAM_DDR_DRAM_WIDTH {16 Bits}] $sys_ps7
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set_property -dict [list CONFIG.PCW_UIPARAM_DDR_DEVICE_CAPACITY {4096 MBits}] $sys_ps7
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set_property -dict [list CONFIG.PCW_UIPARAM_DDR_CWL {6}] $sys_ps7
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set_property -dict [list CONFIG.PCW_UIPARAM_DDR_T_RC {48.75}] $sys_ps7
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set_property -dict [list CONFIG.PCW_UIPARAM_DDR_T_RAS_MIN {35.0}] $sys_ps7
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set_property -dict [list CONFIG.PCW_UIPARAM_DDR_T_FAW {40.0}] $sys_ps7
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set_property -dict [list CONFIG.PCW_UIPARAM_DDR_TRAIN_WRITE_LEVEL {1}] $sys_ps7
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set_property -dict [list CONFIG.PCW_UIPARAM_DDR_TRAIN_READ_GATE {1}] $sys_ps7
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set_property -dict [list CONFIG.PCW_UIPARAM_DDR_TRAIN_DATA_EYE {1}] $sys_ps7
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set_property -dict [list CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 {0.048}] $sys_ps7
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set_property -dict [list CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 {0.050}] $sys_ps7
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set_property -dict [list CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY0 {0.241}] $sys_ps7
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set_property -dict [list CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY1 {0.240}] $sys_ps7
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set sys_concat_intc [create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 sys_concat_intc]
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set_property -dict [list CONFIG.NUM_PORTS {16}] $sys_concat_intc
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@ -104,22 +118,28 @@ ad_connect sys_rstgen/ext_reset_in sys_ps7/FCLK_RESET0_N
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# interface connections
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ad_connect ddr sys_ps7/DDR
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ad_connect gpio_i sys_ps7/GPIO_I
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ad_connect gpio_o sys_ps7/GPIO_O
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ad_connect gpio_t sys_ps7/GPIO_T
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ad_connect ps_gpio_i sys_ps7/GPIO_I
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ad_connect ps_gpio_o sys_ps7/GPIO_O
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ad_connect ps_gpio_t sys_ps7/GPIO_T
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ad_connect fixed_io sys_ps7/FIXED_IO
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# spi connections
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ad_connect spi0_csn_2_o sys_ps7/SPI0_SS2_O
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ad_connect spi0_csn_1_o sys_ps7/SPI0_SS1_O
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ad_connect spi0_csn_0_o sys_ps7/SPI0_SS_O
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ad_connect spi0_csn_i sys_ps7/SPI0_SS_I
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ad_connect spi0_clk_i sys_ps7/SPI0_SCLK_I
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ad_connect spi0_clk_o sys_ps7/SPI0_SCLK_O
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ad_connect spi0_sdo_i sys_ps7/SPI0_MOSI_I
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ad_connect spi0_sdo_o sys_ps7/SPI0_MOSI_O
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ad_connect spi0_sdi_i sys_ps7/SPI0_MISO_I
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ad_connect sys_ps7/SPI0_SS_O spi0_csn_0
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ad_connect sys_ps7/SPI0_SS1_O spi0_csn_1
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ad_connect sys_ps7/SPI0_SS2_O spi0_csn_2
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ad_connect sys_ps7/SPI0_SCLK_O spi0_clk
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ad_connect sys_ps7/SPI0_MOSI_O spi0_mosi
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ad_connect sys_ps7/SPI0_MISO_I spi0_miso
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ad_connect sys_ps7/SPI0_SS_I VCC
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ad_connect sys_ps7/SPI0_SCLK_I GND
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ad_connect sys_ps7/SPI0_MOSI_I GND
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ad_connect sys_ps7/SPI1_SS_I spi1_csn
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ad_connect sys_ps7/SPI1_SCLK_I spi1_clk
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ad_connect sys_ps7/SPI1_MOSI_I spi1_mosi
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ad_connect sys_ps7/SPI1_MISO_O spi1_miso
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ad_connect sys_ps7/SPI1_MISO_I GND
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# interrupts
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@ -141,16 +161,6 @@ ad_connect sys_concat_intc/In2 ps_intr_02
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ad_connect sys_concat_intc/In1 ps_intr_01
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ad_connect sys_concat_intc/In0 ps_intr_00
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# iic
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create_bd_intf_port -mode Master -vlnv xilinx.com:interface:iic_rtl:1.0 iic_main
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set axi_iic_main [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_iic:2.0 axi_iic_main]
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ad_connect iic_main axi_iic_main/iic
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ad_cpu_interconnect 0x41600000 axi_iic_main
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ad_cpu_interrupt ps-15 mb-15 axi_iic_main/iic2intc_irpt
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# ad9361
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create_bd_port -dir I rx_clk_in
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@ -213,7 +223,6 @@ ad_connect txnrx axi_ad9361/txnrx
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ad_connect up_enable axi_ad9361/up_enable
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ad_connect up_txnrx axi_ad9361/up_txnrx
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ad_connect axi_ad9361/tdd_sync GND
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ad_connect sys_200m_clk axi_ad9361/delay_clk
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ad_connect axi_ad9361/l_clk axi_ad9361/clk
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@ -261,4 +270,33 @@ ad_connect sys_cpu_resetn axi_ad9361_dac_dma/m_src_axi_aresetn
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ad_cpu_interrupt ps-13 mb-13 axi_ad9361_adc_dma/irq
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ad_cpu_interrupt ps-12 mb-12 axi_ad9361_dac_dma/irq
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# tdd-sync
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set util_ad9361_tdd_sync [create_bd_cell -type ip -vlnv analog.com:user:util_tdd_sync:1.0 util_ad9361_tdd_sync]
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set_property -dict [list CONFIG.TDD_SYNC_PERIOD {10000000}] $util_ad9361_tdd_sync
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create_bd_port -dir I tdd_sync
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ad_connect tdd_sync util_ad9361_tdd_sync/sync_in
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ad_connect sys_cpu_clk util_ad9361_tdd_sync/clk
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ad_connect sys_cpu_resetn util_ad9361_tdd_sync/rstn
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ad_connect util_ad9361_tdd_sync/sync_out axi_ad9361/tdd_sync
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ad_connect util_ad9361_tdd_sync/sync_mode axi_ad9361/tdd_sync_cntr
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# gpio
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create_bd_port -dir I -from 31 -to 0 pl_gpio_i
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create_bd_port -dir O -from 31 -to 0 pl_gpio_o
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create_bd_port -dir O -from 31 -to 0 pl_gpio_t
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set axi_gpio [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio]
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set_property -dict [list CONFIG.C_GPIO_WIDTH {32}] $axi_gpio
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set_property -dict [list CONFIG.C_INTERRUPT_PRESENT {1}] $axi_gpio
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ad_connect pl_gpio_i axi_gpio/gpio_io_i
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ad_connect pl_gpio_o axi_gpio/gpio_io_o
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ad_connect pl_gpio_t axi_gpio/gpio_io_t
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ad_cpu_interconnect 0x41600000 axi_gpio
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ad_cpu_interrupt ps-15 mb-15 axi_gpio/ip2intc_irpt
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@ -1,202 +1,157 @@
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# constraints
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# ad9361 (SWAP == 0x1)
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set_property -dict {PACKAGE_PIN L12 IOSTANDARD LVCMOS18 } [get_ports rx_clk_in]
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set_property -dict {PACKAGE_PIN N13 IOSTANDARD LVCMOS18 } [get_ports rx_frame_in]
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set_property -dict {PACKAGE_PIN H14 IOSTANDARD LVCMOS18 } [get_ports rx_data_in[0]]
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set_property -dict {PACKAGE_PIN J13 IOSTANDARD LVCMOS18 } [get_ports rx_data_in[1]]
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set_property -dict {PACKAGE_PIN G14 IOSTANDARD LVCMOS18 } [get_ports rx_data_in[2]]
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set_property -dict {PACKAGE_PIN H13 IOSTANDARD LVCMOS18 } [get_ports rx_data_in[3]]
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set_property -dict {PACKAGE_PIN G12 IOSTANDARD LVCMOS18 } [get_ports rx_data_in[4]]
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set_property -dict {PACKAGE_PIN H12 IOSTANDARD LVCMOS18 } [get_ports rx_data_in[5]]
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set_property -dict {PACKAGE_PIN G11 IOSTANDARD LVCMOS18 } [get_ports rx_data_in[6]]
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set_property -dict {PACKAGE_PIN J14 IOSTANDARD LVCMOS18 } [get_ports rx_data_in[7]]
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set_property -dict {PACKAGE_PIN J15 IOSTANDARD LVCMOS18 } [get_ports rx_data_in[8]]
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set_property -dict {PACKAGE_PIN K15 IOSTANDARD LVCMOS18 } [get_ports rx_data_in[9]]
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set_property -dict {PACKAGE_PIN H11 IOSTANDARD LVCMOS18 } [get_ports rx_data_in[10]]
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set_property -dict {PACKAGE_PIN J11 IOSTANDARD LVCMOS18 } [get_ports rx_data_in[11]]
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set_property -dict {PACKAGE_PIN L18 IOSTANDARD LVCMOS18} [get_ports rx_clk_in]
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set_property -dict {PACKAGE_PIN N18 IOSTANDARD LVCMOS18} [get_ports rx_frame_in]
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set_property -dict {PACKAGE_PIN L16 IOSTANDARD LVCMOS18} [get_ports rx_data_in[0]]
|
||||
set_property -dict {PACKAGE_PIN K18 IOSTANDARD LVCMOS18} [get_ports rx_data_in[1]]
|
||||
set_property -dict {PACKAGE_PIN L17 IOSTANDARD LVCMOS18} [get_ports rx_data_in[2]]
|
||||
set_property -dict {PACKAGE_PIN J17 IOSTANDARD LVCMOS18} [get_ports rx_data_in[3]]
|
||||
set_property -dict {PACKAGE_PIN M16 IOSTANDARD LVCMOS18} [get_ports rx_data_in[4]]
|
||||
set_property -dict {PACKAGE_PIN J15 IOSTANDARD LVCMOS18} [get_ports rx_data_in[5]]
|
||||
set_property -dict {PACKAGE_PIN K16 IOSTANDARD LVCMOS18} [get_ports rx_data_in[6]]
|
||||
set_property -dict {PACKAGE_PIN J16 IOSTANDARD LVCMOS18} [get_ports rx_data_in[7]]
|
||||
set_property -dict {PACKAGE_PIN N20 IOSTANDARD LVCMOS18} [get_ports rx_data_in[8]]
|
||||
set_property -dict {PACKAGE_PIN K15 IOSTANDARD LVCMOS18} [get_ports rx_data_in[9]]
|
||||
set_property -dict {PACKAGE_PIN N17 IOSTANDARD LVCMOS18} [get_ports rx_data_in[10]]
|
||||
set_property -dict {PACKAGE_PIN M17 IOSTANDARD LVCMOS18} [get_ports rx_data_in[11]]
|
||||
|
||||
set_property -dict {PACKAGE_PIN P10 IOSTANDARD LVCMOS18} [get_ports tx_clk_out]
|
||||
set_property -dict {PACKAGE_PIN L14 IOSTANDARD LVCMOS18} [get_ports tx_frame_out]
|
||||
set_property -dict {PACKAGE_PIN P15 IOSTANDARD LVCMOS18} [get_ports tx_data_out[0]]
|
||||
set_property -dict {PACKAGE_PIN R13 IOSTANDARD LVCMOS18} [get_ports tx_data_out[1]]
|
||||
set_property -dict {PACKAGE_PIN R15 IOSTANDARD LVCMOS18} [get_ports tx_data_out[2]]
|
||||
set_property -dict {PACKAGE_PIN P11 IOSTANDARD LVCMOS18} [get_ports tx_data_out[3]]
|
||||
set_property -dict {PACKAGE_PIN R11 IOSTANDARD LVCMOS18} [get_ports tx_data_out[4]]
|
||||
set_property -dict {PACKAGE_PIN R12 IOSTANDARD LVCMOS18} [get_ports tx_data_out[5]]
|
||||
set_property -dict {PACKAGE_PIN P14 IOSTANDARD LVCMOS18} [get_ports tx_data_out[6]]
|
||||
set_property -dict {PACKAGE_PIN P13 IOSTANDARD LVCMOS18} [get_ports tx_data_out[7]]
|
||||
set_property -dict {PACKAGE_PIN N9 IOSTANDARD LVCMOS18} [get_ports tx_data_out[8]]
|
||||
set_property -dict {PACKAGE_PIN M9 IOSTANDARD LVCMOS18} [get_ports tx_data_out[9]]
|
||||
set_property -dict {PACKAGE_PIN R8 IOSTANDARD LVCMOS18} [get_ports tx_data_out[10]]
|
||||
set_property -dict {PACKAGE_PIN R7 IOSTANDARD LVCMOS18} [get_ports tx_data_out[11]]
|
||||
set_property -dict {PACKAGE_PIN R21 IOSTANDARD LVCMOS18} [get_ports tx_clk_out]
|
||||
set_property -dict {PACKAGE_PIN P22 IOSTANDARD LVCMOS18} [get_ports tx_frame_out]
|
||||
set_property -dict {PACKAGE_PIN N19 IOSTANDARD LVCMOS18} [get_ports tx_data_out[0]]
|
||||
set_property -dict {PACKAGE_PIN M21 IOSTANDARD LVCMOS18} [get_ports tx_data_out[1]]
|
||||
set_property -dict {PACKAGE_PIN P20 IOSTANDARD LVCMOS18} [get_ports tx_data_out[2]]
|
||||
set_property -dict {PACKAGE_PIN P15 IOSTANDARD LVCMOS18} [get_ports tx_data_out[3]]
|
||||
set_property -dict {PACKAGE_PIN P17 IOSTANDARD LVCMOS18} [get_ports tx_data_out[4]]
|
||||
set_property -dict {PACKAGE_PIN P18 IOSTANDARD LVCMOS18} [get_ports tx_data_out[5]]
|
||||
set_property -dict {PACKAGE_PIN R20 IOSTANDARD LVCMOS18} [get_ports tx_data_out[6]]
|
||||
set_property -dict {PACKAGE_PIN P21 IOSTANDARD LVCMOS18} [get_ports tx_data_out[7]]
|
||||
set_property -dict {PACKAGE_PIN M22 IOSTANDARD LVCMOS18} [get_ports tx_data_out[8]]
|
||||
set_property -dict {PACKAGE_PIN T17 IOSTANDARD LVCMOS18} [get_ports tx_data_out[9]]
|
||||
set_property -dict {PACKAGE_PIN N22 IOSTANDARD LVCMOS18} [get_ports tx_data_out[10]]
|
||||
set_property -dict {PACKAGE_PIN N15 IOSTANDARD LVCMOS18} [get_ports tx_data_out[11]]
|
||||
|
||||
set_property -dict {PACKAGE_PIN L15 IOSTANDARD LVCMOS18} [get_ports gpio_status[0]]
|
||||
set_property -dict {PACKAGE_PIN M15 IOSTANDARD LVCMOS18} [get_ports gpio_status[1]]
|
||||
set_property -dict {PACKAGE_PIN N11 IOSTANDARD LVCMOS18} [get_ports gpio_status[2]]
|
||||
set_property -dict {PACKAGE_PIN N12 IOSTANDARD LVCMOS18} [get_ports gpio_status[3]]
|
||||
set_property -dict {PACKAGE_PIN M10 IOSTANDARD LVCMOS18} [get_ports gpio_status[4]]
|
||||
set_property -dict {PACKAGE_PIN M11 IOSTANDARD LVCMOS18} [get_ports gpio_status[5]]
|
||||
set_property -dict {PACKAGE_PIN N7 IOSTANDARD LVCMOS18} [get_ports gpio_status[6]]
|
||||
set_property -dict {PACKAGE_PIN N8 IOSTANDARD LVCMOS18} [get_ports gpio_status[7]]
|
||||
set_property -dict {PACKAGE_PIN AB4 IOSTANDARD LVCMOS18} [get_ports enable]
|
||||
set_property -dict {PACKAGE_PIN AB1 IOSTANDARD LVCMOS18} [get_ports txnrx]
|
||||
set_property -dict {PACKAGE_PIN M19 IOSTANDARD LVCMOS18} [get_ports out_clk]
|
||||
|
||||
set_property -dict {PACKAGE_PIN F13 IOSTANDARD LVCMOS18} [get_ports gpio_ctl[0]]
|
||||
set_property -dict {PACKAGE_PIN F14 IOSTANDARD LVCMOS18} [get_ports gpio_ctl[1]]
|
||||
set_property -dict {PACKAGE_PIN G15 IOSTANDARD LVCMOS18} [get_ports gpio_ctl[2]]
|
||||
set_property -dict {PACKAGE_PIN F15 IOSTANDARD LVCMOS18} [get_ports gpio_ctl[3]]
|
||||
set_property -dict {PACKAGE_PIN U11 IOSTANDARD LVCMOS18} [get_ports gpio_resetb]
|
||||
set_property -dict {PACKAGE_PIN T16 IOSTANDARD LVCMOS18} [get_ports gpio_sync]
|
||||
set_property -dict {PACKAGE_PIN AB2 IOSTANDARD LVCMOS18} [get_ports gpio_en_agc]
|
||||
set_property -dict {PACKAGE_PIN V4 IOSTANDARD LVCMOS18} [get_ports gpio_ctl[0]]
|
||||
set_property -dict {PACKAGE_PIN V5 IOSTANDARD LVCMOS18} [get_ports gpio_ctl[1]]
|
||||
set_property -dict {PACKAGE_PIN U5 IOSTANDARD LVCMOS18} [get_ports gpio_ctl[2]]
|
||||
set_property -dict {PACKAGE_PIN U6 IOSTANDARD LVCMOS18} [get_ports gpio_ctl[3]]
|
||||
set_property -dict {PACKAGE_PIN AB5 IOSTANDARD LVCMOS18} [get_ports gpio_status[0]]
|
||||
set_property -dict {PACKAGE_PIN AB6 IOSTANDARD LVCMOS18} [get_ports gpio_status[1]]
|
||||
set_property -dict {PACKAGE_PIN AB7 IOSTANDARD LVCMOS18} [get_ports gpio_status[2]]
|
||||
set_property -dict {PACKAGE_PIN AA4 IOSTANDARD LVCMOS18} [get_ports gpio_status[3]]
|
||||
set_property -dict {PACKAGE_PIN K20 IOSTANDARD LVCMOS18} [get_ports gpio_status[4]]
|
||||
set_property -dict {PACKAGE_PIN L19 IOSTANDARD LVCMOS18} [get_ports gpio_status[5]]
|
||||
set_property -dict {PACKAGE_PIN V12 IOSTANDARD LVCMOS18} [get_ports gpio_status[6]]
|
||||
set_property -dict {PACKAGE_PIN W12 IOSTANDARD LVCMOS18} [get_ports gpio_status[7]]
|
||||
|
||||
set_property -dict {PACKAGE_PIN L13 IOSTANDARD LVCMOS18} [get_ports gpio_en_agc]
|
||||
set_property -dict {PACKAGE_PIN P9 IOSTANDARD LVCMOS18} [get_ports gpio_resetb]
|
||||
# not-connected?
|
||||
|
||||
set_property -dict {PACKAGE_PIN K12 IOSTANDARD LVCMOS18} [get_ports enable]
|
||||
set_property -dict {PACKAGE_PIN K11 IOSTANDARD LVCMOS18} [get_ports txnrx]
|
||||
set_property -dict {PACKAGE_PIN R18 IOSTANDARD LVCMOS18} [get_ports gpio_rf[0]]
|
||||
set_property -dict {PACKAGE_PIN T18 IOSTANDARD LVCMOS18} [get_ports gpio_rf[1]]
|
||||
set_property -dict {PACKAGE_PIN M15 IOSTANDARD LVCMOS18} [get_ports gpio_rf[2]]
|
||||
set_property -dict {PACKAGE_PIN J18 IOSTANDARD LVCMOS18} [get_ports gpio_rf[3]]
|
||||
set_property -dict {PACKAGE_PIN J20 IOSTANDARD LVCMOS18} [get_ports gpio_rf[4]]
|
||||
set_property -dict {PACKAGE_PIN K19 IOSTANDARD LVCMOS18} [get_ports gpio_rf[5]]
|
||||
set_property -dict {PACKAGE_PIN AB12 IOSTANDARD LVCMOS18} [get_ports gpio_rf[6]]
|
||||
set_property -dict {PACKAGE_PIN T6 IOSTANDARD LVCMOS18} [get_ports gpio_rf[7]]
|
||||
set_property -dict {PACKAGE_PIN R6 IOSTANDARD LVCMOS18} [get_ports gpio_rf[8]]
|
||||
|
||||
set_property -dict {PACKAGE_PIN M14 IOSTANDARD LVCMOS18 PULLTYPE PULLUP} [get_ports iic_scl]
|
||||
set_property -dict {PACKAGE_PIN N14 IOSTANDARD LVCMOS18 PULLTYPE PULLUP} [get_ports iic_sda]
|
||||
# forwarded clocks (not-connected?)
|
||||
|
||||
set_property -dict {PACKAGE_PIN E12 IOSTANDARD LVCMOS18 PULLTYPE PULLUP} [get_ports spi_csn]
|
||||
set_property -dict {PACKAGE_PIN E11 IOSTANDARD LVCMOS18} [get_ports spi_clk]
|
||||
set_property -dict {PACKAGE_PIN E13 IOSTANDARD LVCMOS18} [get_ports spi_mosi]
|
||||
set_property -dict {PACKAGE_PIN F12 IOSTANDARD LVCMOS18} [get_ports spi_miso]
|
||||
set_property -dict {PACKAGE_PIN U4 IOSTANDARD LVCMOS18} [get_ports gpio_tcxo_clk]
|
||||
set_property -dict {PACKAGE_PIN T4 IOSTANDARD LVCMOS18} [get_ports gpio_out_clk]
|
||||
|
||||
set_property -dict {PACKAGE_PIN K13 IOSTANDARD LVCMOS18} [get_ports gpio_bd]
|
||||
set_property -dict {PACKAGE_PIN P8 IOSTANDARD LVCMOS18} [get_ports clk_out]
|
||||
# spi
|
||||
|
||||
set_property -dict {PACKAGE_PIN W6 IOSTANDARD LVCMOS18 PULLTYPE PULLUP} [get_ports spi_csn]
|
||||
set_property -dict {PACKAGE_PIN W5 IOSTANDARD LVCMOS18} [get_ports spi_clk]
|
||||
set_property -dict {PACKAGE_PIN V7 IOSTANDARD LVCMOS18} [get_ports spi_mosi]
|
||||
set_property -dict {PACKAGE_PIN W7 IOSTANDARD LVCMOS18} [get_ports spi_miso]
|
||||
|
||||
create_clock -name rx_clk -period 16 [get_ports rx_clk_in]
|
||||
|
||||
# probably gone in 2016.4
|
||||
# rf filter selects
|
||||
|
||||
create_clock -name clk_fpga_0 -period 10 [get_pins "i_system_wrapper/system_i/sys_ps7/inst/PS7_i/FCLKCLK[0]"]
|
||||
create_clock -name clk_fpga_1 -period 5 [get_pins "i_system_wrapper/system_i/sys_ps7/inst/PS7_i/FCLKCLK[1]"]
|
||||
set_property -dict {PACKAGE_PIN F22 IOSTANDARD LVCMOS33} [get_ports tx_bandsel[0]]
|
||||
set_property -dict {PACKAGE_PIN F21 IOSTANDARD LVCMOS33} [get_ports tx_bandsel[1]]
|
||||
set_property -dict {PACKAGE_PIN H19 IOSTANDARD LVCMOS33} [get_ports tx_bandsel[2]]
|
||||
set_property -dict {PACKAGE_PIN E19 IOSTANDARD LVCMOS33} [get_ports rx_bandsel_1[0]]
|
||||
set_property -dict {PACKAGE_PIN G21 IOSTANDARD LVCMOS33} [get_ports rx_bandsel_1[1]]
|
||||
set_property -dict {PACKAGE_PIN G20 IOSTANDARD LVCMOS33} [get_ports rx_bandsel_1[2]]
|
||||
set_property -dict {PACKAGE_PIN F19 IOSTANDARD LVCMOS33} [get_ports rx_bandsel_1b[0]]
|
||||
set_property -dict {PACKAGE_PIN G19 IOSTANDARD LVCMOS33} [get_ports rx_bandsel_1b[1]]
|
||||
set_property -dict {PACKAGE_PIN A19 IOSTANDARD LVCMOS33} [get_ports rx_bandsel_1c[0]]
|
||||
set_property -dict {PACKAGE_PIN B15 IOSTANDARD LVCMOS33} [get_ports rx_bandsel_1c[1]]
|
||||
set_property -dict {PACKAGE_PIN AB9 IOSTANDARD LVCMOS18} [get_ports rx_bandsel_2[0]]
|
||||
set_property -dict {PACKAGE_PIN AA9 IOSTANDARD LVCMOS18} [get_ports rx_bandsel_2[1]]
|
||||
set_property -dict {PACKAGE_PIN AA8 IOSTANDARD LVCMOS18} [get_ports rx_bandsel_2[2]]
|
||||
set_property -dict {PACKAGE_PIN Y4 IOSTANDARD LVCMOS18} [get_ports rx_bandsel_2b[0]]
|
||||
set_property -dict {PACKAGE_PIN U9 IOSTANDARD LVCMOS18} [get_ports rx_bandsel_2b[1]]
|
||||
set_property -dict {PACKAGE_PIN Y10 IOSTANDARD LVCMOS18} [get_ports rx_bandsel_2c[0]]
|
||||
set_property -dict {PACKAGE_PIN U10 IOSTANDARD LVCMOS18} [get_ports rx_bandsel_2c[1]]
|
||||
|
||||
set_input_jitter clk_fpga_0 0.3
|
||||
set_input_jitter clk_fpga_1 0.15
|
||||
# rf enables
|
||||
|
||||
set_property IOSTANDARD LVCMOS18 [get_ports *fixed_io_mio*]
|
||||
set_property SLEW SLOW [get_ports *fixed_io_mio*]
|
||||
set_property DRIVE 8 [get_ports *fixed_io_mio*]
|
||||
set_property -dict {PACKAGE_PIN D8 PULLTYPE PULLUP} [get_ports fixed_io_mio[ 0]]
|
||||
set_property -dict {PACKAGE_PIN A5 PULLTYPE PULLUP} [get_ports fixed_io_mio[ 1]]
|
||||
set_property -dict {PACKAGE_PIN A8 } [get_ports fixed_io_mio[ 2]]
|
||||
set_property -dict {PACKAGE_PIN A7 } [get_ports fixed_io_mio[ 3]]
|
||||
set_property -dict {PACKAGE_PIN C8 } [get_ports fixed_io_mio[ 4]]
|
||||
set_property -dict {PACKAGE_PIN A9 } [get_ports fixed_io_mio[ 5]]
|
||||
set_property -dict {PACKAGE_PIN A10 } [get_ports fixed_io_mio[ 6]]
|
||||
set_property -dict {PACKAGE_PIN D9 } [get_ports fixed_io_mio[ 7]]
|
||||
set_property -dict {PACKAGE_PIN B6 } [get_ports fixed_io_mio[ 8]]
|
||||
set_property -dict {PACKAGE_PIN B5 PULLTYPE PULLUP} [get_ports fixed_io_mio[ 9]]
|
||||
set_property -dict {PACKAGE_PIN D6 PULLTYPE PULLUP} [get_ports fixed_io_mio[10]]
|
||||
set_property -dict {PACKAGE_PIN B10 PULLTYPE PULLUP} [get_ports fixed_io_mio[11]]
|
||||
set_property -dict {PACKAGE_PIN B7 PULLTYPE PULLUP} [get_ports fixed_io_mio[12]]
|
||||
set_property -dict {PACKAGE_PIN C6 PULLTYPE PULLUP} [get_ports fixed_io_mio[13]]
|
||||
set_property -dict {PACKAGE_PIN B9 PULLTYPE PULLUP} [get_ports fixed_io_mio[14]]
|
||||
set_property -dict {PACKAGE_PIN D10 PULLTYPE PULLUP} [get_ports fixed_io_mio[15]]
|
||||
set_property -dict {PACKAGE_PIN A15 PULLTYPE PULLUP} [get_ports fixed_io_mio[16]]
|
||||
set_property -dict {PACKAGE_PIN D11 PULLTYPE PULLUP} [get_ports fixed_io_mio[17]]
|
||||
set_property -dict {PACKAGE_PIN B15 PULLTYPE PULLUP} [get_ports fixed_io_mio[18]]
|
||||
set_property -dict {PACKAGE_PIN C12 PULLTYPE PULLUP} [get_ports fixed_io_mio[19]]
|
||||
set_property -dict {PACKAGE_PIN E15 PULLTYPE PULLUP} [get_ports fixed_io_mio[20]]
|
||||
set_property -dict {PACKAGE_PIN C11 PULLTYPE PULLUP} [get_ports fixed_io_mio[21]]
|
||||
set_property -dict {PACKAGE_PIN D15 PULLTYPE PULLUP} [get_ports fixed_io_mio[22]]
|
||||
set_property -dict {PACKAGE_PIN A14 PULLTYPE PULLUP} [get_ports fixed_io_mio[23]]
|
||||
set_property -dict {PACKAGE_PIN B14 PULLTYPE PULLUP} [get_ports fixed_io_mio[24]]
|
||||
set_property -dict {PACKAGE_PIN C14 PULLTYPE PULLUP} [get_ports fixed_io_mio[25]]
|
||||
set_property -dict {PACKAGE_PIN A13 PULLTYPE PULLUP} [get_ports fixed_io_mio[26]]
|
||||
set_property -dict {PACKAGE_PIN D14 PULLTYPE PULLUP} [get_ports fixed_io_mio[27]]
|
||||
set_property -dict {PACKAGE_PIN B12 PULLTYPE PULLUP} [get_ports fixed_io_mio[28]]
|
||||
set_property -dict {PACKAGE_PIN D13 PULLTYPE PULLUP} [get_ports fixed_io_mio[29]]
|
||||
set_property -dict {PACKAGE_PIN A12 PULLTYPE PULLUP} [get_ports fixed_io_mio[30]]
|
||||
set_property -dict {PACKAGE_PIN C13 PULLTYPE PULLUP} [get_ports fixed_io_mio[31]]
|
||||
set_property -dict {PACKAGE_PIN G22 IOSTANDARD LVCMOS33} [get_ports tx_enable_1a]
|
||||
set_property -dict {PACKAGE_PIN H22 IOSTANDARD LVCMOS33} [get_ports tx_enable_2a]
|
||||
set_property -dict {PACKAGE_PIN A17 IOSTANDARD LVCMOS33} [get_ports tx_enable_1b]
|
||||
set_property -dict {PACKAGE_PIN B16 IOSTANDARD LVCMOS33} [get_ports tx_enable_2b]
|
||||
|
||||
set_property IOSTANDARD LVCMOS18 [get_ports *fixed_io_ps*]
|
||||
set_property SLEW SLOW [get_ports *fixed_io_ps*]
|
||||
set_property DRIVE 8 [get_ports *fixed_io_ps*]
|
||||
set_property PACKAGE_PIN C7 [get_ports fixed_io_ps_clk]
|
||||
set_property PACKAGE_PIN C9 [get_ports fixed_io_ps_porb]
|
||||
# antennae selects
|
||||
|
||||
set_property IOSTANDARD SSTL15_T_DCI [get_ports *fixed_io_ddr_vr*]
|
||||
set_property SLEW FAST [get_ports *fixed_io_ddr_vr*]
|
||||
set_property PACKAGE_PIN H3 [get_ports fixed_io_ddr_vrp]
|
||||
set_property PACKAGE_PIN J3 [get_ports fixed_io_ddr_vrn]
|
||||
set_property -dict {PACKAGE_PIN C15 IOSTANDARD LVCMOS33} [get_ports txrx1_antsel_v1]
|
||||
set_property -dict {PACKAGE_PIN B17 IOSTANDARD LVCMOS33} [get_ports txrx1_antsel_v2]
|
||||
set_property -dict {PACKAGE_PIN A16 IOSTANDARD LVCMOS33} [get_ports txrx2_antsel_v1]
|
||||
set_property -dict {PACKAGE_PIN E20 IOSTANDARD LVCMOS33} [get_ports txrx2_antsel_v2]
|
||||
set_property -dict {PACKAGE_PIN E18 IOSTANDARD LVCMOS33} [get_ports rx1_antsel_v1]
|
||||
set_property -dict {PACKAGE_PIN F18 IOSTANDARD LVCMOS33} [get_ports rx1_antsel_v2]
|
||||
set_property -dict {PACKAGE_PIN F17 IOSTANDARD LVCMOS33} [get_ports rx2_antsel_v1]
|
||||
set_property -dict {PACKAGE_PIN G17 IOSTANDARD LVCMOS33} [get_ports rx2_antsel_v2]
|
||||
|
||||
set_property IOSTANDARD DIFF_SSTL15 [get_ports *ddr_ck*]
|
||||
set_property SLEW FAST [get_ports *ddr_ck*]
|
||||
set_property PACKAGE_PIN N3 [get_ports ddr_ck_p]
|
||||
set_property PACKAGE_PIN N2 [get_ports ddr_ck_n]
|
||||
# fancy stuff
|
||||
|
||||
set_property IOSTANDARD SSTL15 [get_ports *ddr_addr*]
|
||||
set_property SLEW SLOW [get_ports *ddr_addr*]
|
||||
set_property PACKAGE_PIN P1 [get_ports ddr_addr[0]]
|
||||
set_property PACKAGE_PIN N1 [get_ports ddr_addr[1]]
|
||||
set_property PACKAGE_PIN M1 [get_ports ddr_addr[2]]
|
||||
set_property PACKAGE_PIN M4 [get_ports ddr_addr[3]]
|
||||
set_property PACKAGE_PIN P3 [get_ports ddr_addr[4]]
|
||||
set_property PACKAGE_PIN P4 [get_ports ddr_addr[5]]
|
||||
set_property PACKAGE_PIN P5 [get_ports ddr_addr[6]]
|
||||
set_property PACKAGE_PIN M5 [get_ports ddr_addr[7]]
|
||||
set_property PACKAGE_PIN P6 [get_ports ddr_addr[8]]
|
||||
set_property PACKAGE_PIN N4 [get_ports ddr_addr[9]]
|
||||
set_property PACKAGE_PIN J1 [get_ports ddr_addr[10]]
|
||||
set_property PACKAGE_PIN L2 [get_ports ddr_addr[11]]
|
||||
set_property PACKAGE_PIN M2 [get_ports ddr_addr[12]]
|
||||
set_property PACKAGE_PIN K2 [get_ports ddr_addr[13]]
|
||||
set_property PACKAGE_PIN K1 [get_ports ddr_addr[14]]
|
||||
set_property -dict {PACKAGE_PIN Y11 IOSTANDARD LVCMOS18} [get_ports txrx1_tx_led]
|
||||
set_property -dict {PACKAGE_PIN AB10 IOSTANDARD LVCMOS18} [get_ports txrx1_rx_led]
|
||||
set_property -dict {PACKAGE_PIN U12 IOSTANDARD LVCMOS18} [get_ports txrx2_tx_led]
|
||||
set_property -dict {PACKAGE_PIN AB11 IOSTANDARD LVCMOS18} [get_ports txrx2_rx_led]
|
||||
set_property -dict {PACKAGE_PIN AA12 IOSTANDARD LVCMOS18} [get_ports rx1_rx_led]
|
||||
set_property -dict {PACKAGE_PIN AA11 IOSTANDARD LVCMOS18} [get_ports rx2_rx_led]
|
||||
|
||||
set_property IOSTANDARD SSTL15 [get_ports *ddr_ba*]
|
||||
set_property SLEW SLOW [get_ports *ddr_ba*]
|
||||
set_property PACKAGE_PIN M6 [get_ports ddr_ba[0]]
|
||||
set_property PACKAGE_PIN R1 [get_ports ddr_ba[1]]
|
||||
set_property PACKAGE_PIN N6 [get_ports ddr_ba[2]]
|
||||
# xtal tuning (ad5662)
|
||||
|
||||
set_property IOSTANDARD SSTL15 [get_ports ddr_reset_n]
|
||||
set_property SLEW FAST [get_ports ddr_reset_n]
|
||||
set_property PACKAGE_PIN L4 [get_ports ddr_reset_n]
|
||||
set_property IOSTANDARD SSTL15 [get_ports ddr_cs_n]
|
||||
set_property SLEW SLOW [get_ports ddr_cs_n]
|
||||
set_property PACKAGE_PIN R2 [get_ports ddr_cs_n]
|
||||
set_property IOSTANDARD SSTL15 [get_ports ddr_ras_n]
|
||||
set_property SLEW SLOW [get_ports ddr_ras_n]
|
||||
set_property PACKAGE_PIN R6 [get_ports ddr_ras_n]
|
||||
set_property IOSTANDARD SSTL15 [get_ports ddr_cas_n]
|
||||
set_property SLEW SLOW [get_ports ddr_cas_n]
|
||||
set_property PACKAGE_PIN R5 [get_ports ddr_cas_n]
|
||||
set_property IOSTANDARD SSTL15 [get_ports ddr_we_n]
|
||||
set_property SLEW SLOW [get_ports ddr_we_n]
|
||||
set_property PACKAGE_PIN R3 [get_ports ddr_we_n]
|
||||
set_property IOSTANDARD SSTL15 [get_ports ddr_cke]
|
||||
set_property SLEW SLOW [get_ports ddr_cke]
|
||||
set_property PACKAGE_PIN L3 [get_ports ddr_cke]
|
||||
set_property IOSTANDARD SSTL15 [get_ports ddr_odt]
|
||||
set_property SLEW SLOW [get_ports ddr_odt]
|
||||
set_property PACKAGE_PIN K3 [get_ports ddr_odt]
|
||||
set_property -dict {PACKAGE_PIN K21 IOSTANDARD LVCMOS18} [get_ports tcxo_dac_csn]
|
||||
set_property -dict {PACKAGE_PIN L22 IOSTANDARD LVCMOS18} [get_ports tcxo_dac_clk]
|
||||
set_property -dict {PACKAGE_PIN L21 IOSTANDARD LVCMOS18} [get_ports tcxo_dac_mosi]
|
||||
set_property -dict {PACKAGE_PIN M20 IOSTANDARD LVCMOS18} [get_ports tcxo_clk]
|
||||
|
||||
set_property IOSTANDARD SSTL15_T_DCI [get_ports *ddr_dq[*]]
|
||||
set_property SLEW FAST [get_ports *ddr_dq[*]]
|
||||
set_property PACKAGE_PIN D4 [get_ports ddr_dq[0]]
|
||||
set_property PACKAGE_PIN A2 [get_ports ddr_dq[1]]
|
||||
set_property PACKAGE_PIN C4 [get_ports ddr_dq[2]]
|
||||
set_property PACKAGE_PIN C1 [get_ports ddr_dq[3]]
|
||||
set_property PACKAGE_PIN B4 [get_ports ddr_dq[4]]
|
||||
set_property PACKAGE_PIN A4 [get_ports ddr_dq[5]]
|
||||
set_property PACKAGE_PIN C3 [get_ports ddr_dq[6]]
|
||||
set_property PACKAGE_PIN A3 [get_ports ddr_dq[7]]
|
||||
set_property PACKAGE_PIN E1 [get_ports ddr_dq[8]]
|
||||
set_property PACKAGE_PIN D1 [get_ports ddr_dq[9]]
|
||||
set_property PACKAGE_PIN E2 [get_ports ddr_dq[10]]
|
||||
set_property PACKAGE_PIN E3 [get_ports ddr_dq[11]]
|
||||
set_property PACKAGE_PIN F3 [get_ports ddr_dq[12]]
|
||||
set_property PACKAGE_PIN G1 [get_ports ddr_dq[13]]
|
||||
set_property PACKAGE_PIN H1 [get_ports ddr_dq[14]]
|
||||
set_property PACKAGE_PIN H2 [get_ports ddr_dq[15]]
|
||||
set_property IOSTANDARD SSTL15_T_DCI [get_ports *ddr_dm[*]]
|
||||
set_property SLEW FAST [get_ports *ddr_dm[*]]
|
||||
set_property PACKAGE_PIN B1 [get_ports ddr_dm[0]]
|
||||
set_property PACKAGE_PIN D3 [get_ports ddr_dm[1]]
|
||||
set_property IOSTANDARD DIFF_SSTL15_T_DCI [get_ports *ddr_dqs*]
|
||||
set_property SLEW FAST [get_ports *ddr_dqs*]
|
||||
set_property PACKAGE_PIN C2 [get_ports ddr_dqs_p[0]]
|
||||
set_property PACKAGE_PIN B2 [get_ports ddr_dqs_n[0]]
|
||||
set_property PACKAGE_PIN G2 [get_ports ddr_dqs_p[1]]
|
||||
set_property PACKAGE_PIN F2 [get_ports ddr_dqs_n[1]]
|
||||
# board power
|
||||
|
||||
set_property -dict {PACKAGE_PIN A22 IOSTANDARD LVCMOS33} [get_ports avr_csn]
|
||||
set_property -dict {PACKAGE_PIN D22 IOSTANDARD LVCMOS33} [get_ports avr_clk]
|
||||
set_property -dict {PACKAGE_PIN A21 IOSTANDARD LVCMOS33} [get_ports avr_mosi]
|
||||
set_property -dict {PACKAGE_PIN C22 IOSTANDARD LVCMOS33} [get_ports avr_miso]
|
||||
set_property -dict {PACKAGE_PIN B22 IOSTANDARD LVCMOS33} [get_ports avr_irq]
|
||||
|
||||
set_property -dict {PACKAGE_PIN E21 IOSTANDARD LVCMOS33} [get_ports pwr_switch]
|
||||
|
||||
# gps-sync
|
||||
|
||||
set_property -dict {PACKAGE_PIN Y9 IOSTANDARD LVCMOS18} [get_ports pps_gps]
|
||||
set_property -dict {PACKAGE_PIN D18 IOSTANDARD LVCMOS33} [get_ports pps_ext]
|
||||
|
||||
# board-gpio
|
||||
|
||||
set_property -dict {PACKAGE_PIN E16 IOSTANDARD LVCMOS33} [get_ports gpio_bd[0]]
|
||||
set_property -dict {PACKAGE_PIN C18 IOSTANDARD LVCMOS33} [get_ports gpio_bd[1]]
|
||||
set_property -dict {PACKAGE_PIN D17 IOSTANDARD LVCMOS33} [get_ports gpio_bd[2]]
|
||||
set_property -dict {PACKAGE_PIN D16 IOSTANDARD LVCMOS33} [get_ports gpio_bd[3]]
|
||||
set_property -dict {PACKAGE_PIN D15 IOSTANDARD LVCMOS33} [get_ports gpio_bd[4]]
|
||||
set_property -dict {PACKAGE_PIN E15 IOSTANDARD LVCMOS33} [get_ports gpio_bd[5]]
|
||||
|
||||
|
|
|
|||
|
|
@ -46,10 +46,10 @@ module system_top (
|
|||
inout ddr_ck_p,
|
||||
inout ddr_cke,
|
||||
inout ddr_cs_n,
|
||||
inout [ 1:0] ddr_dm,
|
||||
inout [15:0] ddr_dq,
|
||||
inout [ 1:0] ddr_dqs_n,
|
||||
inout [ 1:0] ddr_dqs_p,
|
||||
inout [ 3:0] ddr_dm,
|
||||
inout [31:0] ddr_dq,
|
||||
inout [ 3:0] ddr_dqs_n,
|
||||
inout [ 3:0] ddr_dqs_p,
|
||||
inout ddr_odt,
|
||||
inout ddr_ras_n,
|
||||
inout ddr_reset_n,
|
||||
|
|
@ -57,16 +57,11 @@ module system_top (
|
|||
|
||||
inout fixed_io_ddr_vrn,
|
||||
inout fixed_io_ddr_vrp,
|
||||
inout [31:0] fixed_io_mio,
|
||||
inout [53:0] fixed_io_mio,
|
||||
inout fixed_io_ps_clk,
|
||||
inout fixed_io_ps_porb,
|
||||
inout fixed_io_ps_srstb,
|
||||
|
||||
inout iic_scl,
|
||||
inout iic_sda,
|
||||
|
||||
inout gpio_bd,
|
||||
|
||||
input rx_clk_in,
|
||||
input rx_frame_in,
|
||||
input [11:0] rx_data_in,
|
||||
|
|
@ -76,36 +71,177 @@ module system_top (
|
|||
|
||||
output enable,
|
||||
output txnrx,
|
||||
input clk_out,
|
||||
input out_clk,
|
||||
|
||||
inout gpio_resetb,
|
||||
inout gpio_en_agc,
|
||||
inout [ 3:0] gpio_ctl,
|
||||
inout [ 7:0] gpio_status,
|
||||
output gpio_resetb,
|
||||
output gpio_sync,
|
||||
output gpio_en_agc,
|
||||
output [ 3:0] gpio_ctl,
|
||||
input [ 7:0] gpio_status,
|
||||
inout [ 8:0] gpio_rf,
|
||||
output gpio_tcxo_clk,
|
||||
output gpio_out_clk,
|
||||
|
||||
output spi_csn,
|
||||
output spi_clk,
|
||||
output spi_mosi,
|
||||
input spi_miso);
|
||||
input spi_miso,
|
||||
|
||||
output [ 2:0] tx_bandsel,
|
||||
output [ 2:0] rx_bandsel_1,
|
||||
output [ 1:0] rx_bandsel_1b,
|
||||
output [ 1:0] rx_bandsel_1c,
|
||||
output [ 2:0] rx_bandsel_2,
|
||||
output [ 1:0] rx_bandsel_2b,
|
||||
output [ 1:0] rx_bandsel_2c,
|
||||
|
||||
output tx_enable_1a,
|
||||
output tx_enable_2a,
|
||||
output tx_enable_1b,
|
||||
output tx_enable_2b,
|
||||
|
||||
output txrx1_antsel_v1,
|
||||
output txrx1_antsel_v2,
|
||||
output txrx2_antsel_v1,
|
||||
output txrx2_antsel_v2,
|
||||
output rx1_antsel_v1,
|
||||
output rx1_antsel_v2,
|
||||
output rx2_antsel_v1,
|
||||
output rx2_antsel_v2,
|
||||
|
||||
output txrx1_tx_led,
|
||||
output txrx1_rx_led,
|
||||
output txrx2_tx_led,
|
||||
output txrx2_rx_led,
|
||||
output rx1_rx_led,
|
||||
output rx2_rx_led,
|
||||
|
||||
output tcxo_dac_csn,
|
||||
output tcxo_dac_clk,
|
||||
output tcxo_dac_mosi,
|
||||
input tcxo_clk,
|
||||
|
||||
input avr_csn,
|
||||
input avr_clk,
|
||||
input avr_mosi,
|
||||
output avr_miso,
|
||||
output avr_irq,
|
||||
|
||||
input pwr_switch,
|
||||
|
||||
input pps_gps,
|
||||
input pps_ext,
|
||||
|
||||
inout [ 5:0] gpio_bd);
|
||||
|
||||
// internal signals
|
||||
|
||||
wire [16:0] gpio_i;
|
||||
wire [16:0] gpio_o;
|
||||
wire [16:0] gpio_t;
|
||||
wire pps_s;
|
||||
wire [31:0] pl_gpio_i;
|
||||
wire [31:0] pl_gpio_o;
|
||||
wire [31:0] pl_gpio_t;
|
||||
wire [63:0] ps_gpio_i;
|
||||
wire [63:0] ps_gpio_o;
|
||||
wire [63:0] ps_gpio_t;
|
||||
|
||||
// assignments
|
||||
|
||||
assign pps_s = pps_gps | pps_ext;
|
||||
assign tcxo_dac_clk = spi_clk;
|
||||
assign tcxo_dac_mosi = spi_mosi;
|
||||
|
||||
// gpio-rf (pl)
|
||||
|
||||
assign gpio_tcxo_clk = tcxo_clk;
|
||||
assign gpio_out_clk = out_clk;
|
||||
assign pl_gpio_i[31:9] = pl_gpio_o[31:9];
|
||||
|
||||
ad_iobuf #(.DATA_WIDTH(9)) i_iobuf_rf (
|
||||
.dio_t (pl_gpio_t[8:0]),
|
||||
.dio_i (pl_gpio_o[8:0]),
|
||||
.dio_o (pl_gpio_i[8:0]),
|
||||
.dio_p (gpio_rf));
|
||||
|
||||
// gpio[63:56] - antennae selects
|
||||
|
||||
assign ps_gpio_i[63:56] = ps_gpio_o[63:56];
|
||||
assign txrx1_antsel_v1 = ps_gpio_o[63];
|
||||
assign txrx1_antsel_v2 = ps_gpio_o[62];
|
||||
assign txrx2_antsel_v1 = ps_gpio_o[61];
|
||||
assign txrx2_antsel_v2 = ps_gpio_o[60];
|
||||
assign rx1_antsel_v1 = ps_gpio_o[59];
|
||||
assign rx1_antsel_v2 = ps_gpio_o[58];
|
||||
assign rx2_antsel_v1 = ps_gpio_o[57];
|
||||
assign rx2_antsel_v2 = ps_gpio_o[56];
|
||||
|
||||
// gpio[55:48] - antennae leds
|
||||
|
||||
assign ps_gpio_i[55:49] = ps_gpio_o[55:49];
|
||||
assign txrx1_tx_led = ps_gpio_o[55];
|
||||
assign txrx1_rx_led = ps_gpio_o[54];
|
||||
assign txrx2_tx_led = ps_gpio_o[53];
|
||||
assign txrx2_rx_led = ps_gpio_o[52];
|
||||
assign rx1_rx_led = ps_gpio_o[51];
|
||||
assign rx2_rx_led = ps_gpio_o[50];
|
||||
|
||||
// gpio[48:32] - ad9361
|
||||
|
||||
assign ps_gpio_i[48:44] = ps_gpio_o[48:44];
|
||||
assign gpio_resetb = ps_gpio_o[46];
|
||||
assign gpio_sync = ps_gpio_o[45];
|
||||
assign gpio_en_agc = ps_gpio_o[44];
|
||||
|
||||
assign ps_gpio_i[43:40] = ps_gpio_o[43:40];
|
||||
assign gpio_ctl = ps_gpio_o[43:40];
|
||||
|
||||
assign ps_gpio_i[39:32] = gpio_status;
|
||||
|
||||
// gpio[31:28] - tx_enable
|
||||
|
||||
assign ps_gpio_i[31:28] = ps_gpio_o[31:28];
|
||||
|
||||
assign tx_enable_1a = ps_gpio_o[31];
|
||||
assign tx_enable_2a = ps_gpio_o[30];
|
||||
assign tx_enable_1b = ps_gpio_o[29];
|
||||
assign tx_enable_2b = ps_gpio_o[28];
|
||||
|
||||
// gpio[27:24] - tx_bandsel
|
||||
|
||||
assign ps_gpio_i[27:24] = ps_gpio_o[27:24];
|
||||
|
||||
assign tx_bandsel = ps_gpio_o[26:24];
|
||||
|
||||
// gpio[23:16] - rx_bandsel(1)
|
||||
|
||||
assign ps_gpio_i[23:16] = ps_gpio_o[23:16];
|
||||
|
||||
assign rx_bandsel_1 = ps_gpio_o[22:20];
|
||||
assign rx_bandsel_1b = ps_gpio_o[19:18];
|
||||
assign rx_bandsel_1c = ps_gpio_o[17:16];
|
||||
|
||||
// gpio[15:8] - rx_bandsel(2)
|
||||
|
||||
assign ps_gpio_i[15:8] = ps_gpio_o[15:8];
|
||||
|
||||
assign rx_bandsel_2 = ps_gpio_o[14:12];
|
||||
assign rx_bandsel_2b = ps_gpio_o[11:10];
|
||||
assign rx_bandsel_2c = ps_gpio_o[9:8];
|
||||
|
||||
// gpio[7:0] - board stuff (+ pwr_switch, avr_irq)
|
||||
|
||||
assign ps_gpio_i[7] = ps_gpio_o[7];
|
||||
assign avr_irq = ps_gpio_o[7];
|
||||
|
||||
assign ps_gpio_i[6] = pwr_switch;
|
||||
|
||||
ad_iobuf #(.DATA_WIDTH(6)) i_iobuf_bd (
|
||||
.dio_t (ps_gpio_t[5:0]),
|
||||
.dio_i (ps_gpio_o[5:0]),
|
||||
.dio_o (ps_gpio_i[5:0]),
|
||||
.dio_p (gpio_bd));
|
||||
|
||||
// instantiations
|
||||
|
||||
ad_iobuf #(.DATA_WIDTH(15)) i_iobuf (
|
||||
.dio_t (gpio_t[14:0]),
|
||||
.dio_i (gpio_o[14:0]),
|
||||
.dio_o (gpio_i[14:0]),
|
||||
.dio_p ({ gpio_bd, // 14:14
|
||||
gpio_resetb, // 13:13
|
||||
gpio_en_agc, // 12:12
|
||||
gpio_ctl, // 11: 8
|
||||
gpio_status})); // 7: 0
|
||||
|
||||
system_wrapper i_system_wrapper (
|
||||
.ddr_addr (ddr_addr),
|
||||
.ddr_ba (ddr_ba),
|
||||
|
|
@ -129,11 +265,12 @@ module system_top (
|
|||
.fixed_io_ps_clk (fixed_io_ps_clk),
|
||||
.fixed_io_ps_porb (fixed_io_ps_porb),
|
||||
.fixed_io_ps_srstb (fixed_io_ps_srstb),
|
||||
.gpio_i (gpio_i),
|
||||
.gpio_o (gpio_o),
|
||||
.gpio_t (gpio_t),
|
||||
.iic_main_scl_io (iic_scl),
|
||||
.iic_main_sda_io (iic_sda),
|
||||
.pl_gpio_i (pl_gpio_i),
|
||||
.pl_gpio_o (pl_gpio_o),
|
||||
.pl_gpio_t (pl_gpio_t),
|
||||
.ps_gpio_i (ps_gpio_i),
|
||||
.ps_gpio_o (ps_gpio_o),
|
||||
.ps_gpio_t (ps_gpio_t),
|
||||
.ps_intr_00 (1'b0),
|
||||
.ps_intr_01 (1'b0),
|
||||
.ps_intr_02 (1'b0),
|
||||
|
|
@ -150,21 +287,23 @@ module system_top (
|
|||
.rx_clk_in (rx_clk_in),
|
||||
.rx_data_in (rx_data_in),
|
||||
.rx_frame_in (rx_frame_in),
|
||||
.spi0_clk_i (1'b0),
|
||||
.spi0_clk_o (spi_clk),
|
||||
.spi0_csn_0_o (spi_csn),
|
||||
.spi0_csn_1_o (),
|
||||
.spi0_csn_2_o (),
|
||||
.spi0_csn_i (1'b1),
|
||||
.spi0_sdi_i (spi_miso),
|
||||
.spi0_sdo_i (1'b0),
|
||||
.spi0_sdo_o (spi_mosi),
|
||||
.spi0_clk (spi_clk),
|
||||
.spi0_csn_0 (spi_csn),
|
||||
.spi0_csn_1 (tcxo_dac_csn),
|
||||
.spi0_csn_2 (),
|
||||
.spi0_miso (spi_miso),
|
||||
.spi0_mosi (spi_mosi),
|
||||
.spi1_clk (avr_clk),
|
||||
.spi1_csn (avr_csn),
|
||||
.spi1_miso (avr_miso),
|
||||
.spi1_mosi (avr_mosi),
|
||||
.tdd_sync (pps_s),
|
||||
.tx_clk_out (tx_clk_out),
|
||||
.tx_data_out (tx_data_out),
|
||||
.tx_frame_out (tx_frame_out),
|
||||
.txnrx (txnrx),
|
||||
.up_enable (gpio_o[15]),
|
||||
.up_txnrx (gpio_o[16]));
|
||||
.up_enable (ps_gpio_o[47]),
|
||||
.up_txnrx (ps_gpio_o[48]));
|
||||
|
||||
endmodule
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue