From c9c05e21c2bc32e2dc6d0e15d989b77f22b9a127 Mon Sep 17 00:00:00 2001
From: Adrian Costina <adrian.costina@analog.com>
Date: Wed, 13 May 2015 16:34:06 +0300
Subject: [PATCH] axi_dmac: Updated constraints to cover cases when the
 hierarchy is rebuilt by synthesis

---
 library/axi_dmac/axi_dmac_constr.xdc | 76 ++++++++++++++--------------
 1 file changed, 38 insertions(+), 38 deletions(-)

diff --git a/library/axi_dmac/axi_dmac_constr.xdc b/library/axi_dmac/axi_dmac_constr.xdc
index fff9d1068..e3e8e0ac1 100644
--- a/library/axi_dmac/axi_dmac_constr.xdc
+++ b/library/axi_dmac/axi_dmac_constr.xdc
@@ -12,8 +12,8 @@ set async_dest_to_src_clk [expr {$src_clk != $dest_clk ? $dest_clk : {}}]
 set async_src_to_dest_clk [expr {$src_clk != $dest_clk ? $src_clk : {}}]
 
 set_property ASYNC_REG TRUE \
-	[get_cells -quiet -hier cdc_sync_stage1_reg*] \
-	[get_cells -quiet -hier cdc_sync_stage2_reg*]
+	[get_cells -quiet -hier *cdc_sync_stage1_reg*] \
+	[get_cells -quiet -hier *cdc_sync_stage2_reg*]
 
 #proc get_flops {name inst} {
 #	return [get_cells -hier $name \
@@ -21,18 +21,18 @@ set_property ASYNC_REG TRUE \
 #}
 #
 #proc set_single_bit_cdc_constraints {name clk} {
-#	set_false_path -from $clk -to [get_flops cdc_sync_stage1_reg* ${name}]
+#	set_false_path -from $clk -to [get_flops *cdc_sync_stage1_reg* ${name}]
 #}
 #
 #proc set_multi_bit_cdc_constraints {name clk} {
-#	set_max_delay -from $clk -to [get_flops cdc_sync_stage1_reg* ${name}] \
+#	set_max_delay -from $clk -to [get_flops *cdc_sync_stage1_reg* ${name}] \
 #		[get_property PERIOD $clk] -datapath_only
 #}
 #
 #proc set_fifo_cdc_constraints {name clk_a clk_b} {
 #	set_multi_bit_cdc_constraints ${name}/i_waddr_sync $clk_a
 #	set_multi_bit_cdc_constraints ${name}/i_raddr_sync $clk_b
-#	set_max_delay -from [get_flops cdc_sync_fifo_ram_reg* ${name}] -to $clk_b [get_property PERIOD $clk_b] -datapath_only
+#	set_max_delay -from [get_flops *cdc_sync_fifo_ram_reg* ${name}] -to $clk_b [get_property PERIOD $clk_b] -datapath_only
 #}
 
 #set_multi_bit_constraints i_sync_src_request_id $req_clk
@@ -41,17 +41,17 @@ set_property ASYNC_REG TRUE \
 
 set_max_delay -quiet \
 	-from $async_req_to_src_clk \
-	-to [get_cells -quiet -hier cdc_sync_stage1_reg* \
+	-to [get_cells -quiet -hier *cdc_sync_stage1_reg* \
 		-filter {NAME =~ *i_sync_src_request_id* && PRIMITIVE_SUBGROUP == flop}] \
 	[get_property PERIOD $req_clk] -datapath_only
 set_max_delay -quiet \
 	-from $async_src_to_dest_clk \
-	-to [get_cells -quiet -hier cdc_sync_stage1_reg* \
+	-to [get_cells -quiet -hier *cdc_sync_stage1_reg* \
 		-filter {NAME =~ *i_sync_dest_request_id* && PRIMITIVE_SUBGROUP == flop}] \
 	[get_property PERIOD $src_clk] -datapath_only
 set_max_delay -quiet \
 	-from $async_dest_to_req_clk \
-	-to [get_cells -hier cdc_sync_stage1_reg* \
+	-to [get_cells -hier *cdc_sync_stage1_reg* \
 		-filter {NAME =~ *i_sync_req_response_id* && PRIMITIVE_SUBGROUP == flop}] \
 	[get_property PERIOD $dest_clk] -datapath_only
 
@@ -62,19 +62,19 @@ set_max_delay -quiet \
 
 set_false_path -quiet \
 	-from $async_src_to_req_clk \
-	-to [get_cells -quiet -hier cdc_sync_stage1_reg* \
+	-to [get_cells -quiet -hier *cdc_sync_stage1_reg* \
 		-filter {NAME =~ *i_sync_status_src* && PRIMITIVE_SUBGROUP == flop}]
 set_false_path -quiet \
 	-from $async_req_to_src_clk \
-	-to [get_cells -quiet -hier cdc_sync_stage1_reg* \
+	-to [get_cells -quiet -hier *cdc_sync_stage1_reg* \
 		-filter {NAME =~ *i_sync_control_src* && PRIMITIVE_SUBGROUP == flop}]
 set_false_path -quiet \
 	-from $async_dest_to_req_clk \
-	-to [get_cells -quiet -hier cdc_sync_stage1_reg* \
+	-to [get_cells -quiet -hier *cdc_sync_stage1_reg* \
 		-filter {NAME =~ *i_sync_status_dest* && PRIMITIVE_SUBGROUP == flop}]
 set_false_path -quiet \
 	-from $async_req_to_dest_clk \
-	-to [get_cells -quiet -hier cdc_sync_stage1_reg* \
+	-to [get_cells -quiet -hier *cdc_sync_stage1_reg* \
 		-filter {NAME =~ *i_sync_control_dest* && PRIMITIVE_SUBGROUP == flop}]
 
 #set_fifo_cdc_constraints i_dest_req_fifo $req_clk $dest_clk
@@ -84,88 +84,88 @@ set_false_path -quiet \
 
 set_max_delay -quiet \
 	-from $async_req_to_dest_clk \
-	-to [get_cells -quiet -hier cdc_sync_stage1_reg* \
+	-to [get_cells -quiet -hier *cdc_sync_stage1_reg* \
 		-filter {NAME =~ *i_dest_req_fifo/i_waddr_sync* && PRIMITIVE_SUBGROUP == flop}] \
 	[get_property PERIOD $req_clk] -datapath_only
 set_max_delay -quiet \
 	-from $async_dest_to_req_clk \
-	-to [get_cells -quiet -hier cdc_sync_stage1_reg* \
+	-to [get_cells -quiet -hier *cdc_sync_stage1_reg* \
 		-filter {NAME =~ *i_dest_req_fifo/i_raddr_sync* && PRIMITIVE_SUBGROUP == flop}] \
 	[get_property PERIOD $dest_clk] -datapath_only
 set_max_delay -quiet \
-	-from [get_cells -quiet -hier cdc_sync_fifo_ram_reg* \
+	-from [get_cells -quiet -hier *cdc_sync_fifo_ram_reg* \
 		-filter {NAME =~ *i_dest_req_fifo* && PRIMITIVE_SUBGROUP == flop}] \
 	-to $async_dest_to_req_clk \
 	[get_property PERIOD $dest_clk] -datapath_only
 
 set_max_delay -quiet \
 	-from $async_dest_to_req_clk \
-	-to [get_cells -quiet -hier cdc_sync_stage1_reg* \
+	-to [get_cells -quiet -hier *cdc_sync_stage1_reg* \
 		-filter {NAME =~ *i_dest_response_fifo/i_waddr_sync* && PRIMITIVE_SUBGROUP == flop}] \
 	[get_property PERIOD $dest_clk] -datapath_only
 set_max_delay -quiet \
 	-from $async_req_to_dest_clk \
-	-to [get_cells -quiet -hier cdc_sync_stage1_reg* \
+	-to [get_cells -quiet -hier *cdc_sync_stage1_reg* \
 		-filter {NAME =~ *i_dest_response_fifo/i_raddr_sync* && PRIMITIVE_SUBGROUP == flop}] \
 	[get_property PERIOD $req_clk] -datapath_only
 set_max_delay -quiet \
-	-from [get_cells -quiet -hier cdc_sync_fifo_ram_reg* \
+	-from [get_cells -quiet -hier *cdc_sync_fifo_ram_reg* \
 		-filter {NAME =~ *i_dest_response_fifo* && PRIMITIVE_SUBGROUP == flop}] \
 	-to $async_req_to_dest_clk \
 	[get_property PERIOD $req_clk] -datapath_only
 
 set_max_delay -quiet \
 	-from $async_req_to_src_clk \
-	-to [get_cells -quiet -hier cdc_sync_stage1_reg* \
+	-to [get_cells -quiet -hier *cdc_sync_stage1_reg* \
 		-filter {NAME =~ *i_src_req_fifo/i_waddr_sync* && PRIMITIVE_SUBGROUP == flop}] \
 	[get_property PERIOD $req_clk] -datapath_only
 set_max_delay -quiet \
 	-from $async_src_to_req_clk \
-	-to [get_cells -quiet -hier cdc_sync_stage1_reg* \
+	-to [get_cells -quiet -hier *cdc_sync_stage1_reg* \
 		-filter {NAME =~ *i_src_req_fifo/i_raddr_sync* && PRIMITIVE_SUBGROUP == flop}] \
 	[get_property PERIOD $src_clk] -datapath_only
 set_max_delay -quiet \
-	-from [get_cells -quiet -hier cdc_sync_fifo_ram_reg* \
+	-from [get_cells -quiet -hier *cdc_sync_fifo_ram_reg* \
 		-filter {NAME =~ *i_src_req_fifo* && PRIMITIVE_SUBGROUP == flop}] \
 	-to $async_src_to_req_clk \
 	[get_property PERIOD $src_clk] -datapath_only
 
 #set_max_delay \
 #	-from $src_clk \
-#	-to [get_cells -hier cdc_sync_stage1_reg* \
+#	-to [get_cells -hier *cdc_sync_stage1_reg* \
 #		-filter {NAME =~ *i_src_response_fifo/i_waddr_sync* && PRIMITIVE_SUBGROUP == flop}] \
 #	[get_property PERIOD $src_clk] -datapath_only
 #set_max_delay \
 #	-from $req_clk \
-#	-to [get_cells -hier cdc_sync_stage1_reg* \
+#	-to [get_cells -hier *cdc_sync_stage1_reg* \
 #		-filter {NAME =~ *i_src_response_fifo/i_raddr_sync* && PRIMITIVE_SUBGROUP == flop}] \
 #	[get_property PERIOD $req_clk] -datapath_only
 #set_max_delay \
-#	-from [get_cells -hier cdc_sync_fifo_ram_reg* \
+#	-from [get_cells -hier *cdc_sync_fifo_ram_reg* \
 #		-filter {NAME =~ *i_src_response_fifo* && PRIMITIVE_SUBGROUP == flop}] \
 #	-to $req_clk \
 #	[get_property PERIOD $req_clk] -datapath_only
 
-#set_max_delay -from [get_flops eot_mem_reg* i_request_arb] -to $src_clk [get_property PERIOD $src_clk] -datapath_only
-#set_max_delay -from [get_flops eot_mem_reg* i_request_arb] -to $dest_clk [get_property PERIOD $dest_clk] -datapath_only
+#set_max_delay -from [get_flops *eot_mem_reg* i_request_arb] -to $src_clk [get_property PERIOD $src_clk] -datapath_only
+#set_max_delay -from [get_flops *eot_mem_reg* i_request_arb] -to $dest_clk [get_property PERIOD $dest_clk] -datapath_only
 set_max_delay -quiet \
-	-from [get_cells -quiet -hier eot_mem_reg* \
+	-from [get_cells -quiet -hier *eot_mem_reg* \
 		-filter {NAME =~ *i_request_arb* && PRIMITIVE_SUBGROUP == flop}] \
 	-to $async_src_to_req_clk [get_property PERIOD $src_clk] -datapath_only
 set_max_delay -quiet \
-	-from [get_cells -quiet -hier eot_mem_reg* \
+	-from [get_cells -quiet -hier *eot_mem_reg* \
 		-filter {NAME =~ *i_request_arb* && PRIMITIVE_SUBGROUP == flop}] \
 	-to $async_dest_to_req_clk [get_property PERIOD $dest_clk] -datapath_only
 
 #set_fifo_cdc_constraints i_fifo $src_clk $dest_clk
 set_max_delay -quiet \
 	-from $async_src_to_dest_clk \
-	-to [get_cells -quiet -hier cdc_sync_stage1_reg* \
+	-to [get_cells -quiet -hier *cdc_sync_stage1_reg* \
 		-filter {NAME =~ *i_fifo/i_address_gray/i_waddr_sync* && PRIMITIVE_SUBGROUP == flop}] \
 	[get_property PERIOD $src_clk] -datapath_only
 set_max_delay -quiet \
 	-from $async_dest_to_src_clk \
-	-to [get_cells -quiet -hier cdc_sync_stage1_reg* \
+	-to [get_cells -quiet -hier *cdc_sync_stage1_reg* \
 		-filter {NAME =~ *i_fifo/i_address_gray/i_raddr_sync* && PRIMITIVE_SUBGROUP == flop}] \
 	[get_property PERIOD $dest_clk] -datapath_only
 
@@ -177,21 +177,21 @@ set_false_path -quiet \
 # Not sure why, but it seems the built-in constraints for the RAM36B are wrong
 set_max_delay -quiet \
 	-from $async_dest_to_src_clk \
-	-to [get_pins -hier ram_reg*/REGCEB -filter {NAME =~ *i_fifo*}] \
+	-to [get_pins -hier *ram_reg*/REGCEB -filter {NAME =~ *i_fifo*}] \
 	[get_property PERIOD $dest_clk] -datapath_only
 
 # Ignore timing for debug signals to register map
 set_false_path -quiet \
-	-from [get_cells -quiet -hier cdc_sync_stage2_reg* \
+	-from [get_cells -quiet -hier *cdc_sync_stage2_reg* \
 		-filter {name =~ *i_sync_src_request_id* && primitive_subgroup == flop}] \
-	-to [get_cells -quiet -hier up_rdata_reg* -filter {primitive_subgroup == flop}]
+	-to [get_cells -quiet -hier *up_rdata_reg* -filter {primitive_subgroup == flop}]
 set_false_path -quiet \
-	-from [get_cells -quiet -hier cdc_sync_stage2_reg* \
+	-from [get_cells -quiet -hier *cdc_sync_stage2_reg* \
 		-filter {name =~ *i_sync_dest_request_id* && primitive_subgroup == flop}] \
-	-to [get_cells -quiet -hier up_rdata_reg* -filter {primitive_subgroup == flop}]
+	-to [get_cells -quiet -hier *up_rdata_reg* -filter {primitive_subgroup == flop}]
 set_false_path -quiet \
 	-from [get_cells -quiet -hier *id_reg* -filter {name =~ *i_request_arb* && primitive_subgroup == flop}] \
-	-to [get_cells -quiet -hier up_rdata_reg* -filter {primitive_subgroup == flop}]
+	-to [get_cells -quiet -hier *up_rdata_reg* -filter {primitive_subgroup == flop}]
 set_false_path -quiet \
-	-from [get_cells -quiet -hier address_reg* -filter {name =~ *i_addr_gen* && primitive_subgroup == flop}] \
-	-to [get_cells -quiet -hier up_rdata_reg* -filter {primitive_subgroup == flop}]
+	-from [get_cells -quiet -hier *address_reg* -filter {name =~ *i_addr_gen* && primitive_subgroup == flop}] \
+	-to [get_cells -quiet -hier *up_rdata_reg* -filter {primitive_subgroup == flop}]