fmcomms5: Update UP instantiations
Istvan Csomortani
parent
bb0cdf2f5e
commit
c9eaa43b1e
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@ -45,75 +45,75 @@ create_bd_port -dir O sys_100m_resetn
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# instances
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set axi_ad9361_0 [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9361:1.0 axi_ad9361_0]
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set_property -dict [list CONFIG.ID {0}] $axi_ad9361_0
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set_property -dict [list CONFIG.IO_DELAY_GROUP {dev_0_if_delay_group}] $axi_ad9361_0
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ad_ip_instance axi_ad9361 axi_ad9361_0
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ad_ip_parameter axi_ad9361_0 CONFIG.ID 0
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ad_ip_parameter axi_ad9361_0 CONFIG.IO_DELAY_GROUP dev_0_if_delay_group
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set axi_ad9361_1 [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9361:1.0 axi_ad9361_1]
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set_property -dict [list CONFIG.ID {1}] $axi_ad9361_1
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set_property -dict [list CONFIG.IO_DELAY_GROUP {dev_1_if_delay_group}] $axi_ad9361_1
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ad_ip_instance axi_ad9361 axi_ad9361_1
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ad_ip_parameter axi_ad9361_1 CONFIG.ID 1
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ad_ip_parameter axi_ad9361_1 CONFIG.IO_DELAY_GROUP dev_1_if_delay_group
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set axi_ad9361_dac_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad9361_dac_dma]
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set_property -dict [list CONFIG.DMA_TYPE_SRC {0}] $axi_ad9361_dac_dma
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set_property -dict [list CONFIG.DMA_TYPE_DEST {2}] $axi_ad9361_dac_dma
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set_property -dict [list CONFIG.CYCLIC {1}] $axi_ad9361_dac_dma
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set_property -dict [list CONFIG.SYNC_TRANSFER_START {0}] $axi_ad9361_dac_dma
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set_property -dict [list CONFIG.AXI_SLICE_SRC {0}] $axi_ad9361_dac_dma
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set_property -dict [list CONFIG.AXI_SLICE_DEST {1}] $axi_ad9361_dac_dma
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set_property -dict [list CONFIG.DMA_2D_TRANSFER {0}] $axi_ad9361_dac_dma
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set_property -dict [list CONFIG.DMA_DATA_WIDTH_DEST {128}] $axi_ad9361_dac_dma
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set_property -dict [list CONFIG.DMA_DATA_WIDTH_SRC {128}] $axi_ad9361_dac_dma
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ad_ip_instance axi_dmac axi_ad9361_dac_dma
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ad_ip_parameter axi_ad9361_dac_dma CONFIG.DMA_TYPE_SRC 0
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ad_ip_parameter axi_ad9361_dac_dma CONFIG.DMA_TYPE_DEST 2
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ad_ip_parameter axi_ad9361_dac_dma CONFIG.CYCLIC 1
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ad_ip_parameter axi_ad9361_dac_dma CONFIG.SYNC_TRANSFER_START 0
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ad_ip_parameter axi_ad9361_dac_dma CONFIG.AXI_SLICE_SRC 0
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ad_ip_parameter axi_ad9361_dac_dma CONFIG.AXI_SLICE_DEST 1
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ad_ip_parameter axi_ad9361_dac_dma CONFIG.DMA_2D_TRANSFER 0
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ad_ip_parameter axi_ad9361_dac_dma CONFIG.DMA_DATA_WIDTH_DEST 128
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ad_ip_parameter axi_ad9361_dac_dma CONFIG.DMA_DATA_WIDTH_SRC 128
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if {$sys_zynq == 1} {
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set_property -dict [list CONFIG.DMA_AXI_PROTOCOL_SRC {1}] $axi_ad9361_dac_dma
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set_property -dict [list CONFIG.DMA_DATA_WIDTH_SRC {64}] $axi_ad9361_dac_dma
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ad_ip_parameter axi_ad9361_dac_dma CONFIG.DMA_AXI_PROTOCOL_SRC 1
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ad_ip_parameter axi_ad9361_dac_dma CONFIG.DMA_DATA_WIDTH_SRC 64
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}
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set axi_ad9361_adc_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad9361_adc_dma]
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set_property -dict [list CONFIG.DMA_TYPE_SRC {2}] $axi_ad9361_adc_dma
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set_property -dict [list CONFIG.DMA_TYPE_DEST {0}] $axi_ad9361_adc_dma
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set_property -dict [list CONFIG.CYCLIC {0}] $axi_ad9361_adc_dma
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set_property -dict [list CONFIG.SYNC_TRANSFER_START {1}] $axi_ad9361_adc_dma
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set_property -dict [list CONFIG.AXI_SLICE_SRC {1}] $axi_ad9361_adc_dma
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set_property -dict [list CONFIG.AXI_SLICE_DEST {0}] $axi_ad9361_adc_dma
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set_property -dict [list CONFIG.DMA_2D_TRANSFER {0}] $axi_ad9361_adc_dma
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set_property -dict [list CONFIG.DMA_DATA_WIDTH_DEST {128}] $axi_ad9361_adc_dma
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set_property -dict [list CONFIG.DMA_DATA_WIDTH_SRC {128}] $axi_ad9361_adc_dma
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ad_ip_instance axi_dmac axi_ad9361_adc_dma
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ad_ip_parameter axi_ad9361_adc_dma CONFIG.DMA_TYPE_SRC 2
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ad_ip_parameter axi_ad9361_adc_dma CONFIG.DMA_TYPE_DEST 0
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ad_ip_parameter axi_ad9361_adc_dma CONFIG.CYCLIC 0
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ad_ip_parameter axi_ad9361_adc_dma CONFIG.SYNC_TRANSFER_START 1
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ad_ip_parameter axi_ad9361_adc_dma CONFIG.AXI_SLICE_SRC 1
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ad_ip_parameter axi_ad9361_adc_dma CONFIG.AXI_SLICE_DEST 0
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ad_ip_parameter axi_ad9361_adc_dma CONFIG.DMA_2D_TRANSFER 0
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ad_ip_parameter axi_ad9361_adc_dma CONFIG.DMA_DATA_WIDTH_DEST 128
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ad_ip_parameter axi_ad9361_adc_dma CONFIG.DMA_DATA_WIDTH_SRC 128
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if {$sys_zynq == 1} {
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set_property -dict [list CONFIG.DMA_AXI_PROTOCOL_DEST {1}] $axi_ad9361_adc_dma
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set_property -dict [list CONFIG.DMA_DATA_WIDTH_DEST {64}] $axi_ad9361_adc_dma
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ad_ip_parameter axi_ad9361_adc_dma CONFIG.DMA_AXI_PROTOCOL_DEST 1
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ad_ip_parameter axi_ad9361_adc_dma CONFIG.DMA_DATA_WIDTH_DEST 64
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}
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set util_upack_dac [create_bd_cell -type ip -vlnv analog.com:user:util_upack:1.0 util_upack_dac]
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set_property -dict [list CONFIG.CHANNEL_DATA_WIDTH {16}] $util_upack_dac
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set_property -dict [list CONFIG.NUM_OF_CHANNELS {8}] $util_upack_dac
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ad_ip_instance util_upack util_upack_dac
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ad_ip_parameter util_upack_dac CONFIG.CHANNEL_DATA_WIDTH 16
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ad_ip_parameter util_upack_dac CONFIG.NUM_OF_CHANNELS 8
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set util_cpack_adc [create_bd_cell -type ip -vlnv analog.com:user:util_cpack:1.0 util_cpack_adc]
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set_property -dict [list CONFIG.CHANNEL_DATA_WIDTH {16}] $util_cpack_adc
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set_property -dict [list CONFIG.NUM_OF_CHANNELS {8}] $util_cpack_adc
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ad_ip_instance util_cpack util_cpack_adc
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ad_ip_parameter util_cpack_adc CONFIG.CHANNEL_DATA_WIDTH 16
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ad_ip_parameter util_cpack_adc CONFIG.NUM_OF_CHANNELS 8
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set adc_wfifo [create_bd_cell -type ip -vlnv analog.com:user:util_wfifo:1.0 adc_wfifo]
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set_property -dict [list CONFIG.NUM_OF_CHANNELS {8} ] $adc_wfifo
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set_property -dict [list CONFIG.DIN_DATA_WIDTH {16} ] $adc_wfifo
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set_property -dict [list CONFIG.DOUT_DATA_WIDTH {16} ] $adc_wfifo
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set_property -dict [list CONFIG.DIN_ADDRESS_WIDTH {4}] $adc_wfifo
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ad_ip_instance util_wfifo adc_wfifo
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ad_ip_parameter adc_wfifo CONFIG.NUM_OF_CHANNELS 8
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ad_ip_parameter adc_wfifo CONFIG.DIN_DATA_WIDTH 16
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ad_ip_parameter adc_wfifo CONFIG.DOUT_DATA_WIDTH 16
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ad_ip_parameter adc_wfifo CONFIG.DIN_ADDRESS_WIDTH 4
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set clkdiv [ create_bd_cell -type ip -vlnv analog.com:user:util_clkdiv:1.0 clkdiv ]
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ad_ip_instance util_clkdiv clkdiv
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set clkdiv_reset [create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 clkdiv_reset]
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ad_ip_instance proc_sys_reset clkdiv_reset
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set dac_fifo [create_bd_cell -type ip -vlnv analog.com:user:util_rfifo:1.0 dac_fifo]
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set_property -dict [list CONFIG.DIN_DATA_WIDTH {16}] $dac_fifo
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set_property -dict [list CONFIG.DOUT_DATA_WIDTH {16}] $dac_fifo
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set_property -dict [list CONFIG.DIN_ADDRESS_WIDTH {4}] $dac_fifo
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set_property -dict [list CONFIG.NUM_OF_CHANNELS {8}] $dac_fifo
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ad_ip_instance util_rfifo dac_fifo
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ad_ip_parameter dac_fifo CONFIG.DIN_DATA_WIDTH 16
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ad_ip_parameter dac_fifo CONFIG.DOUT_DATA_WIDTH 16
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ad_ip_parameter dac_fifo CONFIG.DIN_ADDRESS_WIDTH 4
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ad_ip_parameter dac_fifo CONFIG.NUM_OF_CHANNELS 8
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set clkdiv_sel_logic [create_bd_cell -type ip -vlnv xilinx.com:ip:util_reduced_logic:2.0 clkdiv_sel_logic]
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set_property -dict [list CONFIG.C_SIZE {4}] $clkdiv_sel_logic
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ad_ip_instance util_reduced_logic clkdiv_sel_logic
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ad_ip_parameter clkdiv_sel_logic CONFIG.C_SIZE 4
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set concat_logic [create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 concat_logic]
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set_property -dict [list CONFIG.NUM_PORTS {4}] $concat_logic
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ad_ip_instance xlconcat concat_logic
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ad_ip_parameter concat_logic CONFIG.NUM_PORTS 4
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# connections (ad9361)
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@ -180,7 +180,7 @@ ad_connect concat_logic/In3 axi_ad9361_1/dac_r1_mode
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ad_connect concat_logic/dout clkdiv_sel_logic/Op1
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ad_connect clkdiv_sel_logic/Res clkdiv/clk_sel
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ad_connect axi_ad9361_adc_dma/fifo_wr_overflow adc_wfifo/dout_ovf
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ad_connect axi_ad9361_adc_dma/fifo_wr_overflow adc_wfifo/dout_ovf
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ad_connect adc_wfifo/din_ovf axi_ad9361_0/adc_dovf
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ad_connect axi_ad9361_0/adc_enable_i0 adc_wfifo/din_enable_0
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ad_connect axi_ad9361_0/adc_valid_i0 adc_wfifo/din_valid_0
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@ -1,11 +1,11 @@
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source $ad_hdl_dir/projects/common/zc702/zc702_system_bd.tcl
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set_property -dict [list CONFIG.PCW_EN_CLK2_PORT {1}] $sys_ps7
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set_property -dict [list CONFIG.PCW_FPGA2_PERIPHERAL_FREQMHZ {150.0}] $sys_ps7
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ad_ip_parameter sys_ps7 CONFIG.PCW_EN_CLK2_PORT 1
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ad_ip_parameter sys_ps7 CONFIG.PCW_FPGA2_PERIPHERAL_FREQMHZ 150.0
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ad_connect sys_dma_clk sys_ps7/FCLK_CLK2
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source ../common/fmcomms5_bd.tcl
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set_property CONFIG.ADC_INIT_DELAY 24 [get_bd_cells axi_ad9361_0]
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set_property CONFIG.ADC_INIT_DELAY 24 [get_bd_cells axi_ad9361_1]
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ad_ip_parameter axi_ad9361_0 CONFIG.ADC_INIT_DELAY 24
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ad_ip_parameter axi_ad9361_1 CONFIG.ADC_INIT_DELAY 24
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@ -1,11 +1,11 @@
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source $ad_hdl_dir/projects/common/zc706/zc706_system_bd.tcl
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set_property -dict [list CONFIG.PCW_EN_CLK2_PORT {1}] $sys_ps7
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set_property -dict [list CONFIG.PCW_FPGA2_PERIPHERAL_FREQMHZ {200.0}] $sys_ps7
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ad_ip_parameter sys_ps7 CONFIG.PCW_EN_CLK2_PORT 1
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ad_ip_parameter sys_ps7 CONFIG.PCW_FPGA2_PERIPHERAL_FREQMHZ 200.0
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ad_connect sys_dma_clk sys_ps7/FCLK_CLK2
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source ../common/fmcomms5_bd.tcl
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set_property CONFIG.ADC_INIT_DELAY 16 [get_bd_cells axi_ad9361_0]
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set_property CONFIG.ADC_INIT_DELAY 16 [get_bd_cells axi_ad9361_1]
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ad_ip_parameter axi_ad9361_0 CONFIG.ADC_INIT_DELAY 16
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ad_ip_parameter axi_ad9361_1 CONFIG.ADC_INIT_DELAY 16
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@ -1,16 +1,16 @@
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source $ad_hdl_dir/projects/common/zcu102/zcu102_system_bd.tcl
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set_property CONFIG.PSU__FPGA_PL2_ENABLE {1} $sys_ps8
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set_property CONFIG.PSU__CRL_APB__PL2_REF_CTRL__FREQMHZ {200} $sys_ps8
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set_property CONFIG.PSU__CRL_APB__PL2_REF_CTRL__DIVISOR0 {3} $sys_ps8
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set_property CONFIG.PSU__CRL_APB__PL2_REF_CTRL__DIVISOR1 {2} $sys_ps8
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ad_ip_parameter sys_ps8 CONFIG.PSU__FPGA_PL2_ENABLE 1
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ad_ip_parameter sys_ps8 CONFIG.PSU__CRL_APB__PL2_REF_CTRL__FREQMHZ 200
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ad_ip_parameter sys_ps8 CONFIG.PSU__CRL_APB__PL2_REF_CTRL__DIVISOR0 3
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ad_ip_parameter sys_ps8 CONFIG.PSU__CRL_APB__PL2_REF_CTRL__DIVISOR1 2
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ad_connect sys_dma_clk sys_ps8/pl_clk2
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source ../common/fmcomms5_bd.tcl
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set_property CONFIG.DEVICE_TYPE 2 [get_bd_cells axi_ad9361_0]
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set_property CONFIG.ADC_INIT_DELAY 8 [get_bd_cells axi_ad9361_0]
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set_property CONFIG.DEVICE_TYPE 2 [get_bd_cells axi_ad9361_1]
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set_property CONFIG.ADC_INIT_DELAY 8 [get_bd_cells axi_ad9361_1]
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ad_ip_parameter axi_ad9361_0 CONFIG.DEVICE_TYPE 2
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ad_ip_parameter axi_ad9361_0 CONFIG.ADC_INIT_DELAY 8
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ad_ip_parameter axi_ad9361_1 CONFIG.DEVICE_TYPE 2
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ad_ip_parameter axi_ad9361_1 CONFIG.ADC_INIT_DELAY 8
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set_property -dict [list CONFIG.SIM_DEVICE {ULTRASCALE}] $clkdiv
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ad_ip_parameter clkdiv CONFIG.SIM_DEVICE ULTRASCALE
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