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adrv9009: use generic TPL 

Make the block design parametrizable.
Limitations:
  F = 1,2,4
main
Laszlo Nagy 2018-10-11 09:21:10 +01:00 committed by Laszlo Nagy
parent a65bafb056
commit c9f1c92eaa
4 changed files with 134 additions and 91 deletions
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219
projects/adrv9009/common/adrv9009_bd.tcl
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@ -1,4 +1,28 @@
# TX parameters
set TX_NUM_OF_LANES 4 ; # L
set TX_NUM_OF_CONVERTERS 4 ; # M
set TX_SAMPLES_PER_FRAME 1 ; # S
set TX_SAMPLE_WIDTH 16 ; # N/NP
set TX_SAMPLES_PER_CHANNEL 2 ; # L * 32 / (M * N)
# RX parameters
set RX_NUM_OF_LANES 2 ; # L
set RX_NUM_OF_CONVERTERS 4 ; # M
set RX_SAMPLES_PER_FRAME 1 ; # S
set RX_SAMPLE_WIDTH 16 ; # N/NP
set RX_SAMPLES_PER_CHANNEL 1 ; # L * 32 / (M * N)
# RX Observation parameters
set RX_OS_NUM_OF_LANES 2 ; # L
set RX_OS_NUM_OF_CONVERTERS 4 ; # M
set RX_OS_SAMPLES_PER_FRAME 1 ; # S
set RX_OS_SAMPLE_WIDTH 16 ; # N/NP
set RX_OS_SAMPLES_PER_CHANNEL 1 ; # L * 32 / (M * N)
source $ad_hdl_dir/library/jesd204/scripts/jesd204.tcl
# adrv9009
@ -15,19 +39,24 @@ ad_ip_parameter axi_adrv9009_tx_clkgen CONFIG.VCO_MUL 4
ad_ip_parameter axi_adrv9009_tx_clkgen CONFIG.CLK0_DIV 4
ad_ip_instance axi_adxcvr axi_adrv9009_tx_xcvr
ad_ip_parameter axi_adrv9009_tx_xcvr CONFIG.NUM_OF_LANES 4
ad_ip_parameter axi_adrv9009_tx_xcvr CONFIG.NUM_OF_LANES $TX_NUM_OF_LANES
ad_ip_parameter axi_adrv9009_tx_xcvr CONFIG.QPLL_ENABLE 1
ad_ip_parameter axi_adrv9009_tx_xcvr CONFIG.TX_OR_RX_N 1
ad_ip_parameter axi_adrv9009_tx_xcvr CONFIG.SYS_CLK_SEL 3
ad_ip_parameter axi_adrv9009_tx_xcvr CONFIG.OUT_CLK_SEL 3
adi_axi_jesd204_tx_create axi_adrv9009_tx_jesd 4
adi_axi_jesd204_tx_create axi_adrv9009_tx_jesd $TX_NUM_OF_LANES
ad_ip_instance util_upack2 util_adrv9009_tx_upack { \
NUM_OF_CHANNELS 4 \
SAMPLES_PER_CHANNEL 2 \
SAMPLE_DATA_WIDTH 16 \
}
ad_ip_instance util_upack2 util_adrv9009_tx_upack [list \
NUM_OF_CHANNELS $TX_NUM_OF_CONVERTERS \
SAMPLES_PER_CHANNEL $TX_SAMPLES_PER_CHANNEL \
SAMPLE_DATA_WIDTH $TX_SAMPLE_WIDTH \
]
adi_tpl_jesd204_tx_create tx_adrv9009_tpl_core $TX_NUM_OF_LANES \
$TX_NUM_OF_CONVERTERS \
$TX_SAMPLES_PER_FRAME \
$TX_SAMPLE_WIDTH
ad_ip_instance axi_dmac axi_adrv9009_tx_dma
ad_ip_parameter axi_adrv9009_tx_dma CONFIG.DMA_TYPE_SRC 0
@ -37,7 +66,7 @@ ad_ip_parameter axi_adrv9009_tx_dma CONFIG.ASYNC_CLK_DEST_REQ 1
ad_ip_parameter axi_adrv9009_tx_dma CONFIG.ASYNC_CLK_SRC_DEST 1
ad_ip_parameter axi_adrv9009_tx_dma CONFIG.ASYNC_CLK_REQ_SRC 1
ad_ip_parameter axi_adrv9009_tx_dma CONFIG.DMA_2D_TRANSFER 0
ad_ip_parameter axi_adrv9009_tx_dma CONFIG.DMA_DATA_WIDTH_DEST 128
ad_ip_parameter axi_adrv9009_tx_dma CONFIG.DMA_DATA_WIDTH_DEST $dac_dma_data_width
ad_ip_parameter axi_adrv9009_tx_dma CONFIG.MAX_BYTES_PER_BURST 256
ad_ip_parameter axi_adrv9009_tx_dma CONFIG.AXI_SLICE_DEST true
ad_ip_parameter axi_adrv9009_tx_dma CONFIG.AXI_SLICE_SRC true
@ -52,19 +81,24 @@ ad_ip_parameter axi_adrv9009_rx_clkgen CONFIG.VCO_MUL 4
ad_ip_parameter axi_adrv9009_rx_clkgen CONFIG.CLK0_DIV 4
ad_ip_instance axi_adxcvr axi_adrv9009_rx_xcvr
ad_ip_parameter axi_adrv9009_rx_xcvr CONFIG.NUM_OF_LANES 2
ad_ip_parameter axi_adrv9009_rx_xcvr CONFIG.NUM_OF_LANES $RX_NUM_OF_LANES
ad_ip_parameter axi_adrv9009_rx_xcvr CONFIG.QPLL_ENABLE 0
ad_ip_parameter axi_adrv9009_rx_xcvr CONFIG.TX_OR_RX_N 0
ad_ip_parameter axi_adrv9009_rx_xcvr CONFIG.SYS_CLK_SEL 0
ad_ip_parameter axi_adrv9009_rx_xcvr CONFIG.OUT_CLK_SEL 3
adi_axi_jesd204_rx_create axi_adrv9009_rx_jesd 2
adi_axi_jesd204_rx_create axi_adrv9009_rx_jesd $RX_NUM_OF_LANES
ad_ip_instance util_cpack2 util_adrv9009_rx_cpack { \
NUM_OF_CHANNELS 4 \
SAMPLES_PER_CHANNEL 1 \
SAMPLE_DATA_WIDTH 16 \
}
ad_ip_instance util_cpack2 util_adrv9009_rx_cpack [list \
NUM_OF_CHANNELS $RX_NUM_OF_CONVERTERS \
SAMPLES_PER_CHANNEL $RX_SAMPLES_PER_CHANNEL \
SAMPLE_DATA_WIDTH $RX_SAMPLE_WIDTH \
]
adi_tpl_jesd204_rx_create rx_adrv9009_tpl_core $RX_NUM_OF_LANES \
$RX_NUM_OF_CONVERTERS \
$RX_SAMPLES_PER_FRAME \
$RX_SAMPLE_WIDTH
ad_ip_instance axi_dmac axi_adrv9009_rx_dma
ad_ip_parameter axi_adrv9009_rx_dma CONFIG.DMA_TYPE_SRC 2
@ -75,7 +109,7 @@ ad_ip_parameter axi_adrv9009_rx_dma CONFIG.ASYNC_CLK_DEST_REQ 1
ad_ip_parameter axi_adrv9009_rx_dma CONFIG.ASYNC_CLK_SRC_DEST 1
ad_ip_parameter axi_adrv9009_rx_dma CONFIG.ASYNC_CLK_REQ_SRC 1
ad_ip_parameter axi_adrv9009_rx_dma CONFIG.DMA_2D_TRANSFER 0
ad_ip_parameter axi_adrv9009_rx_dma CONFIG.DMA_DATA_WIDTH_SRC 64
ad_ip_parameter axi_adrv9009_rx_dma CONFIG.DMA_DATA_WIDTH_SRC [expr 32*$RX_NUM_OF_LANES]
ad_ip_parameter axi_adrv9009_rx_dma CONFIG.MAX_BYTES_PER_BURST 256
ad_ip_parameter axi_adrv9009_rx_dma CONFIG.AXI_SLICE_DEST true
ad_ip_parameter axi_adrv9009_rx_dma CONFIG.AXI_SLICE_SRC true
@ -90,19 +124,24 @@ ad_ip_parameter axi_adrv9009_rx_os_clkgen CONFIG.VCO_MUL 4
ad_ip_parameter axi_adrv9009_rx_os_clkgen CONFIG.CLK0_DIV 4
ad_ip_instance axi_adxcvr axi_adrv9009_rx_os_xcvr
ad_ip_parameter axi_adrv9009_rx_os_xcvr CONFIG.NUM_OF_LANES 2
ad_ip_parameter axi_adrv9009_rx_os_xcvr CONFIG.NUM_OF_LANES $RX_OS_NUM_OF_LANES
ad_ip_parameter axi_adrv9009_rx_os_xcvr CONFIG.QPLL_ENABLE 0
ad_ip_parameter axi_adrv9009_rx_os_xcvr CONFIG.TX_OR_RX_N 0
ad_ip_parameter axi_adrv9009_rx_os_xcvr CONFIG.SYS_CLK_SEL 0
ad_ip_parameter axi_adrv9009_rx_os_xcvr CONFIG.OUT_CLK_SEL 3
adi_axi_jesd204_rx_create axi_adrv9009_rx_os_jesd 2
adi_axi_jesd204_rx_create axi_adrv9009_rx_os_jesd $RX_OS_NUM_OF_LANES
ad_ip_instance util_cpack2 util_adrv9009_rx_os_cpack { \
NUM_OF_CHANNELS 4 \
SAMPLES_PER_CHANNEL 2 \
SAMPLE_DATA_WIDTH 16 \
}
ad_ip_instance util_cpack2 util_adrv9009_rx_os_cpack [list \
NUM_OF_CHANNELS $RX_OS_NUM_OF_CONVERTERS \
SAMPLES_PER_CHANNEL $RX_OS_SAMPLES_PER_CHANNEL\
SAMPLE_DATA_WIDTH $RX_OS_SAMPLE_WIDTH \
]
adi_tpl_jesd204_rx_create rx_os_adrv9009_tpl_core $RX_OS_NUM_OF_LANES \
$RX_OS_NUM_OF_CONVERTERS \
$RX_OS_SAMPLES_PER_FRAME \
$RX_OS_SAMPLE_WIDTH
ad_ip_instance axi_dmac axi_adrv9009_rx_os_dma
ad_ip_parameter axi_adrv9009_rx_os_dma CONFIG.DMA_TYPE_SRC 2
@ -113,18 +152,17 @@ ad_ip_parameter axi_adrv9009_rx_os_dma CONFIG.ASYNC_CLK_DEST_REQ 1
ad_ip_parameter axi_adrv9009_rx_os_dma CONFIG.ASYNC_CLK_SRC_DEST 1
ad_ip_parameter axi_adrv9009_rx_os_dma CONFIG.ASYNC_CLK_REQ_SRC 1
ad_ip_parameter axi_adrv9009_rx_os_dma CONFIG.DMA_2D_TRANSFER 0
ad_ip_parameter axi_adrv9009_rx_os_dma CONFIG.DMA_DATA_WIDTH_SRC 128
ad_ip_parameter axi_adrv9009_rx_os_dma CONFIG.DMA_DATA_WIDTH_SRC [expr 32*$RX_NUM_OF_LANES];
ad_ip_parameter axi_adrv9009_rx_os_dma CONFIG.MAX_BYTES_PER_BURST 256
ad_ip_parameter axi_adrv9009_rx_os_dma CONFIG.AXI_SLICE_DEST true
ad_ip_parameter axi_adrv9009_rx_os_dma CONFIG.AXI_SLICE_SRC true
# common cores
ad_ip_instance axi_adrv9009 axi_adrv9009_core
ad_ip_instance util_adxcvr util_adrv9009_xcvr
ad_ip_parameter util_adrv9009_xcvr CONFIG.RX_NUM_OF_LANES 4
ad_ip_parameter util_adrv9009_xcvr CONFIG.TX_NUM_OF_LANES 4
ad_ip_parameter util_adrv9009_xcvr CONFIG.RX_NUM_OF_LANES [expr $RX_NUM_OF_LANES+$RX_OS_NUM_OF_LANES]
ad_ip_parameter util_adrv9009_xcvr CONFIG.TX_NUM_OF_LANES $TX_NUM_OF_LANES
ad_ip_parameter util_adrv9009_xcvr CONFIG.TX_OUT_DIV 1
ad_ip_parameter util_adrv9009_xcvr CONFIG.CPLL_FBDIV 4
ad_ip_parameter util_adrv9009_xcvr CONFIG.CPLL_FBDIV_4_5 5
@ -136,41 +174,52 @@ ad_ip_parameter util_adrv9009_xcvr CONFIG.QPLL_FBDIV 0x080
# xcvr interfaces
create_bd_port -dir I tx_ref_clk_0
create_bd_port -dir I rx_ref_clk_0
create_bd_port -dir I rx_ref_clk_2
set tx_offset 0
set rx_offset 0
set rx_obs_offset $RX_NUM_OF_LANES
ad_xcvrpll tx_ref_clk_0 util_adrv9009_xcvr/qpll_ref_clk_0
ad_xcvrpll rx_ref_clk_0 util_adrv9009_xcvr/cpll_ref_clk_0
ad_xcvrpll rx_ref_clk_0 util_adrv9009_xcvr/cpll_ref_clk_1
ad_xcvrpll rx_ref_clk_2 util_adrv9009_xcvr/cpll_ref_clk_2
ad_xcvrpll rx_ref_clk_2 util_adrv9009_xcvr/cpll_ref_clk_3
ad_xcvrpll axi_adrv9009_tx_xcvr/up_pll_rst util_adrv9009_xcvr/up_qpll_rst_0
ad_xcvrpll axi_adrv9009_rx_xcvr/up_pll_rst util_adrv9009_xcvr/up_cpll_rst_0
ad_xcvrpll axi_adrv9009_rx_xcvr/up_pll_rst util_adrv9009_xcvr/up_cpll_rst_1
ad_xcvrpll axi_adrv9009_rx_os_xcvr/up_pll_rst util_adrv9009_xcvr/up_cpll_rst_2
ad_xcvrpll axi_adrv9009_rx_os_xcvr/up_pll_rst util_adrv9009_xcvr/up_cpll_rst_3
set tx_ref_clk tx_ref_clk_$tx_offset
set rx_ref_clk rx_ref_clk_$rx_offset
set rx_obs_ref_clk rx_ref_clk_$rx_obs_offset
create_bd_port -dir I $tx_ref_clk
create_bd_port -dir I $rx_ref_clk
create_bd_port -dir I $rx_obs_ref_clk
ad_connect sys_cpu_resetn util_adrv9009_xcvr/up_rstn
ad_connect sys_cpu_clk util_adrv9009_xcvr/up_clk
# Tx
ad_xcvrcon util_adrv9009_xcvr axi_adrv9009_tx_xcvr axi_adrv9009_tx_jesd {0 3 2 1}
ad_reconct util_adrv9009_xcvr/tx_out_clk_0 axi_adrv9009_tx_clkgen/clk
ad_connect axi_adrv9009_tx_clkgen/clk_0 util_adrv9009_xcvr/tx_clk_0
ad_connect axi_adrv9009_tx_clkgen/clk_0 util_adrv9009_xcvr/tx_clk_1
ad_connect axi_adrv9009_tx_clkgen/clk_0 util_adrv9009_xcvr/tx_clk_2
ad_connect axi_adrv9009_tx_clkgen/clk_0 util_adrv9009_xcvr/tx_clk_3
for {set i 0} {$i < $TX_NUM_OF_LANES} {incr i} {
ad_connect axi_adrv9009_tx_clkgen/clk_0 util_adrv9009_xcvr/tx_clk_$i
}
ad_xcvrpll $tx_ref_clk util_adrv9009_xcvr/qpll_ref_clk_0
ad_xcvrpll axi_adrv9009_tx_xcvr/up_pll_rst util_adrv9009_xcvr/up_qpll_rst_0
ad_connect axi_adrv9009_tx_clkgen/clk_0 axi_adrv9009_tx_jesd/device_clk
ad_connect axi_adrv9009_tx_clkgen/clk_0 axi_adrv9009_tx_jesd_rstgen/slowest_sync_clk
# Rx
ad_xcvrcon util_adrv9009_xcvr axi_adrv9009_rx_xcvr axi_adrv9009_rx_jesd
ad_reconct util_adrv9009_xcvr/rx_out_clk_0 axi_adrv9009_rx_clkgen/clk
ad_connect axi_adrv9009_rx_clkgen/clk_0 util_adrv9009_xcvr/rx_clk_0
ad_connect axi_adrv9009_rx_clkgen/clk_0 util_adrv9009_xcvr/rx_clk_1
ad_reconct util_adrv9009_xcvr/rx_out_clk_$rx_offset axi_adrv9009_rx_clkgen/clk
for {set i 0} {$i < $RX_NUM_OF_LANES} {incr i} {
set ch [expr $rx_offset+$i]
ad_connect axi_adrv9009_rx_clkgen/clk_0 util_adrv9009_xcvr/rx_clk_$ch
ad_xcvrpll $rx_ref_clk util_adrv9009_xcvr/cpll_ref_clk_$ch
ad_xcvrpll axi_adrv9009_rx_xcvr/up_pll_rst util_adrv9009_xcvr/up_cpll_rst_$ch
}
ad_connect axi_adrv9009_rx_clkgen/clk_0 axi_adrv9009_rx_jesd/device_clk
ad_connect axi_adrv9009_rx_clkgen/clk_0 axi_adrv9009_rx_jesd_rstgen/slowest_sync_clk
# Rx - OBS
ad_xcvrcon util_adrv9009_xcvr axi_adrv9009_rx_os_xcvr axi_adrv9009_rx_os_jesd
ad_reconct util_adrv9009_xcvr/rx_out_clk_2 axi_adrv9009_rx_os_clkgen/clk
ad_connect axi_adrv9009_rx_os_clkgen/clk_0 util_adrv9009_xcvr/rx_clk_2
ad_connect axi_adrv9009_rx_os_clkgen/clk_0 util_adrv9009_xcvr/rx_clk_3
ad_reconct util_adrv9009_xcvr/rx_out_clk_$rx_obs_offset axi_adrv9009_rx_os_clkgen/clk
for {set i 0} {$i < $RX_OS_NUM_OF_LANES} {incr i} {
set ch [expr $rx_obs_offset+$i]
ad_connect axi_adrv9009_rx_os_clkgen/clk_0 util_adrv9009_xcvr/rx_clk_$ch
ad_xcvrpll $rx_obs_ref_clk util_adrv9009_xcvr/cpll_ref_clk_$ch
ad_xcvrpll axi_adrv9009_rx_os_xcvr/up_pll_rst util_adrv9009_xcvr/up_cpll_rst_$ch
}
ad_connect axi_adrv9009_rx_os_clkgen/clk_0 axi_adrv9009_rx_os_jesd/device_clk
ad_connect axi_adrv9009_rx_os_clkgen/clk_0 axi_adrv9009_rx_os_jesd_rstgen/slowest_sync_clk
@ -186,21 +235,17 @@ ad_connect sys_dma_reset axi_adrv9009_dacfifo/dma_rst
# connections (dac)
ad_connect axi_adrv9009_tx_clkgen/clk_0 axi_adrv9009_core/dac_clk
ad_connect axi_adrv9009_tx_jesd/tx_data_tdata axi_adrv9009_core/dac_tx_data
ad_connect axi_adrv9009_tx_clkgen/clk_0 tx_adrv9009_tpl_core/link_clk
ad_connect axi_adrv9009_tx_jesd/tx_data tx_adrv9009_tpl_core/link
ad_connect axi_adrv9009_tx_clkgen/clk_0 util_adrv9009_tx_upack/clk
ad_connect axi_adrv9009_tx_jesd_rstgen/peripheral_reset util_adrv9009_tx_upack/reset
ad_connect axi_adrv9009_core/dac_valid_i0 util_adrv9009_tx_upack/fifo_rd_en
ad_connect axi_adrv9009_core/dac_enable_i0 util_adrv9009_tx_upack/enable_0
ad_connect axi_adrv9009_core/dac_data_i0 util_adrv9009_tx_upack/fifo_rd_data_0
ad_connect axi_adrv9009_core/dac_enable_q0 util_adrv9009_tx_upack/enable_1
ad_connect axi_adrv9009_core/dac_data_q0 util_adrv9009_tx_upack/fifo_rd_data_1
ad_connect axi_adrv9009_core/dac_enable_i1 util_adrv9009_tx_upack/enable_2
ad_connect axi_adrv9009_core/dac_data_i1 util_adrv9009_tx_upack/fifo_rd_data_2
ad_connect axi_adrv9009_core/dac_enable_q1 util_adrv9009_tx_upack/enable_3
ad_connect axi_adrv9009_core/dac_data_q1 util_adrv9009_tx_upack/fifo_rd_data_3
ad_connect tx_adrv9009_tpl_core/dac_valid_0 util_adrv9009_tx_upack/fifo_rd_en
for {set i 0} {$i < $TX_NUM_OF_CONVERTERS} {incr i} {
ad_connect util_adrv9009_tx_upack/fifo_rd_data_$i tx_adrv9009_tpl_core/dac_data_$i
ad_connect tx_adrv9009_tpl_core/dac_enable_$i util_adrv9009_tx_upack/enable_$i
}
ad_connect axi_adrv9009_tx_clkgen/clk_0 axi_adrv9009_dacfifo/dac_clk
ad_connect axi_adrv9009_tx_jesd_rstgen/peripheral_reset axi_adrv9009_dacfifo/dac_rst
@ -217,27 +262,25 @@ ad_connect axi_adrv9009_dacfifo/dma_data axi_adrv9009_tx_dma/m_axis_data
ad_connect axi_adrv9009_dacfifo/dma_ready axi_adrv9009_tx_dma/m_axis_ready
ad_connect axi_adrv9009_dacfifo/dma_xfer_req axi_adrv9009_tx_dma/m_axis_xfer_req
ad_connect axi_adrv9009_dacfifo/dma_xfer_last axi_adrv9009_tx_dma/m_axis_last
ad_connect axi_adrv9009_dacfifo/dac_dunf axi_adrv9009_core/dac_dunf
ad_connect axi_adrv9009_dacfifo/dac_dunf tx_adrv9009_tpl_core/dac_dunf
ad_connect axi_adrv9009_dacfifo/bypass dac_fifo_bypass
ad_connect sys_dma_resetn axi_adrv9009_tx_dma/m_src_axi_aresetn
# connections (adc)
ad_connect axi_adrv9009_rx_clkgen/clk_0 axi_adrv9009_core/adc_clk
ad_connect axi_adrv9009_rx_jesd/rx_sof axi_adrv9009_core/adc_rx_sof
ad_connect axi_adrv9009_rx_jesd/rx_data_tdata axi_adrv9009_core/adc_rx_data
ad_connect axi_adrv9009_rx_clkgen/clk_0 rx_adrv9009_tpl_core/link_clk
ad_connect axi_adrv9009_rx_jesd/rx_sof rx_adrv9009_tpl_core/link_sof
ad_connect axi_adrv9009_rx_jesd/rx_data_tdata rx_adrv9009_tpl_core/link_data
ad_connect axi_adrv9009_rx_jesd/rx_data_tvalid rx_adrv9009_tpl_core/link_valid
ad_connect axi_adrv9009_rx_clkgen/clk_0 util_adrv9009_rx_cpack/clk
ad_connect axi_adrv9009_rx_jesd_rstgen/peripheral_reset util_adrv9009_rx_cpack/reset
ad_connect axi_adrv9009_core/adc_valid_i0 util_adrv9009_rx_cpack/fifo_wr_en
ad_connect axi_adrv9009_core/adc_enable_i0 util_adrv9009_rx_cpack/enable_0
ad_connect axi_adrv9009_core/adc_data_i0 util_adrv9009_rx_cpack/fifo_wr_data_0
ad_connect axi_adrv9009_core/adc_enable_q0 util_adrv9009_rx_cpack/enable_1
ad_connect axi_adrv9009_core/adc_data_q0 util_adrv9009_rx_cpack/fifo_wr_data_1
ad_connect axi_adrv9009_core/adc_enable_i1 util_adrv9009_rx_cpack/enable_2
ad_connect axi_adrv9009_core/adc_data_i1 util_adrv9009_rx_cpack/fifo_wr_data_2
ad_connect axi_adrv9009_core/adc_enable_q1 util_adrv9009_rx_cpack/enable_3
ad_connect axi_adrv9009_core/adc_data_q1 util_adrv9009_rx_cpack/fifo_wr_data_3
ad_connect rx_adrv9009_tpl_core/adc_valid_0 util_adrv9009_rx_cpack/fifo_wr_en
for {set i 0} {$i < $RX_NUM_OF_CONVERTERS} {incr i} {
ad_connect rx_adrv9009_tpl_core/adc_enable_$i util_adrv9009_rx_cpack/enable_$i
ad_connect rx_adrv9009_tpl_core/adc_data_$i util_adrv9009_rx_cpack/fifo_wr_data_$i
}
ad_connect rx_adrv9009_tpl_core/adc_dovf util_adrv9009_rx_cpack/fifo_wr_overflow
ad_connect axi_adrv9009_rx_clkgen/clk_0 axi_adrv9009_rx_dma/fifo_wr_clk
ad_connect util_adrv9009_rx_cpack/packed_fifo_wr axi_adrv9009_rx_dma/fifo_wr
@ -245,31 +288,29 @@ ad_connect sys_dma_resetn axi_adrv9009_rx_dma/m_dest_axi_aresetn
# connections (adc-os)
ad_connect axi_adrv9009_rx_os_clkgen/clk_0 axi_adrv9009_core/adc_os_clk
ad_connect axi_adrv9009_rx_os_jesd/rx_sof axi_adrv9009_core/adc_rx_os_sof
ad_connect axi_adrv9009_rx_os_jesd/rx_data_tdata axi_adrv9009_core/adc_rx_os_data
ad_connect axi_adrv9009_rx_os_clkgen/clk_0 rx_os_adrv9009_tpl_core/link_clk
ad_connect axi_adrv9009_rx_os_jesd/rx_sof rx_os_adrv9009_tpl_core/link_sof
ad_connect axi_adrv9009_rx_os_jesd/rx_data_tdata rx_os_adrv9009_tpl_core/link_data
ad_connect axi_adrv9009_rx_os_jesd/rx_data_tvalid rx_os_adrv9009_tpl_core/link_valid
ad_connect axi_adrv9009_rx_os_clkgen/clk_0 util_adrv9009_rx_os_cpack/clk
ad_connect axi_adrv9009_rx_os_jesd_rstgen/peripheral_reset util_adrv9009_rx_os_cpack/reset
ad_connect axi_adrv9009_rx_os_clkgen/clk_0 axi_adrv9009_rx_os_dma/fifo_wr_clk
ad_connect axi_adrv9009_core/adc_os_valid_i0 util_adrv9009_rx_os_cpack/fifo_wr_en
ad_connect axi_adrv9009_core/adc_os_enable_i0 util_adrv9009_rx_os_cpack/enable_0
ad_connect axi_adrv9009_core/adc_os_data_i0 util_adrv9009_rx_os_cpack/fifo_wr_data_0
ad_connect axi_adrv9009_core/adc_os_enable_q0 util_adrv9009_rx_os_cpack/enable_1
ad_connect axi_adrv9009_core/adc_os_data_q0 util_adrv9009_rx_os_cpack/fifo_wr_data_1
ad_connect axi_adrv9009_core/adc_os_enable_i1 util_adrv9009_rx_os_cpack/enable_2
ad_connect axi_adrv9009_core/adc_os_data_i1 util_adrv9009_rx_os_cpack/fifo_wr_data_2
ad_connect axi_adrv9009_core/adc_os_enable_q1 util_adrv9009_rx_os_cpack/enable_3
ad_connect axi_adrv9009_core/adc_os_data_q1 util_adrv9009_rx_os_cpack/fifo_wr_data_3
ad_connect axi_adrv9009_core/adc_os_dovf util_adrv9009_rx_os_cpack/fifo_wr_overflow
ad_connect rx_os_adrv9009_tpl_core/adc_valid_0 util_adrv9009_rx_os_cpack/fifo_wr_en
for {set i 0} {$i < $RX_OS_NUM_OF_CONVERTERS} {incr i} {
ad_connect rx_os_adrv9009_tpl_core/adc_enable_$i util_adrv9009_rx_os_cpack/enable_$i
ad_connect rx_os_adrv9009_tpl_core/adc_data_$i util_adrv9009_rx_os_cpack/fifo_wr_data_$i
}
ad_connect rx_os_adrv9009_tpl_core/adc_dovf util_adrv9009_rx_os_cpack/fifo_wr_overflow
ad_connect util_adrv9009_rx_os_cpack/packed_fifo_wr axi_adrv9009_rx_os_dma/fifo_wr
ad_connect sys_dma_resetn axi_adrv9009_rx_os_dma/m_dest_axi_aresetn
# interconnect (cpu)
ad_cpu_interconnect 0x44A00000 axi_adrv9009_core
ad_cpu_interconnect 0x44A00000 rx_adrv9009_tpl_core
ad_cpu_interconnect 0x44A04000 tx_adrv9009_tpl_core
ad_cpu_interconnect 0x44A08000 rx_os_adrv9009_tpl_core
ad_cpu_interconnect 0x44A80000 axi_adrv9009_tx_xcvr
ad_cpu_interconnect 0x43C00000 axi_adrv9009_tx_clkgen
ad_cpu_interconnect 0x44A90000 axi_adrv9009_tx_jesd

2
projects/adrv9009/zc706/Makefile
View File

@ -22,6 +22,8 @@ LIB_DEPS += jesd204/axi_jesd204_rx
LIB_DEPS += jesd204/axi_jesd204_tx
LIB_DEPS += jesd204/jesd204_rx
LIB_DEPS += jesd204/jesd204_tx
LIB_DEPS += jesd204/ad_ip_jesd204_tpl_dac
LIB_DEPS += jesd204/ad_ip_jesd204_tpl_adc
LIB_DEPS += util_cpack
LIB_DEPS += util_upack
LIB_DEPS += xilinx/axi_adxcvr

2
projects/adrv9009/zc706/system_bd.tcl
View File

@ -1,7 +1,7 @@
set dac_fifo_name axi_adrv9009_dacfifo
set dac_fifo_address_width 10
set dac_data_width 128
set dac_data_width 128 ; # should be 32*L (number of TX lanes)
set dac_dma_data_width 128
source $ad_hdl_dir/projects/common/zc706/zc706_system_bd.tcl

2
projects/adrv9009/zcu102/system_bd.tcl
View File

@ -2,7 +2,7 @@
## FIFO depth is 18Mb - 1M samples
set dac_fifo_name axi_adrv9009_dacfifo
set dac_fifo_address_width 17
set dac_data_width 128
set dac_data_width 128 ; # should be 32*L (number of TX lanes)
set dac_dma_data_width 128
## NOTE: With this configuration the #36Kb BRAM utilization is at ~57%