adi_project_alt: add c5soc
parent
034aa7c1ee
commit
ca20309166
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@ -19,11 +19,19 @@ proc adi_project_altera {project_name} {
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if [regexp "_a10gx$" $project_name] {
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if [regexp "_a10gx$" $project_name] {
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set family "Arria 10"
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set family "Arria 10"
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set device 10AX115S2F45I1SG
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set device 10AX115S2F45I1SG
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set system_qip_file system_bd/system_bd.qip
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}
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}
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if [regexp "_a10soc$" $project_name] {
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if [regexp "_a10soc$" $project_name] {
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set family "Arria 10"
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set family "Arria 10"
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set device 10AS066N3F40E2SG
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set device 10AS066N3F40E2SG
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set system_qip_file system_bd/system_bd.qip
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}
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if [regexp "_c5soc$" $project_name] {
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set family "Cyclone V"
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set device 5CSXFC6D6F31C8ES
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set system_qip_file system_bd/synthesis/system_bd.qip
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}
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}
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# version check
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# version check
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@ -90,7 +98,7 @@ proc adi_project_altera {project_name} {
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# default assignments
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# default assignments
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set_global_assignment -name QIP_FILE system_bd/system_bd.qip
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set_global_assignment -name QIP_FILE $system_qip_file
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set_global_assignment -name VERILOG_FILE system_top.v
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set_global_assignment -name VERILOG_FILE system_top.v
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set_global_assignment -name SDC_FILE system_constr.sdc
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set_global_assignment -name SDC_FILE system_constr.sdc
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set_global_assignment -name TOP_LEVEL_ENTITY system_top
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set_global_assignment -name TOP_LEVEL_ENTITY system_top
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