From ce47cf8d3030f371bb295c5b297ff14cfed833f5 Mon Sep 17 00:00:00 2001 From: Istvan Csomortani Date: Mon, 19 Dec 2016 18:02:49 +0200 Subject: [PATCH 1/2] ad_sysref_gen: Fix sysref generation Toggle sysref output just if the sysref_en is asserted. --- library/common/ad_sysref_gen.v | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/library/common/ad_sysref_gen.v b/library/common/ad_sysref_gen.v index 0bf970890..61173acd1 100644 --- a/library/common/ad_sysref_gen.v +++ b/library/common/ad_sysref_gen.v @@ -77,8 +77,10 @@ module ad_sysref_gen ( // generate SYSREF always @(posedge core_clk) begin - if (counter == SYSREF_HALFPERIOD) begin - sysref_out <= ~sysref_out; + if (sysref_en_int) begin + if (counter == SYSREF_HALFPERIOD) begin + sysref_out <= ~sysref_out; + end end else begin sysref_out <= 1'b0; end From 1156aeac16188b9d18a0991a8ee988cc1e2e4135 Mon Sep 17 00:00:00 2001 From: Istvan Csomortani Date: Mon, 19 Dec 2016 18:07:05 +0200 Subject: [PATCH 2/2] ad_sysref_gen: Update SYSREF related constraints --- projects/ad6676evb/vc707/system_constr.xdc | 2 +- projects/ad6676evb/zc706/system_constr.xdc | 2 +- projects/fmcadc2/vc707/system_constr.xdc | 2 +- projects/fmcadc2/zc706/system_constr.xdc | 2 +- projects/fmcjesdadc1/kc705/system_constr.xdc | 2 +- projects/fmcjesdadc1/vc707/system_constr.xdc | 2 +- projects/fmcjesdadc1/zc706/system_constr.xdc | 2 +- 7 files changed, 7 insertions(+), 7 deletions(-) diff --git a/projects/ad6676evb/vc707/system_constr.xdc b/projects/ad6676evb/vc707/system_constr.xdc index e3c798d6d..2113457bd 100644 --- a/projects/ad6676evb/vc707/system_constr.xdc +++ b/projects/ad6676evb/vc707/system_constr.xdc @@ -36,5 +36,5 @@ create_clock -name rx_div_clk -period 10.00 [get_pins i_system_wrapper/system set_false_path -from [get_cells i_system_wrapper/system_i/axi_ad6676_jesd_rstgen/U0/PR_OUT_DFF[0].peripheral_reset_reg[0]] set_property shreg_extract no [get_cells -hier -filter {name =~ *sysref_en_m*}] -set_false_path -to [get_cells -hier -filter {name =~ *sysref_en_m* && IS_SEQUENTIAL}] +set_false_path -to [get_cells -hier -filter {name =~ *sysref_en_m1* && IS_SEQUENTIAL}] diff --git a/projects/ad6676evb/zc706/system_constr.xdc b/projects/ad6676evb/zc706/system_constr.xdc index 54b6d22d3..e73918db8 100644 --- a/projects/ad6676evb/zc706/system_constr.xdc +++ b/projects/ad6676evb/zc706/system_constr.xdc @@ -36,5 +36,5 @@ create_clock -name rx_div_clk -period 10.00 [get_pins i_system_wrapper/system set_false_path -from [get_cells i_system_wrapper/system_i/axi_ad6676_jesd_rstgen/U0/PR_OUT_DFF[0].peripheral_reset_reg[0]] set_property shreg_extract no [get_cells -hier -filter {name =~ *sysref_en_m*}] -set_false_path -to [get_cells -hier -filter {name =~ *sysref_en_m* && IS_SEQUENTIAL}] +set_false_path -to [get_cells -hier -filter {name =~ *sysref_en_m1* && IS_SEQUENTIAL}] diff --git a/projects/fmcadc2/vc707/system_constr.xdc b/projects/fmcadc2/vc707/system_constr.xdc index b0a63362c..f1caf236e 100644 --- a/projects/fmcadc2/vc707/system_constr.xdc +++ b/projects/fmcadc2/vc707/system_constr.xdc @@ -43,5 +43,5 @@ create_clock -name rx_div_clk -period 6.40 [get_pins i_system_wrapper/system_ set_false_path -from [get_cells i_system_wrapper/system_i/axi_ad9625_jesd_rstgen/U0/PR_OUT_DFF[0].peripheral_reset_reg[0]] set_property shreg_extract no [get_cells -hier -filter {name =~ *sysref_en_m*}] -set_false_path -to [get_cells -hier -filter {name =~ *sysref_en_m* && IS_SEQUENTIAL}] +set_false_path -to [get_cells -hier -filter {name =~ *sysref_en_m1* && IS_SEQUENTIAL}] diff --git a/projects/fmcadc2/zc706/system_constr.xdc b/projects/fmcadc2/zc706/system_constr.xdc index f811cf7de..1b4c18f41 100644 --- a/projects/fmcadc2/zc706/system_constr.xdc +++ b/projects/fmcadc2/zc706/system_constr.xdc @@ -43,5 +43,5 @@ create_clock -name rx_div_clk -period 6.40 [get_pins i_system_wrapper/system_ set_false_path -from [get_cells i_system_wrapper/system_i/axi_ad9625_jesd_rstgen/U0/PR_OUT_DFF[0].peripheral_reset_reg[0]] set_property shreg_extract no [get_cells -hier -filter {name =~ *sysref_en_m*}] -set_false_path -to [get_cells -hier -filter {name =~ *sysref_en_m* && IS_SEQUENTIAL}] +set_false_path -to [get_cells -hier -filter {name =~ *sysref_en_m1* && IS_SEQUENTIAL}] diff --git a/projects/fmcjesdadc1/kc705/system_constr.xdc b/projects/fmcjesdadc1/kc705/system_constr.xdc index 8a4142a24..ba04189fa 100644 --- a/projects/fmcjesdadc1/kc705/system_constr.xdc +++ b/projects/fmcjesdadc1/kc705/system_constr.xdc @@ -26,5 +26,5 @@ create_clock -name rx_div_clk -period 6.40 [get_pins i_system_wrapper/system_ set_false_path -from [get_cells i_system_wrapper/system_i/axi_ad9250_jesd_rstgen/U0/PR_OUT_DFF[0].peripheral_reset_reg[0]] set_property shreg_extract no [get_cells -hier -filter {name =~ *sysref_en_m*}] -set_false_path -to [get_cells -hier -filter {name =~ *sysref_en_m* && IS_SEQUENTIAL}] +set_false_path -to [get_cells -hier -filter {name =~ *sysref_en_m1* && IS_SEQUENTIAL}] diff --git a/projects/fmcjesdadc1/vc707/system_constr.xdc b/projects/fmcjesdadc1/vc707/system_constr.xdc index 42de9cede..ebeded59b 100644 --- a/projects/fmcjesdadc1/vc707/system_constr.xdc +++ b/projects/fmcjesdadc1/vc707/system_constr.xdc @@ -27,5 +27,5 @@ set_false_path -from [get_cells i_system_wrapper/system_i/axi_ad9250_jesd_rstgen set_false_path -to [get_cells i_system_wrapper/system_i/axi_ad9250_jesd/inst/rx_sysref_r_reg/D] set_property shreg_extract no [get_cells -hier -filter {name =~ *sysref_en_m*}] -set_false_path -to [get_cells -hier -filter {name =~ *sysref_en_m* && IS_SEQUENTIAL}] +set_false_path -to [get_cells -hier -filter {name =~ *sysref_en_m1* && IS_SEQUENTIAL}] diff --git a/projects/fmcjesdadc1/zc706/system_constr.xdc b/projects/fmcjesdadc1/zc706/system_constr.xdc index 97d65a600..963178e90 100644 --- a/projects/fmcjesdadc1/zc706/system_constr.xdc +++ b/projects/fmcjesdadc1/zc706/system_constr.xdc @@ -26,5 +26,5 @@ create_clock -name rx_div_clk -period 6.40 [get_pins i_system_wrapper/system_ set_false_path -from [get_cells i_system_wrapper/system_i/axi_ad9250_jesd_rstgen/U0/PR_OUT_DFF[0].peripheral_reset_reg[0]] set_property shreg_extract no [get_cells -hier -filter {name =~ *sysref_en_m*}] -set_false_path -to [get_cells -hier -filter {name =~ *sysref_en_m* && IS_SEQUENTIAL}] +set_false_path -to [get_cells -hier -filter {name =~ *sysref_en_m1* && IS_SEQUENTIAL}]