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Merge branch 'hdl_2016_r2' into dev

main
Istvan Csomortani 2016-12-20 12:41:57 +02:00
parent a48c4a41bc 1156aeac16
commit ca8b479cee
8 changed files with 11 additions and 9 deletions
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2
library/common/ad_sysref_gen.v
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@ -77,8 +77,10 @@ module ad_sysref_gen (
// generate SYSREF
always @(posedge core_clk) begin
if (sysref_en_int) begin
if (counter == SYSREF_HALFPERIOD) begin
sysref_out <= ~sysref_out;
end
end else begin
sysref_out <= 1'b0;
end

2
projects/ad6676evb/vc707/system_constr.xdc
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@ -36,5 +36,5 @@ create_clock -name rx_div_clk -period 10.00 [get_pins i_system_wrapper/system
set_false_path -from [get_cells i_system_wrapper/system_i/axi_ad6676_jesd_rstgen/U0/PR_OUT_DFF[0].peripheral_reset_reg[0]]
set_property shreg_extract no [get_cells -hier -filter {name =~ *sysref_en_m*}]
set_false_path -to [get_cells -hier -filter {name =~ *sysref_en_m* && IS_SEQUENTIAL}]
set_false_path -to [get_cells -hier -filter {name =~ *sysref_en_m1* && IS_SEQUENTIAL}]

2
projects/ad6676evb/zc706/system_constr.xdc
View File

@ -36,5 +36,5 @@ create_clock -name rx_div_clk -period 10.00 [get_pins i_system_wrapper/system
set_false_path -from [get_cells i_system_wrapper/system_i/axi_ad6676_jesd_rstgen/U0/PR_OUT_DFF[0].peripheral_reset_reg[0]]
set_property shreg_extract no [get_cells -hier -filter {name =~ *sysref_en_m*}]
set_false_path -to [get_cells -hier -filter {name =~ *sysref_en_m* && IS_SEQUENTIAL}]
set_false_path -to [get_cells -hier -filter {name =~ *sysref_en_m1* && IS_SEQUENTIAL}]

2
projects/fmcadc2/vc707/system_constr.xdc
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@ -43,5 +43,5 @@ create_clock -name rx_div_clk -period 6.40 [get_pins i_system_wrapper/system_
set_false_path -from [get_cells i_system_wrapper/system_i/axi_ad9625_jesd_rstgen/U0/PR_OUT_DFF[0].peripheral_reset_reg[0]]
set_property shreg_extract no [get_cells -hier -filter {name =~ *sysref_en_m*}]
set_false_path -to [get_cells -hier -filter {name =~ *sysref_en_m* && IS_SEQUENTIAL}]
set_false_path -to [get_cells -hier -filter {name =~ *sysref_en_m1* && IS_SEQUENTIAL}]

2
projects/fmcadc2/zc706/system_constr.xdc
View File

@ -43,5 +43,5 @@ create_clock -name rx_div_clk -period 6.40 [get_pins i_system_wrapper/system_
set_false_path -from [get_cells i_system_wrapper/system_i/axi_ad9625_jesd_rstgen/U0/PR_OUT_DFF[0].peripheral_reset_reg[0]]
set_property shreg_extract no [get_cells -hier -filter {name =~ *sysref_en_m*}]
set_false_path -to [get_cells -hier -filter {name =~ *sysref_en_m* && IS_SEQUENTIAL}]
set_false_path -to [get_cells -hier -filter {name =~ *sysref_en_m1* && IS_SEQUENTIAL}]

2
projects/fmcjesdadc1/kc705/system_constr.xdc
View File

@ -26,5 +26,5 @@ create_clock -name rx_div_clk -period 6.40 [get_pins i_system_wrapper/system_
set_false_path -from [get_cells i_system_wrapper/system_i/axi_ad9250_jesd_rstgen/U0/PR_OUT_DFF[0].peripheral_reset_reg[0]]
set_property shreg_extract no [get_cells -hier -filter {name =~ *sysref_en_m*}]
set_false_path -to [get_cells -hier -filter {name =~ *sysref_en_m* && IS_SEQUENTIAL}]
set_false_path -to [get_cells -hier -filter {name =~ *sysref_en_m1* && IS_SEQUENTIAL}]

2
projects/fmcjesdadc1/vc707/system_constr.xdc
View File

@ -27,5 +27,5 @@ set_false_path -from [get_cells i_system_wrapper/system_i/axi_ad9250_jesd_rstgen
set_false_path -to [get_cells i_system_wrapper/system_i/axi_ad9250_jesd/inst/rx_sysref_r_reg/D]
set_property shreg_extract no [get_cells -hier -filter {name =~ *sysref_en_m*}]
set_false_path -to [get_cells -hier -filter {name =~ *sysref_en_m* && IS_SEQUENTIAL}]
set_false_path -to [get_cells -hier -filter {name =~ *sysref_en_m1* && IS_SEQUENTIAL}]

2
projects/fmcjesdadc1/zc706/system_constr.xdc
View File

@ -26,5 +26,5 @@ create_clock -name rx_div_clk -period 6.40 [get_pins i_system_wrapper/system_
set_false_path -from [get_cells i_system_wrapper/system_i/axi_ad9250_jesd_rstgen/U0/PR_OUT_DFF[0].peripheral_reset_reg[0]]
set_property shreg_extract no [get_cells -hier -filter {name =~ *sysref_en_m*}]
set_false_path -to [get_cells -hier -filter {name =~ *sysref_en_m* && IS_SEQUENTIAL}]
set_false_path -to [get_cells -hier -filter {name =~ *sysref_en_m1* && IS_SEQUENTIAL}]