axi_ad9234: axi_ad9680 copy
Rejeesh Kutty
parent
fb5d212370
commit
ca9f7bf1f6
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// ***************************************************************************
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// ***************************************************************************
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// Copyright 2011(c) Analog Devices, Inc.
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//
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without modification,
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||||
// are permitted provided that the following conditions are met:
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||||
// - Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
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||||
// - Redistributions in binary form must reproduce the above copyright
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||||
// notice, this list of conditions and the following disclaimer in
|
||||
// the documentation and/or other materials provided with the
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||||
// distribution.
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// - Neither the name of Analog Devices, Inc. nor the names of its
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||||
// contributors may be used to endorse or promote products derived
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||||
// from this software without specific prior written permission.
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||||
// - The use of this software may or may not infringe the patent rights
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||||
// of one or more patent holders. This license does not release you
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||||
// from the requirement that you obtain separate licenses from these
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||||
// patent holders to use this software.
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// - Use of the software either in source or binary form, must be run
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// on or directly connected to an Analog Devices Inc. component.
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//
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// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
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// PARTICULAR PURPOSE ARE DISCLAIMED.
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//
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// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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||||
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
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||||
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module axi_ad9680 (
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// jesd interface
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// rx_clk is (line-rate/40)
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rx_clk,
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rx_data,
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// dma interface
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adc_clk,
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adc_enable_0,
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adc_valid_0,
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adc_data_0,
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adc_enable_1,
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adc_valid_1,
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adc_data_1,
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adc_dovf,
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adc_dunf,
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// axi interface
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s_axi_aclk,
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s_axi_aresetn,
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s_axi_awvalid,
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s_axi_awaddr,
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s_axi_awready,
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s_axi_wvalid,
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s_axi_wdata,
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s_axi_wstrb,
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s_axi_wready,
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s_axi_bvalid,
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s_axi_bresp,
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s_axi_bready,
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s_axi_arvalid,
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s_axi_araddr,
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s_axi_arready,
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s_axi_rvalid,
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s_axi_rresp,
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s_axi_rdata,
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s_axi_rready);
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parameter PCORE_ID = 0;
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parameter PCORE_DEVICE_TYPE = 0;
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parameter PCORE_IODELAY_GROUP = "adc_if_delay_group";
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parameter C_S_AXI_MIN_SIZE = 32'hffff;
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// jesd interface
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// rx_clk is (line-rate/40)
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input rx_clk;
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input [127:0] rx_data;
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// dma interface
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output adc_clk;
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output adc_enable_0;
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output adc_valid_0;
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output [63:0] adc_data_0;
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output adc_enable_1;
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output adc_valid_1;
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output [63:0] adc_data_1;
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input adc_dovf;
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input adc_dunf;
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// axi interface
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input s_axi_aclk;
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input s_axi_aresetn;
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input s_axi_awvalid;
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input [31:0] s_axi_awaddr;
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output s_axi_awready;
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input s_axi_wvalid;
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input [31:0] s_axi_wdata;
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input [ 3:0] s_axi_wstrb;
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output s_axi_wready;
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output s_axi_bvalid;
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output [ 1:0] s_axi_bresp;
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input s_axi_bready;
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input s_axi_arvalid;
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input [31:0] s_axi_araddr;
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output s_axi_arready;
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output s_axi_rvalid;
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output [ 1:0] s_axi_rresp;
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output [31:0] s_axi_rdata;
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input s_axi_rready;
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// internal registers
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reg up_status_pn_err = 'd0;
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reg up_status_pn_oos = 'd0;
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reg up_status_or = 'd0;
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reg [31:0] up_rdata = 'd0;
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reg up_ack = 'd0;
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// internal clocks & resets
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wire adc_rst;
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wire up_rstn;
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wire up_clk;
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// internal signals
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wire [55:0] adc_data_a_s;
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wire [55:0] adc_data_b_s;
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wire adc_or_a_s;
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wire adc_or_b_s;
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wire adc_status_s;
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wire [ 1:0] up_adc_pn_err_s;
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wire [ 1:0] up_adc_pn_oos_s;
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wire [ 1:0] up_adc_or_s;
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wire [31:0] up_rdata_s[0:2];
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wire up_ack_s[0:2];
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wire up_sel_s;
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wire up_wr_s;
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wire [13:0] up_addr_s;
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wire [31:0] up_wdata_s;
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// signal name changes
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assign up_clk = s_axi_aclk;
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assign up_rstn = s_axi_aresetn;
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// defaults
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assign adc_valid_0 = 1'b1;
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assign adc_valid_1 = 1'b1;
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// processor read interface
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always @(negedge up_rstn or posedge up_clk) begin
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if (up_rstn == 0) begin
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up_status_pn_err <= 'd0;
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up_status_pn_oos <= 'd0;
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up_status_or <= 'd0;
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up_rdata <= 'd0;
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up_ack <= 'd0;
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end else begin
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up_status_pn_err <= | up_adc_pn_err_s;
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up_status_pn_oos <= | up_adc_pn_oos_s;
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up_status_or <= | up_adc_or_s;
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up_rdata <= up_rdata_s[0] | up_rdata_s[1] | up_rdata_s[2];
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up_ack <= up_ack_s[0] | up_ack_s[1] | up_ack_s[2];
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end
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end
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// main (device interface)
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axi_ad9680_if i_if (
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.rx_clk (rx_clk),
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.rx_data (rx_data),
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.adc_clk (adc_clk),
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.adc_rst (adc_rst),
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.adc_data_a (adc_data_a_s),
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.adc_data_b (adc_data_b_s),
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.adc_or_a (adc_or_a_s),
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.adc_or_b (adc_or_b_s),
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.adc_status (adc_status_s));
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// channel
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axi_ad9680_channel #(.IQSEL(0), .CHID(0)) i_channel_0 (
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.adc_clk (adc_clk),
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.adc_rst (adc_rst),
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.adc_data (adc_data_a_s),
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.adc_or (adc_or_a_s),
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.adc_dfmt_data (adc_data_0),
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.adc_enable (adc_enable_0),
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.up_adc_pn_err (up_adc_pn_err_s[0]),
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.up_adc_pn_oos (up_adc_pn_oos_s[0]),
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.up_adc_or (up_adc_or_s[0]),
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.up_rstn (up_rstn),
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.up_clk (up_clk),
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.up_sel (up_sel_s),
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.up_wr (up_wr_s),
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.up_addr (up_addr_s),
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.up_wdata (up_wdata_s),
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.up_rdata (up_rdata_s[0]),
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.up_ack (up_ack_s[0]));
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// channel
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axi_ad9680_channel #(.IQSEL(1), .CHID(1)) i_channel_1 (
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.adc_clk (adc_clk),
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.adc_rst (adc_rst),
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.adc_data (adc_data_b_s),
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.adc_or (adc_or_b_s),
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.adc_dfmt_data (adc_data_1),
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.adc_enable (adc_enable_1),
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.up_adc_pn_err (up_adc_pn_err_s[1]),
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.up_adc_pn_oos (up_adc_pn_oos_s[1]),
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.up_adc_or (up_adc_or_s[1]),
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.up_rstn (up_rstn),
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.up_clk (up_clk),
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.up_sel (up_sel_s),
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.up_wr (up_wr_s),
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.up_addr (up_addr_s),
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.up_wdata (up_wdata_s),
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.up_rdata (up_rdata_s[1]),
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.up_ack (up_ack_s[1]));
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// common processor control
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up_adc_common #(.PCORE_ID(PCORE_ID)) i_up_adc_common (
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.mmcm_rst (),
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.adc_clk (adc_clk),
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.adc_rst (adc_rst),
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.adc_r1_mode (),
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.adc_ddr_edgesel (),
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.adc_pin_mode (),
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.adc_status (adc_status_s),
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.adc_status_ovf (adc_dovf),
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.adc_status_unf (adc_dunf),
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.adc_clk_ratio (32'd40),
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.up_status_pn_err (up_status_pn_err),
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.up_status_pn_oos (up_status_pn_oos),
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.up_status_or (up_status_or),
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.delay_clk (1'b0),
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.delay_rst (),
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.delay_sel (),
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.delay_rwn (),
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.delay_addr (),
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.delay_wdata (),
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.delay_rdata (5'd0),
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.delay_ack_t (1'b0),
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.delay_locked (1'b1),
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.drp_clk (1'd0),
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.drp_rst (),
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.drp_sel (),
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.drp_wr (),
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.drp_addr (),
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.drp_wdata (),
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.drp_rdata (16'd0),
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.drp_ready (1'd0),
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.drp_locked (1'd1),
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.up_usr_chanmax (),
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.adc_usr_chanmax (8'd1),
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.up_adc_gpio_in (32'd0),
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.up_adc_gpio_out (),
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.up_rstn (up_rstn),
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.up_clk (up_clk),
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.up_sel (up_sel_s),
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.up_wr (up_wr_s),
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.up_addr (up_addr_s),
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.up_wdata (up_wdata_s),
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.up_rdata (up_rdata_s[2]),
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.up_ack (up_ack_s[2]));
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// up bus interface
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up_axi i_up_axi (
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.up_rstn (up_rstn),
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.up_clk (up_clk),
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.up_axi_awvalid (s_axi_awvalid),
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.up_axi_awaddr (s_axi_awaddr),
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.up_axi_awready (s_axi_awready),
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.up_axi_wvalid (s_axi_wvalid),
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.up_axi_wdata (s_axi_wdata),
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.up_axi_wstrb (s_axi_wstrb),
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.up_axi_wready (s_axi_wready),
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.up_axi_bvalid (s_axi_bvalid),
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.up_axi_bresp (s_axi_bresp),
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.up_axi_bready (s_axi_bready),
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.up_axi_arvalid (s_axi_arvalid),
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.up_axi_araddr (s_axi_araddr),
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.up_axi_arready (s_axi_arready),
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.up_axi_rvalid (s_axi_rvalid),
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.up_axi_rresp (s_axi_rresp),
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.up_axi_rdata (s_axi_rdata),
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.up_axi_rready (s_axi_rready),
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.up_sel (up_sel_s),
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.up_wr (up_wr_s),
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.up_addr (up_addr_s),
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.up_wdata (up_wdata_s),
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.up_rdata (up_rdata),
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.up_ack (up_ack));
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endmodule
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// ***************************************************************************
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// ***************************************************************************
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@ -0,0 +1,183 @@
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// ***************************************************************************
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// ***************************************************************************
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// Copyright 2011(c) Analog Devices, Inc.
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//
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without modification,
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// are permitted provided that the following conditions are met:
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||||
// - Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
// - Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in
|
||||
// the documentation and/or other materials provided with the
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// distribution.
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// - Neither the name of Analog Devices, Inc. nor the names of its
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// contributors may be used to endorse or promote products derived
|
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// from this software without specific prior written permission.
|
||||
// - The use of this software may or may not infringe the patent rights
|
||||
// of one or more patent holders. This license does not release you
|
||||
// from the requirement that you obtain separate licenses from these
|
||||
// patent holders to use this software.
|
||||
// - Use of the software either in source or binary form, must be run
|
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// on or directly connected to an Analog Devices Inc. component.
|
||||
//
|
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// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
|
||||
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
|
||||
// PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
//
|
||||
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
|
||||
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
|
||||
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
|
||||
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
|
||||
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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// ADC channel-
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`timescale 1ns/100ps
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module axi_ad9680_channel (
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// adc interface
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adc_clk,
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adc_rst,
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adc_data,
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adc_or,
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// channel interface
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adc_dfmt_data,
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adc_enable,
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up_adc_pn_err,
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up_adc_pn_oos,
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up_adc_or,
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// processor interface
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up_rstn,
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up_clk,
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up_sel,
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up_wr,
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up_addr,
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up_wdata,
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up_rdata,
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up_ack);
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// parameters
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parameter IQSEL = 0;
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parameter CHID = 0;
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// adc interface
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input adc_clk;
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input adc_rst;
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input [55:0] adc_data;
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input adc_or;
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// channel interface
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output [63:0] adc_dfmt_data;
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output adc_enable;
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output up_adc_pn_err;
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output up_adc_pn_oos;
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output up_adc_or;
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// processor interface
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input up_rstn;
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input up_clk;
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input up_sel;
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input up_wr;
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input [13:0] up_addr;
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input [31:0] up_wdata;
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output [31:0] up_rdata;
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output up_ack;
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// internal signals
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wire adc_pn_oos_s;
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wire adc_pn_err_s;
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wire adc_dfmt_enable_s;
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wire adc_dfmt_type_s;
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wire adc_dfmt_se_s;
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wire [ 3:0] adc_pnseq_sel_s;
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// instantiations
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axi_ad9680_pnmon i_pnmon (
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.adc_clk (adc_clk),
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.adc_data (adc_data),
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.adc_pn_oos (adc_pn_oos_s),
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.adc_pn_err (adc_pn_err_s),
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.adc_pnseq_sel (adc_pnseq_sel_s));
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genvar n;
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generate
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for (n = 0; n < 4; n = n + 1) begin: g_ad_datafmt_1
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ad_datafmt #(.DATA_WIDTH(14)) i_ad_datafmt (
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.clk (adc_clk),
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.valid (1'b1),
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.data (adc_data[n*14+13:n*14]),
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.valid_out (),
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.data_out (adc_dfmt_data[n*16+15:n*16]),
|
||||
.dfmt_enable (adc_dfmt_enable_s),
|
||||
.dfmt_type (adc_dfmt_type_s),
|
||||
.dfmt_se (adc_dfmt_se_s));
|
||||
end
|
||||
endgenerate
|
||||
|
||||
up_adc_channel #(.PCORE_ADC_CHID(CHID)) i_up_adc_channel (
|
||||
.adc_clk (adc_clk),
|
||||
.adc_rst (adc_rst),
|
||||
.adc_enable (adc_enable),
|
||||
.adc_iqcor_enb (),
|
||||
.adc_dcfilt_enb (),
|
||||
.adc_dfmt_se (adc_dfmt_se_s),
|
||||
.adc_dfmt_type (adc_dfmt_type_s),
|
||||
.adc_dfmt_enable (adc_dfmt_enable_s),
|
||||
.adc_dcfilt_offset (),
|
||||
.adc_dcfilt_coeff (),
|
||||
.adc_iqcor_coeff_1 (),
|
||||
.adc_iqcor_coeff_2 (),
|
||||
.adc_pnseq_sel (adc_pnseq_sel_s),
|
||||
.adc_data_sel (),
|
||||
.adc_pn_err (adc_pn_err_s),
|
||||
.adc_pn_oos (adc_pn_oos_s),
|
||||
.adc_or (adc_or),
|
||||
.up_adc_pn_err (up_adc_pn_err),
|
||||
.up_adc_pn_oos (up_adc_pn_oos),
|
||||
.up_adc_or (up_adc_or),
|
||||
.up_usr_datatype_be (),
|
||||
.up_usr_datatype_signed (),
|
||||
.up_usr_datatype_shift (),
|
||||
.up_usr_datatype_total_bits (),
|
||||
.up_usr_datatype_bits (),
|
||||
.up_usr_decimation_m (),
|
||||
.up_usr_decimation_n (),
|
||||
.adc_usr_datatype_be (1'b0),
|
||||
.adc_usr_datatype_signed (1'b1),
|
||||
.adc_usr_datatype_shift (8'd0),
|
||||
.adc_usr_datatype_total_bits (8'd16),
|
||||
.adc_usr_datatype_bits (8'd16),
|
||||
.adc_usr_decimation_m (16'd1),
|
||||
.adc_usr_decimation_n (16'd1),
|
||||
.up_rstn (up_rstn),
|
||||
.up_clk (up_clk),
|
||||
.up_sel (up_sel),
|
||||
.up_wr (up_wr),
|
||||
.up_addr (up_addr),
|
||||
.up_wdata (up_wdata),
|
||||
.up_rdata (up_rdata),
|
||||
.up_ack (up_ack));
|
||||
|
||||
endmodule
|
||||
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
||||
|
|
@ -0,0 +1,6 @@
|
|||
|
||||
set_clock_groups -asynchronous -group [get_clocks -of_objects [get_ports adc_clk]]
|
||||
set_clock_groups -asynchronous -group [get_clocks -of_objects [get_ports s_axi_aclk]]
|
||||
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,132 @@
|
|||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright 2011(c) Analog Devices, Inc.
|
||||
//
|
||||
// All rights reserved.
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without modification,
|
||||
// are permitted provided that the following conditions are met:
|
||||
// - Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
// - Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in
|
||||
// the documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
// - Neither the name of Analog Devices, Inc. nor the names of its
|
||||
// contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
// - The use of this software may or may not infringe the patent rights
|
||||
// of one or more patent holders. This license does not release you
|
||||
// from the requirement that you obtain separate licenses from these
|
||||
// patent holders to use this software.
|
||||
// - Use of the software either in source or binary form, must be run
|
||||
// on or directly connected to an Analog Devices Inc. component.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
|
||||
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
|
||||
// PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
//
|
||||
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
|
||||
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
|
||||
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
|
||||
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
|
||||
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// This is the LVDS/DDR interface
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
module axi_ad9680_if (
|
||||
|
||||
// jesd interface
|
||||
// rx_clk is (line-rate/40)
|
||||
|
||||
rx_clk,
|
||||
rx_data,
|
||||
|
||||
// adc data output
|
||||
|
||||
adc_clk,
|
||||
adc_rst,
|
||||
adc_data_a,
|
||||
adc_data_b,
|
||||
adc_or_a,
|
||||
adc_or_b,
|
||||
adc_status);
|
||||
|
||||
// jesd interface
|
||||
// rx_clk is (line-rate/40)
|
||||
|
||||
input rx_clk;
|
||||
input [127:0] rx_data;
|
||||
|
||||
// adc data output
|
||||
|
||||
output adc_clk;
|
||||
input adc_rst;
|
||||
output [55:0] adc_data_a;
|
||||
output [55:0] adc_data_b;
|
||||
output adc_or_a;
|
||||
output adc_or_b;
|
||||
output adc_status;
|
||||
|
||||
// internal registers
|
||||
|
||||
reg adc_status = 'd0;
|
||||
|
||||
// internal signals
|
||||
|
||||
wire [15:0] adc_data_a_s3_s;
|
||||
wire [15:0] adc_data_a_s2_s;
|
||||
wire [15:0] adc_data_a_s1_s;
|
||||
wire [15:0] adc_data_a_s0_s;
|
||||
wire [15:0] adc_data_b_s3_s;
|
||||
wire [15:0] adc_data_b_s2_s;
|
||||
wire [15:0] adc_data_b_s1_s;
|
||||
wire [15:0] adc_data_b_s0_s;
|
||||
|
||||
// adc clock is the reference clock
|
||||
|
||||
assign adc_clk = rx_clk;
|
||||
assign adc_or_a = 1'b0;
|
||||
assign adc_or_b = 1'b0;
|
||||
|
||||
// adc channels
|
||||
|
||||
assign adc_data_a = { adc_data_a_s3_s[13:0], adc_data_a_s2_s[13:0],
|
||||
adc_data_a_s1_s[13:0], adc_data_a_s0_s[13:0]};
|
||||
|
||||
assign adc_data_b = { adc_data_b_s3_s[13:0], adc_data_b_s2_s[13:0],
|
||||
adc_data_b_s1_s[13:0], adc_data_b_s0_s[13:0]};
|
||||
|
||||
// data multiplex
|
||||
|
||||
assign adc_data_a_s3_s = {rx_data[ 57: 56], rx_data[ 31: 24], rx_data[ 63: 58]};
|
||||
assign adc_data_a_s2_s = {rx_data[ 49: 48], rx_data[ 23: 16], rx_data[ 55: 50]};
|
||||
assign adc_data_a_s1_s = {rx_data[ 41: 40], rx_data[ 15: 8], rx_data[ 47: 42]};
|
||||
assign adc_data_a_s0_s = {rx_data[ 33: 32], rx_data[ 7: 0], rx_data[ 39: 34]};
|
||||
|
||||
assign adc_data_b_s3_s = {rx_data[121:120], rx_data[ 95: 88], rx_data[127:122]};
|
||||
assign adc_data_b_s2_s = {rx_data[113:112], rx_data[ 87: 80], rx_data[119:114]};
|
||||
assign adc_data_b_s1_s = {rx_data[105:104], rx_data[ 79: 72], rx_data[111:106]};
|
||||
assign adc_data_b_s0_s = {rx_data[ 97: 96], rx_data[ 71: 64], rx_data[103: 98]};
|
||||
|
||||
// status
|
||||
|
||||
always @(posedge rx_clk) begin
|
||||
if (adc_rst == 1'b1) begin
|
||||
adc_status <= 1'b0;
|
||||
end else begin
|
||||
adc_status <= 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
||||
|
|
@ -0,0 +1,29 @@
|
|||
# ip
|
||||
|
||||
source ../scripts/adi_env.tcl
|
||||
source $ad_hdl_dir/library/scripts/adi_ip.tcl
|
||||
|
||||
adi_ip_create axi_ad9680
|
||||
adi_ip_files axi_ad9680 [list \
|
||||
"$ad_hdl_dir/library/common/ad_rst.v" \
|
||||
"$ad_hdl_dir/library/common/ad_pnmon.v" \
|
||||
"$ad_hdl_dir/library/common/ad_datafmt.v" \
|
||||
"$ad_hdl_dir/library/common/up_axi.v" \
|
||||
"$ad_hdl_dir/library/common/up_xfer_cntrl.v" \
|
||||
"$ad_hdl_dir/library/common/up_xfer_status.v" \
|
||||
"$ad_hdl_dir/library/common/up_clock_mon.v" \
|
||||
"$ad_hdl_dir/library/common/up_drp_cntrl.v" \
|
||||
"$ad_hdl_dir/library/common/up_delay_cntrl.v" \
|
||||
"$ad_hdl_dir/library/common/up_adc_common.v" \
|
||||
"$ad_hdl_dir/library/common/up_adc_channel.v" \
|
||||
"axi_ad9680_pnmon.v" \
|
||||
"axi_ad9680_channel.v" \
|
||||
"axi_ad9680_if.v" \
|
||||
"axi_ad9680.v" ]
|
||||
|
||||
adi_ip_properties axi_ad9680
|
||||
adi_ip_constraints axi_ad9680 [list \
|
||||
"axi_ad9680_constr.xdc" ]
|
||||
|
||||
ipx::save_core [ipx::current_core]
|
||||
|
||||
|
|
@ -0,0 +1,244 @@
|
|||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright 2011(c) Analog Devices, Inc.
|
||||
//
|
||||
// All rights reserved.
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without modification,
|
||||
// are permitted provided that the following conditions are met:
|
||||
// - Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
// - Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in
|
||||
// the documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
// - Neither the name of Analog Devices, Inc. nor the names of its
|
||||
// contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
// - The use of this software may or may not infringe the patent rights
|
||||
// of one or more patent holders. This license does not release you
|
||||
// from the requirement that you obtain separate licenses from these
|
||||
// patent holders to use this software.
|
||||
// - Use of the software either in source or binary form, must be run
|
||||
// on or directly connected to an Analog Devices Inc. component.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
|
||||
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
|
||||
// PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
//
|
||||
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
|
||||
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
|
||||
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
|
||||
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
|
||||
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// PN monitors
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
module axi_ad9680_pnmon (
|
||||
|
||||
// adc interface
|
||||
|
||||
adc_clk,
|
||||
adc_data,
|
||||
|
||||
// pn out of sync and error
|
||||
|
||||
adc_pn_oos,
|
||||
adc_pn_err,
|
||||
|
||||
// processor interface PN9 (0x0), PN23 (0x1)
|
||||
|
||||
adc_pnseq_sel);
|
||||
|
||||
// adc interface
|
||||
|
||||
input adc_clk;
|
||||
input [55:0] adc_data;
|
||||
|
||||
// pn out of sync and error
|
||||
|
||||
output adc_pn_oos;
|
||||
output adc_pn_err;
|
||||
|
||||
// processor interface PN9 (0x0), PN23 (0x1)
|
||||
|
||||
input [ 3:0] adc_pnseq_sel;
|
||||
|
||||
// internal registers
|
||||
|
||||
reg [55:0] adc_pn_data_in = 'd0;
|
||||
reg [55:0] adc_pn_data_pn = 'd0;
|
||||
|
||||
// internal signals
|
||||
|
||||
wire [55:0] adc_pn_data_pn_s;
|
||||
|
||||
// PN23 function
|
||||
|
||||
function [55:0] pn23;
|
||||
input [55:0] din;
|
||||
reg [55:0] dout;
|
||||
begin
|
||||
dout[55] = din[22] ^ din[17];
|
||||
dout[54] = din[21] ^ din[16];
|
||||
dout[53] = din[20] ^ din[15];
|
||||
dout[52] = din[19] ^ din[14];
|
||||
dout[51] = din[18] ^ din[13];
|
||||
dout[50] = din[17] ^ din[12];
|
||||
dout[49] = din[16] ^ din[11];
|
||||
dout[48] = din[15] ^ din[10];
|
||||
dout[47] = din[14] ^ din[ 9];
|
||||
dout[46] = din[13] ^ din[ 8];
|
||||
dout[45] = din[12] ^ din[ 7];
|
||||
dout[44] = din[11] ^ din[ 6];
|
||||
dout[43] = din[10] ^ din[ 5];
|
||||
dout[42] = din[ 9] ^ din[ 4];
|
||||
dout[41] = din[ 8] ^ din[ 3];
|
||||
dout[40] = din[ 7] ^ din[ 2];
|
||||
dout[39] = din[ 6] ^ din[ 1];
|
||||
dout[38] = din[ 5] ^ din[ 0];
|
||||
dout[37] = din[ 4] ^ din[22] ^ din[17];
|
||||
dout[36] = din[ 3] ^ din[21] ^ din[16];
|
||||
dout[35] = din[ 2] ^ din[20] ^ din[15];
|
||||
dout[34] = din[ 1] ^ din[19] ^ din[14];
|
||||
dout[33] = din[ 0] ^ din[18] ^ din[13];
|
||||
dout[32] = din[22] ^ din[12];
|
||||
dout[31] = din[21] ^ din[11];
|
||||
dout[30] = din[20] ^ din[10];
|
||||
dout[29] = din[19] ^ din[ 9];
|
||||
dout[28] = din[18] ^ din[ 8];
|
||||
dout[27] = din[17] ^ din[ 7];
|
||||
dout[26] = din[16] ^ din[ 6];
|
||||
dout[25] = din[15] ^ din[ 5];
|
||||
dout[24] = din[14] ^ din[ 4];
|
||||
dout[23] = din[13] ^ din[ 3];
|
||||
dout[22] = din[12] ^ din[ 2];
|
||||
dout[21] = din[11] ^ din[ 1];
|
||||
dout[20] = din[10] ^ din[ 0];
|
||||
dout[19] = din[ 9] ^ din[22] ^ din[17];
|
||||
dout[18] = din[ 8] ^ din[21] ^ din[16];
|
||||
dout[17] = din[ 7] ^ din[20] ^ din[15];
|
||||
dout[16] = din[ 6] ^ din[19] ^ din[14];
|
||||
dout[15] = din[ 5] ^ din[18] ^ din[13];
|
||||
dout[14] = din[ 4] ^ din[17] ^ din[12];
|
||||
dout[13] = din[ 3] ^ din[16] ^ din[11];
|
||||
dout[12] = din[ 2] ^ din[15] ^ din[10];
|
||||
dout[11] = din[ 1] ^ din[14] ^ din[ 9];
|
||||
dout[10] = din[ 0] ^ din[13] ^ din[ 8];
|
||||
dout[ 9] = din[22] ^ din[12] ^ din[17] ^ din[ 7];
|
||||
dout[ 8] = din[21] ^ din[11] ^ din[16] ^ din[ 6];
|
||||
dout[ 7] = din[20] ^ din[10] ^ din[15] ^ din[ 5];
|
||||
dout[ 6] = din[19] ^ din[ 9] ^ din[14] ^ din[ 4];
|
||||
dout[ 5] = din[18] ^ din[ 8] ^ din[13] ^ din[ 3];
|
||||
dout[ 4] = din[17] ^ din[ 7] ^ din[12] ^ din[ 2];
|
||||
dout[ 3] = din[16] ^ din[ 6] ^ din[11] ^ din[ 1];
|
||||
dout[ 2] = din[15] ^ din[ 5] ^ din[10] ^ din[ 0];
|
||||
dout[ 1] = din[14] ^ din[ 4] ^ din[ 9] ^ din[22] ^ din[17];
|
||||
dout[ 0] = din[13] ^ din[ 3] ^ din[ 8] ^ din[21] ^ din[16];
|
||||
pn23 = dout;
|
||||
end
|
||||
endfunction
|
||||
|
||||
// PN9 function
|
||||
|
||||
function [55:0] pn9;
|
||||
input [55:0] din;
|
||||
reg [55:0] dout;
|
||||
begin
|
||||
dout[55] = din[ 8] ^ din[ 4];
|
||||
dout[54] = din[ 7] ^ din[ 3];
|
||||
dout[53] = din[ 6] ^ din[ 2];
|
||||
dout[52] = din[ 5] ^ din[ 1];
|
||||
dout[51] = din[ 4] ^ din[ 0];
|
||||
dout[50] = din[ 3] ^ din[ 8] ^ din[ 4];
|
||||
dout[49] = din[ 2] ^ din[ 7] ^ din[ 3];
|
||||
dout[48] = din[ 1] ^ din[ 6] ^ din[ 2];
|
||||
dout[47] = din[ 0] ^ din[ 5] ^ din[ 1];
|
||||
dout[46] = din[ 8] ^ din[ 0];
|
||||
dout[45] = din[ 7] ^ din[ 8] ^ din[ 4];
|
||||
dout[44] = din[ 6] ^ din[ 7] ^ din[ 3];
|
||||
dout[43] = din[ 5] ^ din[ 6] ^ din[ 2];
|
||||
dout[42] = din[ 4] ^ din[ 5] ^ din[ 1];
|
||||
dout[41] = din[ 3] ^ din[ 4] ^ din[ 0];
|
||||
dout[40] = din[ 2] ^ din[ 3] ^ din[ 8] ^ din[ 4];
|
||||
dout[39] = din[ 1] ^ din[ 2] ^ din[ 7] ^ din[ 3];
|
||||
dout[38] = din[ 0] ^ din[ 1] ^ din[ 6] ^ din[ 2];
|
||||
dout[37] = din[ 8] ^ din[ 0] ^ din[ 4] ^ din[ 5] ^ din[ 1];
|
||||
dout[36] = din[ 7] ^ din[ 8] ^ din[ 3] ^ din[ 0];
|
||||
dout[35] = din[ 6] ^ din[ 7] ^ din[ 2] ^ din[ 8] ^ din[ 4];
|
||||
dout[34] = din[ 5] ^ din[ 6] ^ din[ 1] ^ din[ 7] ^ din[ 3];
|
||||
dout[33] = din[ 4] ^ din[ 5] ^ din[ 0] ^ din[ 6] ^ din[ 2];
|
||||
dout[32] = din[ 3] ^ din[ 8] ^ din[ 5] ^ din[ 1];
|
||||
dout[31] = din[ 2] ^ din[ 4] ^ din[ 7] ^ din[ 0];
|
||||
dout[30] = din[ 1] ^ din[ 3] ^ din[ 6] ^ din[ 8] ^ din[ 4];
|
||||
dout[29] = din[ 0] ^ din[ 2] ^ din[ 5] ^ din[ 7] ^ din[ 3];
|
||||
dout[28] = din[ 8] ^ din[ 1] ^ din[ 6] ^ din[ 2];
|
||||
dout[27] = din[ 7] ^ din[ 0] ^ din[ 5] ^ din[ 1];
|
||||
dout[26] = din[ 6] ^ din[ 8] ^ din[ 0];
|
||||
dout[25] = din[ 5] ^ din[ 7] ^ din[ 8] ^ din[ 4];
|
||||
dout[24] = din[ 4] ^ din[ 6] ^ din[ 7] ^ din[ 3];
|
||||
dout[23] = din[ 3] ^ din[ 5] ^ din[ 6] ^ din[ 2];
|
||||
dout[22] = din[ 2] ^ din[ 4] ^ din[ 5] ^ din[ 1];
|
||||
dout[21] = din[ 1] ^ din[ 3] ^ din[ 4] ^ din[ 0];
|
||||
dout[20] = din[ 0] ^ din[ 2] ^ din[ 3] ^ din[ 8] ^ din[ 4];
|
||||
dout[19] = din[ 8] ^ din[ 1] ^ din[ 2] ^ din[ 4] ^ din[ 7] ^ din[ 3];
|
||||
dout[18] = din[ 7] ^ din[ 0] ^ din[ 1] ^ din[ 3] ^ din[ 6] ^ din[ 2];
|
||||
dout[17] = din[ 6] ^ din[ 8] ^ din[ 0] ^ din[ 2] ^ din[ 4] ^ din[ 5] ^ din[ 1];
|
||||
dout[16] = din[ 5] ^ din[ 7] ^ din[ 8] ^ din[ 1] ^ din[ 3] ^ din[ 0];
|
||||
dout[15] = din[ 6] ^ din[ 7] ^ din[ 0] ^ din[ 2] ^ din[ 8];
|
||||
dout[14] = din[ 5] ^ din[ 6] ^ din[ 8] ^ din[ 1] ^ din[ 4] ^ din[ 7];
|
||||
dout[13] = din[ 4] ^ din[ 5] ^ din[ 7] ^ din[ 0] ^ din[ 3] ^ din[ 6];
|
||||
dout[12] = din[ 3] ^ din[ 6] ^ din[ 8] ^ din[ 2] ^ din[ 5];
|
||||
dout[11] = din[ 2] ^ din[ 4] ^ din[ 5] ^ din[ 7] ^ din[ 1];
|
||||
dout[10] = din[ 1] ^ din[ 4] ^ din[ 3] ^ din[ 6] ^ din[ 0];
|
||||
dout[ 9] = din[ 0] ^ din[ 3] ^ din[ 2] ^ din[ 5] ^ din[ 8] ^ din[ 4];
|
||||
dout[ 8] = din[ 8] ^ din[ 2] ^ din[ 1] ^ din[ 7] ^ din[ 3];
|
||||
dout[ 7] = din[ 7] ^ din[ 1] ^ din[ 0] ^ din[ 6] ^ din[ 2];
|
||||
dout[ 6] = din[ 6] ^ din[ 0] ^ din[ 8] ^ din[ 4] ^ din[ 5] ^ din[ 1];
|
||||
dout[ 5] = din[ 5] ^ din[ 8] ^ din[ 7] ^ din[ 3] ^ din[ 0];
|
||||
dout[ 4] = din[ 7] ^ din[ 6] ^ din[ 2] ^ din[ 8];
|
||||
dout[ 3] = din[ 6] ^ din[ 5] ^ din[ 1] ^ din[ 7];
|
||||
dout[ 2] = din[ 4] ^ din[ 5] ^ din[ 0] ^ din[ 6];
|
||||
dout[ 1] = din[ 3] ^ din[ 8] ^ din[ 5];
|
||||
dout[ 0] = din[ 2] ^ din[ 4] ^ din[ 7];
|
||||
pn9 = dout;
|
||||
end
|
||||
endfunction
|
||||
|
||||
// pn sequence select
|
||||
|
||||
assign adc_pn_data_pn_s = (adc_pn_oos == 1'b1) ? adc_pn_data_in : adc_pn_data_pn;
|
||||
|
||||
always @(posedge adc_clk) begin
|
||||
adc_pn_data_in <= { ~adc_data[13], adc_data[12: 0],
|
||||
~adc_data[27], adc_data[26:14],
|
||||
~adc_data[41], adc_data[40:28],
|
||||
~adc_data[55], adc_data[54:42]};
|
||||
if (adc_pnseq_sel == 4'd0) begin
|
||||
adc_pn_data_pn <= pn9(adc_pn_data_pn_s);
|
||||
end else begin
|
||||
adc_pn_data_pn <= pn23(adc_pn_data_pn_s);
|
||||
end
|
||||
end
|
||||
|
||||
// pn oos & pn err
|
||||
|
||||
ad_pnmon #(.DATA_WIDTH(56)) i_pnmon (
|
||||
.adc_clk (adc_clk),
|
||||
.adc_valid_in (1'b1),
|
||||
.adc_data_in (adc_pn_data_in),
|
||||
.adc_data_pn (adc_pn_data_pn),
|
||||
.adc_pn_oos (adc_pn_oos),
|
||||
.adc_pn_err (adc_pn_err));
|
||||
|
||||
endmodule
|
||||
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
||||
Loading…
Reference in New Issue