diff --git a/library/axi_ad9234/axi_ad9234.v b/library/axi_ad9234/axi_ad9234.v new file mode 100644 index 000000000..efcf4c366 --- /dev/null +++ b/library/axi_ad9234/axi_ad9234.v @@ -0,0 +1,323 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2011(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module axi_ad9680 ( + + // jesd interface + // rx_clk is (line-rate/40) + + rx_clk, + rx_data, + + // dma interface + + adc_clk, + adc_enable_0, + adc_valid_0, + adc_data_0, + adc_enable_1, + adc_valid_1, + adc_data_1, + adc_dovf, + adc_dunf, + + // axi interface + + s_axi_aclk, + s_axi_aresetn, + s_axi_awvalid, + s_axi_awaddr, + s_axi_awready, + s_axi_wvalid, + s_axi_wdata, + s_axi_wstrb, + s_axi_wready, + s_axi_bvalid, + s_axi_bresp, + s_axi_bready, + s_axi_arvalid, + s_axi_araddr, + s_axi_arready, + s_axi_rvalid, + s_axi_rresp, + s_axi_rdata, + s_axi_rready); + + parameter PCORE_ID = 0; + parameter PCORE_DEVICE_TYPE = 0; + parameter PCORE_IODELAY_GROUP = "adc_if_delay_group"; + parameter C_S_AXI_MIN_SIZE = 32'hffff; + + // jesd interface + // rx_clk is (line-rate/40) + + input rx_clk; + input [127:0] rx_data; + + // dma interface + + output adc_clk; + output adc_enable_0; + output adc_valid_0; + output [63:0] adc_data_0; + output adc_enable_1; + output adc_valid_1; + output [63:0] adc_data_1; + input adc_dovf; + input adc_dunf; + + // axi interface + + input s_axi_aclk; + input s_axi_aresetn; + input s_axi_awvalid; + input [31:0] s_axi_awaddr; + output s_axi_awready; + input s_axi_wvalid; + input [31:0] s_axi_wdata; + input [ 3:0] s_axi_wstrb; + output s_axi_wready; + output s_axi_bvalid; + output [ 1:0] s_axi_bresp; + input s_axi_bready; + input s_axi_arvalid; + input [31:0] s_axi_araddr; + output s_axi_arready; + output s_axi_rvalid; + output [ 1:0] s_axi_rresp; + output [31:0] s_axi_rdata; + input s_axi_rready; + + // internal registers + + reg up_status_pn_err = 'd0; + reg up_status_pn_oos = 'd0; + reg up_status_or = 'd0; + reg [31:0] up_rdata = 'd0; + reg up_ack = 'd0; + + // internal clocks & resets + + wire adc_rst; + wire up_rstn; + wire up_clk; + + // internal signals + + wire [55:0] adc_data_a_s; + wire [55:0] adc_data_b_s; + wire adc_or_a_s; + wire adc_or_b_s; + wire adc_status_s; + wire [ 1:0] up_adc_pn_err_s; + wire [ 1:0] up_adc_pn_oos_s; + wire [ 1:0] up_adc_or_s; + wire [31:0] up_rdata_s[0:2]; + wire up_ack_s[0:2]; + wire up_sel_s; + wire up_wr_s; + wire [13:0] up_addr_s; + wire [31:0] up_wdata_s; + + // signal name changes + + assign up_clk = s_axi_aclk; + assign up_rstn = s_axi_aresetn; + + // defaults + + assign adc_valid_0 = 1'b1; + assign adc_valid_1 = 1'b1; + + // processor read interface + + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 0) begin + up_status_pn_err <= 'd0; + up_status_pn_oos <= 'd0; + up_status_or <= 'd0; + up_rdata <= 'd0; + up_ack <= 'd0; + end else begin + up_status_pn_err <= | up_adc_pn_err_s; + up_status_pn_oos <= | up_adc_pn_oos_s; + up_status_or <= | up_adc_or_s; + up_rdata <= up_rdata_s[0] | up_rdata_s[1] | up_rdata_s[2]; + up_ack <= up_ack_s[0] | up_ack_s[1] | up_ack_s[2]; + end + end + + // main (device interface) + + axi_ad9680_if i_if ( + .rx_clk (rx_clk), + .rx_data (rx_data), + .adc_clk (adc_clk), + .adc_rst (adc_rst), + .adc_data_a (adc_data_a_s), + .adc_data_b (adc_data_b_s), + .adc_or_a (adc_or_a_s), + .adc_or_b (adc_or_b_s), + .adc_status (adc_status_s)); + + // channel + + axi_ad9680_channel #(.IQSEL(0), .CHID(0)) i_channel_0 ( + .adc_clk (adc_clk), + .adc_rst (adc_rst), + .adc_data (adc_data_a_s), + .adc_or (adc_or_a_s), + .adc_dfmt_data (adc_data_0), + .adc_enable (adc_enable_0), + .up_adc_pn_err (up_adc_pn_err_s[0]), + .up_adc_pn_oos (up_adc_pn_oos_s[0]), + .up_adc_or (up_adc_or_s[0]), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_sel (up_sel_s), + .up_wr (up_wr_s), + .up_addr (up_addr_s), + .up_wdata (up_wdata_s), + .up_rdata (up_rdata_s[0]), + .up_ack (up_ack_s[0])); + + // channel + + axi_ad9680_channel #(.IQSEL(1), .CHID(1)) i_channel_1 ( + .adc_clk (adc_clk), + .adc_rst (adc_rst), + .adc_data (adc_data_b_s), + .adc_or (adc_or_b_s), + .adc_dfmt_data (adc_data_1), + .adc_enable (adc_enable_1), + .up_adc_pn_err (up_adc_pn_err_s[1]), + .up_adc_pn_oos (up_adc_pn_oos_s[1]), + .up_adc_or (up_adc_or_s[1]), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_sel (up_sel_s), + .up_wr (up_wr_s), + .up_addr (up_addr_s), + .up_wdata (up_wdata_s), + .up_rdata (up_rdata_s[1]), + .up_ack (up_ack_s[1])); + + // common processor control + + up_adc_common #(.PCORE_ID(PCORE_ID)) i_up_adc_common ( + .mmcm_rst (), + .adc_clk (adc_clk), + .adc_rst (adc_rst), + .adc_r1_mode (), + .adc_ddr_edgesel (), + .adc_pin_mode (), + .adc_status (adc_status_s), + .adc_status_ovf (adc_dovf), + .adc_status_unf (adc_dunf), + .adc_clk_ratio (32'd40), + .up_status_pn_err (up_status_pn_err), + .up_status_pn_oos (up_status_pn_oos), + .up_status_or (up_status_or), + .delay_clk (1'b0), + .delay_rst (), + .delay_sel (), + .delay_rwn (), + .delay_addr (), + .delay_wdata (), + .delay_rdata (5'd0), + .delay_ack_t (1'b0), + .delay_locked (1'b1), + .drp_clk (1'd0), + .drp_rst (), + .drp_sel (), + .drp_wr (), + .drp_addr (), + .drp_wdata (), + .drp_rdata (16'd0), + .drp_ready (1'd0), + .drp_locked (1'd1), + .up_usr_chanmax (), + .adc_usr_chanmax (8'd1), + .up_adc_gpio_in (32'd0), + .up_adc_gpio_out (), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_sel (up_sel_s), + .up_wr (up_wr_s), + .up_addr (up_addr_s), + .up_wdata (up_wdata_s), + .up_rdata (up_rdata_s[2]), + .up_ack (up_ack_s[2])); + + // up bus interface + + up_axi i_up_axi ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_axi_awvalid (s_axi_awvalid), + .up_axi_awaddr (s_axi_awaddr), + .up_axi_awready (s_axi_awready), + .up_axi_wvalid (s_axi_wvalid), + .up_axi_wdata (s_axi_wdata), + .up_axi_wstrb (s_axi_wstrb), + .up_axi_wready (s_axi_wready), + .up_axi_bvalid (s_axi_bvalid), + .up_axi_bresp (s_axi_bresp), + .up_axi_bready (s_axi_bready), + .up_axi_arvalid (s_axi_arvalid), + .up_axi_araddr (s_axi_araddr), + .up_axi_arready (s_axi_arready), + .up_axi_rvalid (s_axi_rvalid), + .up_axi_rresp (s_axi_rresp), + .up_axi_rdata (s_axi_rdata), + .up_axi_rready (s_axi_rready), + .up_sel (up_sel_s), + .up_wr (up_wr_s), + .up_addr (up_addr_s), + .up_wdata (up_wdata_s), + .up_rdata (up_rdata), + .up_ack (up_ack)); + +endmodule + +// *************************************************************************** +// *************************************************************************** + diff --git a/library/axi_ad9234/axi_ad9234_channel.v b/library/axi_ad9234/axi_ad9234_channel.v new file mode 100644 index 000000000..b80395265 --- /dev/null +++ b/library/axi_ad9234/axi_ad9234_channel.v @@ -0,0 +1,183 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2011(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** +// *************************************************************************** +// *************************************************************************** +// ADC channel- + +`timescale 1ns/100ps + +module axi_ad9680_channel ( + + // adc interface + + adc_clk, + adc_rst, + adc_data, + adc_or, + + // channel interface + + adc_dfmt_data, + adc_enable, + up_adc_pn_err, + up_adc_pn_oos, + up_adc_or, + + // processor interface + + up_rstn, + up_clk, + up_sel, + up_wr, + up_addr, + up_wdata, + up_rdata, + up_ack); + + // parameters + + parameter IQSEL = 0; + parameter CHID = 0; + + // adc interface + + input adc_clk; + input adc_rst; + input [55:0] adc_data; + input adc_or; + + // channel interface + + output [63:0] adc_dfmt_data; + output adc_enable; + output up_adc_pn_err; + output up_adc_pn_oos; + output up_adc_or; + + // processor interface + + input up_rstn; + input up_clk; + input up_sel; + input up_wr; + input [13:0] up_addr; + input [31:0] up_wdata; + output [31:0] up_rdata; + output up_ack; + + // internal signals + + wire adc_pn_oos_s; + wire adc_pn_err_s; + wire adc_dfmt_enable_s; + wire adc_dfmt_type_s; + wire adc_dfmt_se_s; + wire [ 3:0] adc_pnseq_sel_s; + + // instantiations + + axi_ad9680_pnmon i_pnmon ( + .adc_clk (adc_clk), + .adc_data (adc_data), + .adc_pn_oos (adc_pn_oos_s), + .adc_pn_err (adc_pn_err_s), + .adc_pnseq_sel (adc_pnseq_sel_s)); + + genvar n; + generate + for (n = 0; n < 4; n = n + 1) begin: g_ad_datafmt_1 + ad_datafmt #(.DATA_WIDTH(14)) i_ad_datafmt ( + .clk (adc_clk), + .valid (1'b1), + .data (adc_data[n*14+13:n*14]), + .valid_out (), + .data_out (adc_dfmt_data[n*16+15:n*16]), + .dfmt_enable (adc_dfmt_enable_s), + .dfmt_type (adc_dfmt_type_s), + .dfmt_se (adc_dfmt_se_s)); + end + endgenerate + + up_adc_channel #(.PCORE_ADC_CHID(CHID)) i_up_adc_channel ( + .adc_clk (adc_clk), + .adc_rst (adc_rst), + .adc_enable (adc_enable), + .adc_iqcor_enb (), + .adc_dcfilt_enb (), + .adc_dfmt_se (adc_dfmt_se_s), + .adc_dfmt_type (adc_dfmt_type_s), + .adc_dfmt_enable (adc_dfmt_enable_s), + .adc_dcfilt_offset (), + .adc_dcfilt_coeff (), + .adc_iqcor_coeff_1 (), + .adc_iqcor_coeff_2 (), + .adc_pnseq_sel (adc_pnseq_sel_s), + .adc_data_sel (), + .adc_pn_err (adc_pn_err_s), + .adc_pn_oos (adc_pn_oos_s), + .adc_or (adc_or), + .up_adc_pn_err (up_adc_pn_err), + .up_adc_pn_oos (up_adc_pn_oos), + .up_adc_or (up_adc_or), + .up_usr_datatype_be (), + .up_usr_datatype_signed (), + .up_usr_datatype_shift (), + .up_usr_datatype_total_bits (), + .up_usr_datatype_bits (), + .up_usr_decimation_m (), + .up_usr_decimation_n (), + .adc_usr_datatype_be (1'b0), + .adc_usr_datatype_signed (1'b1), + .adc_usr_datatype_shift (8'd0), + .adc_usr_datatype_total_bits (8'd16), + .adc_usr_datatype_bits (8'd16), + .adc_usr_decimation_m (16'd1), + .adc_usr_decimation_n (16'd1), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_sel (up_sel), + .up_wr (up_wr), + .up_addr (up_addr), + .up_wdata (up_wdata), + .up_rdata (up_rdata), + .up_ack (up_ack)); + +endmodule + +// *************************************************************************** +// *************************************************************************** + diff --git a/library/axi_ad9234/axi_ad9234_constr.xdc b/library/axi_ad9234/axi_ad9234_constr.xdc new file mode 100644 index 000000000..f22d7bdfa --- /dev/null +++ b/library/axi_ad9234/axi_ad9234_constr.xdc @@ -0,0 +1,6 @@ + +set_clock_groups -asynchronous -group [get_clocks -of_objects [get_ports adc_clk]] +set_clock_groups -asynchronous -group [get_clocks -of_objects [get_ports s_axi_aclk]] + + + diff --git a/library/axi_ad9234/axi_ad9234_if.v b/library/axi_ad9234/axi_ad9234_if.v new file mode 100644 index 000000000..c658b6b84 --- /dev/null +++ b/library/axi_ad9234/axi_ad9234_if.v @@ -0,0 +1,132 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2011(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** +// *************************************************************************** +// *************************************************************************** +// This is the LVDS/DDR interface + +`timescale 1ns/100ps + +module axi_ad9680_if ( + + // jesd interface + // rx_clk is (line-rate/40) + + rx_clk, + rx_data, + + // adc data output + + adc_clk, + adc_rst, + adc_data_a, + adc_data_b, + adc_or_a, + adc_or_b, + adc_status); + + // jesd interface + // rx_clk is (line-rate/40) + + input rx_clk; + input [127:0] rx_data; + + // adc data output + + output adc_clk; + input adc_rst; + output [55:0] adc_data_a; + output [55:0] adc_data_b; + output adc_or_a; + output adc_or_b; + output adc_status; + + // internal registers + + reg adc_status = 'd0; + + // internal signals + + wire [15:0] adc_data_a_s3_s; + wire [15:0] adc_data_a_s2_s; + wire [15:0] adc_data_a_s1_s; + wire [15:0] adc_data_a_s0_s; + wire [15:0] adc_data_b_s3_s; + wire [15:0] adc_data_b_s2_s; + wire [15:0] adc_data_b_s1_s; + wire [15:0] adc_data_b_s0_s; + + // adc clock is the reference clock + + assign adc_clk = rx_clk; + assign adc_or_a = 1'b0; + assign adc_or_b = 1'b0; + + // adc channels + + assign adc_data_a = { adc_data_a_s3_s[13:0], adc_data_a_s2_s[13:0], + adc_data_a_s1_s[13:0], adc_data_a_s0_s[13:0]}; + + assign adc_data_b = { adc_data_b_s3_s[13:0], adc_data_b_s2_s[13:0], + adc_data_b_s1_s[13:0], adc_data_b_s0_s[13:0]}; + + // data multiplex + + assign adc_data_a_s3_s = {rx_data[ 57: 56], rx_data[ 31: 24], rx_data[ 63: 58]}; + assign adc_data_a_s2_s = {rx_data[ 49: 48], rx_data[ 23: 16], rx_data[ 55: 50]}; + assign adc_data_a_s1_s = {rx_data[ 41: 40], rx_data[ 15: 8], rx_data[ 47: 42]}; + assign adc_data_a_s0_s = {rx_data[ 33: 32], rx_data[ 7: 0], rx_data[ 39: 34]}; + + assign adc_data_b_s3_s = {rx_data[121:120], rx_data[ 95: 88], rx_data[127:122]}; + assign adc_data_b_s2_s = {rx_data[113:112], rx_data[ 87: 80], rx_data[119:114]}; + assign adc_data_b_s1_s = {rx_data[105:104], rx_data[ 79: 72], rx_data[111:106]}; + assign adc_data_b_s0_s = {rx_data[ 97: 96], rx_data[ 71: 64], rx_data[103: 98]}; + + // status + + always @(posedge rx_clk) begin + if (adc_rst == 1'b1) begin + adc_status <= 1'b0; + end else begin + adc_status <= 1'b1; + end + end + +endmodule + +// *************************************************************************** +// *************************************************************************** + diff --git a/library/axi_ad9234/axi_ad9234_ip.tcl b/library/axi_ad9234/axi_ad9234_ip.tcl new file mode 100644 index 000000000..9426b317e --- /dev/null +++ b/library/axi_ad9234/axi_ad9234_ip.tcl @@ -0,0 +1,29 @@ +# ip + +source ../scripts/adi_env.tcl +source $ad_hdl_dir/library/scripts/adi_ip.tcl + +adi_ip_create axi_ad9680 +adi_ip_files axi_ad9680 [list \ + "$ad_hdl_dir/library/common/ad_rst.v" \ + "$ad_hdl_dir/library/common/ad_pnmon.v" \ + "$ad_hdl_dir/library/common/ad_datafmt.v" \ + "$ad_hdl_dir/library/common/up_axi.v" \ + "$ad_hdl_dir/library/common/up_xfer_cntrl.v" \ + "$ad_hdl_dir/library/common/up_xfer_status.v" \ + "$ad_hdl_dir/library/common/up_clock_mon.v" \ + "$ad_hdl_dir/library/common/up_drp_cntrl.v" \ + "$ad_hdl_dir/library/common/up_delay_cntrl.v" \ + "$ad_hdl_dir/library/common/up_adc_common.v" \ + "$ad_hdl_dir/library/common/up_adc_channel.v" \ + "axi_ad9680_pnmon.v" \ + "axi_ad9680_channel.v" \ + "axi_ad9680_if.v" \ + "axi_ad9680.v" ] + +adi_ip_properties axi_ad9680 +adi_ip_constraints axi_ad9680 [list \ + "axi_ad9680_constr.xdc" ] + +ipx::save_core [ipx::current_core] + diff --git a/library/axi_ad9234/axi_ad9234_pnmon.v b/library/axi_ad9234/axi_ad9234_pnmon.v new file mode 100644 index 000000000..4e64ca0fb --- /dev/null +++ b/library/axi_ad9234/axi_ad9234_pnmon.v @@ -0,0 +1,244 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2011(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** +// *************************************************************************** +// *************************************************************************** +// PN monitors + +`timescale 1ns/100ps + +module axi_ad9680_pnmon ( + + // adc interface + + adc_clk, + adc_data, + + // pn out of sync and error + + adc_pn_oos, + adc_pn_err, + + // processor interface PN9 (0x0), PN23 (0x1) + + adc_pnseq_sel); + + // adc interface + + input adc_clk; + input [55:0] adc_data; + + // pn out of sync and error + + output adc_pn_oos; + output adc_pn_err; + + // processor interface PN9 (0x0), PN23 (0x1) + + input [ 3:0] adc_pnseq_sel; + + // internal registers + + reg [55:0] adc_pn_data_in = 'd0; + reg [55:0] adc_pn_data_pn = 'd0; + + // internal signals + + wire [55:0] adc_pn_data_pn_s; + + // PN23 function + + function [55:0] pn23; + input [55:0] din; + reg [55:0] dout; + begin + dout[55] = din[22] ^ din[17]; + dout[54] = din[21] ^ din[16]; + dout[53] = din[20] ^ din[15]; + dout[52] = din[19] ^ din[14]; + dout[51] = din[18] ^ din[13]; + dout[50] = din[17] ^ din[12]; + dout[49] = din[16] ^ din[11]; + dout[48] = din[15] ^ din[10]; + dout[47] = din[14] ^ din[ 9]; + dout[46] = din[13] ^ din[ 8]; + dout[45] = din[12] ^ din[ 7]; + dout[44] = din[11] ^ din[ 6]; + dout[43] = din[10] ^ din[ 5]; + dout[42] = din[ 9] ^ din[ 4]; + dout[41] = din[ 8] ^ din[ 3]; + dout[40] = din[ 7] ^ din[ 2]; + dout[39] = din[ 6] ^ din[ 1]; + dout[38] = din[ 5] ^ din[ 0]; + dout[37] = din[ 4] ^ din[22] ^ din[17]; + dout[36] = din[ 3] ^ din[21] ^ din[16]; + dout[35] = din[ 2] ^ din[20] ^ din[15]; + dout[34] = din[ 1] ^ din[19] ^ din[14]; + dout[33] = din[ 0] ^ din[18] ^ din[13]; + dout[32] = din[22] ^ din[12]; + dout[31] = din[21] ^ din[11]; + dout[30] = din[20] ^ din[10]; + dout[29] = din[19] ^ din[ 9]; + dout[28] = din[18] ^ din[ 8]; + dout[27] = din[17] ^ din[ 7]; + dout[26] = din[16] ^ din[ 6]; + dout[25] = din[15] ^ din[ 5]; + dout[24] = din[14] ^ din[ 4]; + dout[23] = din[13] ^ din[ 3]; + dout[22] = din[12] ^ din[ 2]; + dout[21] = din[11] ^ din[ 1]; + dout[20] = din[10] ^ din[ 0]; + dout[19] = din[ 9] ^ din[22] ^ din[17]; + dout[18] = din[ 8] ^ din[21] ^ din[16]; + dout[17] = din[ 7] ^ din[20] ^ din[15]; + dout[16] = din[ 6] ^ din[19] ^ din[14]; + dout[15] = din[ 5] ^ din[18] ^ din[13]; + dout[14] = din[ 4] ^ din[17] ^ din[12]; + dout[13] = din[ 3] ^ din[16] ^ din[11]; + dout[12] = din[ 2] ^ din[15] ^ din[10]; + dout[11] = din[ 1] ^ din[14] ^ din[ 9]; + dout[10] = din[ 0] ^ din[13] ^ din[ 8]; + dout[ 9] = din[22] ^ din[12] ^ din[17] ^ din[ 7]; + dout[ 8] = din[21] ^ din[11] ^ din[16] ^ din[ 6]; + dout[ 7] = din[20] ^ din[10] ^ din[15] ^ din[ 5]; + dout[ 6] = din[19] ^ din[ 9] ^ din[14] ^ din[ 4]; + dout[ 5] = din[18] ^ din[ 8] ^ din[13] ^ din[ 3]; + dout[ 4] = din[17] ^ din[ 7] ^ din[12] ^ din[ 2]; + dout[ 3] = din[16] ^ din[ 6] ^ din[11] ^ din[ 1]; + dout[ 2] = din[15] ^ din[ 5] ^ din[10] ^ din[ 0]; + dout[ 1] = din[14] ^ din[ 4] ^ din[ 9] ^ din[22] ^ din[17]; + dout[ 0] = din[13] ^ din[ 3] ^ din[ 8] ^ din[21] ^ din[16]; + pn23 = dout; + end + endfunction + + // PN9 function + + function [55:0] pn9; + input [55:0] din; + reg [55:0] dout; + begin + dout[55] = din[ 8] ^ din[ 4]; + dout[54] = din[ 7] ^ din[ 3]; + dout[53] = din[ 6] ^ din[ 2]; + dout[52] = din[ 5] ^ din[ 1]; + dout[51] = din[ 4] ^ din[ 0]; + dout[50] = din[ 3] ^ din[ 8] ^ din[ 4]; + dout[49] = din[ 2] ^ din[ 7] ^ din[ 3]; + dout[48] = din[ 1] ^ din[ 6] ^ din[ 2]; + dout[47] = din[ 0] ^ din[ 5] ^ din[ 1]; + dout[46] = din[ 8] ^ din[ 0]; + dout[45] = din[ 7] ^ din[ 8] ^ din[ 4]; + dout[44] = din[ 6] ^ din[ 7] ^ din[ 3]; + dout[43] = din[ 5] ^ din[ 6] ^ din[ 2]; + dout[42] = din[ 4] ^ din[ 5] ^ din[ 1]; + dout[41] = din[ 3] ^ din[ 4] ^ din[ 0]; + dout[40] = din[ 2] ^ din[ 3] ^ din[ 8] ^ din[ 4]; + dout[39] = din[ 1] ^ din[ 2] ^ din[ 7] ^ din[ 3]; + dout[38] = din[ 0] ^ din[ 1] ^ din[ 6] ^ din[ 2]; + dout[37] = din[ 8] ^ din[ 0] ^ din[ 4] ^ din[ 5] ^ din[ 1]; + dout[36] = din[ 7] ^ din[ 8] ^ din[ 3] ^ din[ 0]; + dout[35] = din[ 6] ^ din[ 7] ^ din[ 2] ^ din[ 8] ^ din[ 4]; + dout[34] = din[ 5] ^ din[ 6] ^ din[ 1] ^ din[ 7] ^ din[ 3]; + dout[33] = din[ 4] ^ din[ 5] ^ din[ 0] ^ din[ 6] ^ din[ 2]; + dout[32] = din[ 3] ^ din[ 8] ^ din[ 5] ^ din[ 1]; + dout[31] = din[ 2] ^ din[ 4] ^ din[ 7] ^ din[ 0]; + dout[30] = din[ 1] ^ din[ 3] ^ din[ 6] ^ din[ 8] ^ din[ 4]; + dout[29] = din[ 0] ^ din[ 2] ^ din[ 5] ^ din[ 7] ^ din[ 3]; + dout[28] = din[ 8] ^ din[ 1] ^ din[ 6] ^ din[ 2]; + dout[27] = din[ 7] ^ din[ 0] ^ din[ 5] ^ din[ 1]; + dout[26] = din[ 6] ^ din[ 8] ^ din[ 0]; + dout[25] = din[ 5] ^ din[ 7] ^ din[ 8] ^ din[ 4]; + dout[24] = din[ 4] ^ din[ 6] ^ din[ 7] ^ din[ 3]; + dout[23] = din[ 3] ^ din[ 5] ^ din[ 6] ^ din[ 2]; + dout[22] = din[ 2] ^ din[ 4] ^ din[ 5] ^ din[ 1]; + dout[21] = din[ 1] ^ din[ 3] ^ din[ 4] ^ din[ 0]; + dout[20] = din[ 0] ^ din[ 2] ^ din[ 3] ^ din[ 8] ^ din[ 4]; + dout[19] = din[ 8] ^ din[ 1] ^ din[ 2] ^ din[ 4] ^ din[ 7] ^ din[ 3]; + dout[18] = din[ 7] ^ din[ 0] ^ din[ 1] ^ din[ 3] ^ din[ 6] ^ din[ 2]; + dout[17] = din[ 6] ^ din[ 8] ^ din[ 0] ^ din[ 2] ^ din[ 4] ^ din[ 5] ^ din[ 1]; + dout[16] = din[ 5] ^ din[ 7] ^ din[ 8] ^ din[ 1] ^ din[ 3] ^ din[ 0]; + dout[15] = din[ 6] ^ din[ 7] ^ din[ 0] ^ din[ 2] ^ din[ 8]; + dout[14] = din[ 5] ^ din[ 6] ^ din[ 8] ^ din[ 1] ^ din[ 4] ^ din[ 7]; + dout[13] = din[ 4] ^ din[ 5] ^ din[ 7] ^ din[ 0] ^ din[ 3] ^ din[ 6]; + dout[12] = din[ 3] ^ din[ 6] ^ din[ 8] ^ din[ 2] ^ din[ 5]; + dout[11] = din[ 2] ^ din[ 4] ^ din[ 5] ^ din[ 7] ^ din[ 1]; + dout[10] = din[ 1] ^ din[ 4] ^ din[ 3] ^ din[ 6] ^ din[ 0]; + dout[ 9] = din[ 0] ^ din[ 3] ^ din[ 2] ^ din[ 5] ^ din[ 8] ^ din[ 4]; + dout[ 8] = din[ 8] ^ din[ 2] ^ din[ 1] ^ din[ 7] ^ din[ 3]; + dout[ 7] = din[ 7] ^ din[ 1] ^ din[ 0] ^ din[ 6] ^ din[ 2]; + dout[ 6] = din[ 6] ^ din[ 0] ^ din[ 8] ^ din[ 4] ^ din[ 5] ^ din[ 1]; + dout[ 5] = din[ 5] ^ din[ 8] ^ din[ 7] ^ din[ 3] ^ din[ 0]; + dout[ 4] = din[ 7] ^ din[ 6] ^ din[ 2] ^ din[ 8]; + dout[ 3] = din[ 6] ^ din[ 5] ^ din[ 1] ^ din[ 7]; + dout[ 2] = din[ 4] ^ din[ 5] ^ din[ 0] ^ din[ 6]; + dout[ 1] = din[ 3] ^ din[ 8] ^ din[ 5]; + dout[ 0] = din[ 2] ^ din[ 4] ^ din[ 7]; + pn9 = dout; + end + endfunction + + // pn sequence select + + assign adc_pn_data_pn_s = (adc_pn_oos == 1'b1) ? adc_pn_data_in : adc_pn_data_pn; + + always @(posedge adc_clk) begin + adc_pn_data_in <= { ~adc_data[13], adc_data[12: 0], + ~adc_data[27], adc_data[26:14], + ~adc_data[41], adc_data[40:28], + ~adc_data[55], adc_data[54:42]}; + if (adc_pnseq_sel == 4'd0) begin + adc_pn_data_pn <= pn9(adc_pn_data_pn_s); + end else begin + adc_pn_data_pn <= pn23(adc_pn_data_pn_s); + end + end + + // pn oos & pn err + + ad_pnmon #(.DATA_WIDTH(56)) i_pnmon ( + .adc_clk (adc_clk), + .adc_valid_in (1'b1), + .adc_data_in (adc_pn_data_in), + .adc_data_pn (adc_pn_data_pn), + .adc_pn_oos (adc_pn_oos), + .adc_pn_err (adc_pn_err)); + +endmodule + +// *************************************************************************** +// *************************************************************************** +