cn0561_de10nano: Initial commit
sergiu arpadi
sarpadi
parent
4b704337d4
commit
cadb8e637d
|
|
@ -0,0 +1,176 @@
|
|||
# receive dma
|
||||
|
||||
add_instance axi_dmac_0 axi_dmac
|
||||
set_instance_parameter_value axi_dmac_0 {DMA_TYPE_SRC} {1}
|
||||
set_instance_parameter_value axi_dmac_0 {DMA_TYPE_DEST} {0}
|
||||
set_instance_parameter_value axi_dmac_0 {CYCLIC} {0}
|
||||
set_instance_parameter_value axi_dmac_0 {DMA_DATA_WIDTH_SRC} {128}
|
||||
set_instance_parameter_value axi_dmac_0 {DMA_DATA_WIDTH_DEST} {128}
|
||||
|
||||
# axi_spi_engine
|
||||
|
||||
add_instance axi_spi_engine_0 axi_spi_engine
|
||||
set_instance_parameter_value axi_spi_engine_0 {ASYNC_SPI_CLK} {1}
|
||||
set_instance_parameter_value axi_spi_engine_0 {DATA_WIDTH} {32}
|
||||
set_instance_parameter_value axi_spi_engine_0 {MM_IF_TYPE} {0}
|
||||
set_instance_parameter_value axi_spi_engine_0 {NUM_OF_SDI} {4}
|
||||
set_instance_parameter_value axi_spi_engine_0 {NUM_OFFLOAD} {1}
|
||||
|
||||
# spi_engine_execution
|
||||
|
||||
add_instance spi_engine_execution_0 spi_engine_execution
|
||||
set_instance_parameter_value spi_engine_execution_0 {DATA_WIDTH} {32}
|
||||
set_instance_parameter_value spi_engine_execution_0 {NUM_OF_SDI} {4}
|
||||
set_instance_parameter_value spi_engine_execution_0 {SDI_DELAY} {0}
|
||||
|
||||
# spi_engine_interconnect
|
||||
|
||||
add_instance spi_engine_interconnect_0 spi_engine_interconnect
|
||||
set_instance_parameter_value spi_engine_interconnect_0 {DATA_WIDTH} {32}
|
||||
set_instance_parameter_value spi_engine_interconnect_0 {NUM_OF_SDI} {4}
|
||||
|
||||
# spi_engine_offload
|
||||
|
||||
add_instance spi_engine_offload_0 spi_engine_offload
|
||||
set_instance_parameter_value spi_engine_offload_0 {ASYNC_TRIG} {1}
|
||||
set_instance_parameter_value spi_engine_offload_0 {ASYNC_SPI_CLK} {0}
|
||||
set_instance_parameter_value spi_engine_offload_0 {DATA_WIDTH} {32}
|
||||
set_instance_parameter_value spi_engine_offload_0 {NUM_OF_SDI} {4}
|
||||
|
||||
# axi pwm gen
|
||||
|
||||
add_instance odr_generator axi_pwm_gen
|
||||
set_instance_parameter_value odr_generator {N_PWMS} {2}
|
||||
set_instance_parameter_value odr_generator {PULSE_0_PERIOD} {85}
|
||||
set_instance_parameter_value odr_generator {PULSE_0_WIDTH} {1}
|
||||
set_instance_parameter_value odr_generator {PULSE_1_PERIOD} {85}
|
||||
set_instance_parameter_value odr_generator {PULSE_1_WIDTH} {13}
|
||||
set_instance_parameter_value odr_generator {PULSE_1_OFFSET} {3}
|
||||
|
||||
# spi_clk pll
|
||||
|
||||
add_instance spi_clk_pll altera_pll
|
||||
set_instance_parameter_value spi_clk_pll {gui_feedback_clock} {Global Clock}
|
||||
set_instance_parameter_value spi_clk_pll {gui_operation_mode} {direct}
|
||||
set_instance_parameter_value spi_clk_pll {gui_number_of_clocks} {1}
|
||||
set_instance_parameter_value spi_clk_pll {gui_output_clock_frequency0} {96}
|
||||
set_instance_parameter_value spi_clk_pll {gui_phase_shift0} {0}
|
||||
set_instance_parameter_value spi_clk_pll {gui_phase_shift1} {0}
|
||||
set_instance_parameter_value spi_clk_pll {gui_phase_shift_deg0} {0.0}
|
||||
set_instance_parameter_value spi_clk_pll {gui_phase_shift_deg1} {0.0}
|
||||
set_instance_parameter_value spi_clk_pll {gui_phout_division} {1}
|
||||
set_instance_parameter_value spi_clk_pll {gui_pll_auto_reset} {Off}
|
||||
set_instance_parameter_value spi_clk_pll {gui_pll_bandwidth_preset} {Auto}
|
||||
set_instance_parameter_value spi_clk_pll {gui_pll_mode} {Fractional-N PLL}
|
||||
set_instance_parameter_value spi_clk_pll {gui_ps_units0} {ps}
|
||||
set_instance_parameter_value spi_clk_pll {gui_refclk_switch} {0}
|
||||
set_instance_parameter_value spi_clk_pll {gui_reference_clock_frequency} {50.0}
|
||||
set_instance_parameter_value spi_clk_pll {gui_switchover_delay} {0}
|
||||
set_instance_parameter_value spi_clk_pll {gui_en_reconf} {1}
|
||||
|
||||
add_instance spi_clk_pll_reconfig altera_pll_reconfig
|
||||
set_instance_parameter_value spi_clk_pll_reconfig {ENABLE_BYTEENABLE} {0}
|
||||
set_instance_parameter_value spi_clk_pll_reconfig {ENABLE_MIF} {0}
|
||||
set_instance_parameter_value spi_clk_pll_reconfig {MIF_FILE_NAME} {}
|
||||
|
||||
add_connection spi_clk_pll.reconfig_from_pll spi_clk_pll_reconfig.reconfig_from_pll
|
||||
set_connection_parameter_value spi_clk_pll.reconfig_from_pll/spi_clk_pll_reconfig.reconfig_from_pll endPort {}
|
||||
set_connection_parameter_value spi_clk_pll.reconfig_from_pll/spi_clk_pll_reconfig.reconfig_from_pll endPortLSB {0}
|
||||
set_connection_parameter_value spi_clk_pll.reconfig_from_pll/spi_clk_pll_reconfig.reconfig_from_pll startPort {}
|
||||
set_connection_parameter_value spi_clk_pll.reconfig_from_pll/spi_clk_pll_reconfig.reconfig_from_pll startPortLSB {0}
|
||||
set_connection_parameter_value spi_clk_pll.reconfig_from_pll/spi_clk_pll_reconfig.reconfig_from_pll width {0}
|
||||
|
||||
add_connection spi_clk_pll.reconfig_to_pll spi_clk_pll_reconfig.reconfig_to_pll
|
||||
set_connection_parameter_value spi_clk_pll.reconfig_to_pll/spi_clk_pll_reconfig.reconfig_to_pll endPort {}
|
||||
set_connection_parameter_value spi_clk_pll.reconfig_to_pll/spi_clk_pll_reconfig.reconfig_to_pll endPortLSB {0}
|
||||
set_connection_parameter_value spi_clk_pll.reconfig_to_pll/spi_clk_pll_reconfig.reconfig_to_pll startPort {}
|
||||
set_connection_parameter_value spi_clk_pll.reconfig_to_pll/spi_clk_pll_reconfig.reconfig_to_pll startPortLSB {0}
|
||||
set_connection_parameter_value spi_clk_pll.reconfig_to_pll/spi_clk_pll_reconfig.reconfig_to_pll width {0}
|
||||
|
||||
# exported interface
|
||||
|
||||
add_interface cn0561_spi_sclk clock source
|
||||
add_interface cn0561_spi_cs conduit end
|
||||
add_interface cn0561_spi_sdi conduit end
|
||||
add_interface cn0561_spi_sdo conduit end
|
||||
add_interface ad4134_odr conduit end
|
||||
|
||||
set_interface_property cn0561_spi_cs EXPORT_OF spi_engine_execution_0.if_cs
|
||||
set_interface_property cn0561_spi_sclk EXPORT_OF spi_engine_execution_0.if_sclk
|
||||
set_interface_property cn0561_spi_sdi EXPORT_OF spi_engine_execution_0.if_sdi
|
||||
set_interface_property cn0561_spi_sdo EXPORT_OF spi_engine_execution_0.if_sdo
|
||||
set_interface_property ad4134_odr EXPORT_OF odr_generator.if_pwm_1
|
||||
|
||||
# clocks
|
||||
|
||||
add_connection sys_clk.clk spi_clk_pll.refclk
|
||||
add_connection sys_clk.clk spi_clk_pll_reconfig.mgmt_clk
|
||||
add_connection sys_clk.clk axi_spi_engine_0.s_axi_clock
|
||||
add_connection sys_clk.clk axi_dmac_0.s_axi_clock
|
||||
add_connection sys_clk.clk odr_generator.s_axi_clock
|
||||
|
||||
add_connection spi_clk_pll.outclk0 odr_generator.if_ext_clk
|
||||
add_connection spi_clk_pll.outclk0 spi_engine_execution_0.if_clk
|
||||
add_connection spi_clk_pll.outclk0 spi_engine_interconnect_0.if_clk
|
||||
add_connection spi_clk_pll.outclk0 axi_spi_engine_0.if_spi_clk
|
||||
add_connection spi_clk_pll.outclk0 spi_engine_offload_0.if_ctrl_clk
|
||||
add_connection spi_clk_pll.outclk0 spi_engine_offload_0.if_spi_clk
|
||||
add_connection spi_clk_pll.outclk0 axi_dmac_0.if_s_axis_aclk
|
||||
|
||||
add_connection sys_dma_clk.clk axi_dmac_0.m_dest_axi_clock
|
||||
|
||||
# resets
|
||||
|
||||
add_connection sys_clk.clk_reset spi_clk_pll.reset
|
||||
add_connection sys_clk.clk_reset spi_clk_pll_reconfig.mgmt_reset
|
||||
add_connection sys_clk.clk_reset axi_spi_engine_0.s_axi_reset
|
||||
add_connection sys_clk.clk_reset axi_dmac_0.s_axi_reset
|
||||
add_connection sys_clk.clk_reset odr_generator.s_axi_reset
|
||||
|
||||
add_connection axi_spi_engine_0.if_spi_resetn spi_engine_execution_0.if_resetn
|
||||
add_connection axi_spi_engine_0.if_spi_resetn spi_engine_interconnect_0.if_resetn
|
||||
add_connection axi_spi_engine_0.if_spi_resetn spi_engine_offload_0.if_spi_resetn
|
||||
|
||||
add_connection sys_dma_clk.clk_reset axi_dmac_0.m_dest_axi_reset
|
||||
|
||||
# interfaces
|
||||
|
||||
add_connection spi_engine_interconnect_0.m_cmd spi_engine_execution_0.cmd
|
||||
add_connection spi_engine_execution_0.sdi_data spi_engine_interconnect_0.m_sdi
|
||||
add_connection spi_engine_interconnect_0.m_sdo spi_engine_execution_0.sdo_data
|
||||
add_connection spi_engine_execution_0.sync spi_engine_interconnect_0.m_sync
|
||||
|
||||
add_connection axi_spi_engine_0.cmd spi_engine_interconnect_0.s0_cmd
|
||||
add_connection spi_engine_interconnect_0.s0_sdi axi_spi_engine_0.sdi_data
|
||||
add_connection axi_spi_engine_0.sdo_data spi_engine_interconnect_0.s0_sdo
|
||||
add_connection spi_engine_interconnect_0.s0_sync axi_spi_engine_0.sync
|
||||
|
||||
add_connection spi_engine_offload_0.cmd spi_engine_interconnect_0.s1_cmd
|
||||
add_connection spi_engine_interconnect_0.s1_sdi spi_engine_offload_0.sdi_data
|
||||
add_connection spi_engine_offload_0.sdo_data spi_engine_interconnect_0.s1_sdo
|
||||
add_connection spi_engine_interconnect_0.s1_sync spi_engine_offload_0.sync
|
||||
|
||||
add_connection spi_engine_offload_0.ctrl_cmd_wr axi_spi_engine_0.offload0_cmd
|
||||
add_connection spi_engine_offload_0.ctrl_sdo_wr axi_spi_engine_0.offload0_sdo
|
||||
add_connection spi_engine_offload_0.if_ctrl_enable axi_spi_engine_0.if_offload0_enable
|
||||
add_connection spi_engine_offload_0.if_ctrl_enabled axi_spi_engine_0.if_offload0_enabled
|
||||
add_connection spi_engine_offload_0.if_ctrl_mem_reset axi_spi_engine_0.if_offload0_mem_reset
|
||||
add_connection spi_engine_offload_0.status_sync axi_spi_engine_0.offload_sync
|
||||
|
||||
add_connection spi_engine_offload_0.if_trigger odr_generator.if_pwm_0
|
||||
add_connection spi_engine_offload_0.offload_sdi axi_dmac_0.s_axis
|
||||
|
||||
# cpu interconnects
|
||||
|
||||
ad_cpu_interconnect 0x00020000 axi_dmac_0.s_axi
|
||||
ad_cpu_interconnect 0x00030000 axi_spi_engine_0.s_axi
|
||||
ad_cpu_interconnect 0x00040000 odr_generator.s_axi
|
||||
|
||||
# dma interconnect
|
||||
|
||||
ad_dma_interconnect axi_dmac_0.m_dest_axi
|
||||
|
||||
#interrupts
|
||||
|
||||
ad_cpu_interrupt 4 axi_dmac_0.interrupt_sender
|
||||
ad_cpu_interrupt 5 axi_spi_engine_0.interrupt_sender
|
||||
|
|
@ -0,0 +1,24 @@
|
|||
####################################################################################
|
||||
## Copyright (c) 2018 - 2023 Analog Devices, Inc.
|
||||
### SPDX short identifier: BSD-1-Clause
|
||||
## Auto-generated, do not modify!
|
||||
####################################################################################
|
||||
|
||||
PROJECT_NAME := cn0561_de10nano
|
||||
|
||||
M_DEPS += ../common/cn0561_qsys.tcl
|
||||
M_DEPS += ../../scripts/adi_pd.tcl
|
||||
M_DEPS += ../../common/de10nano/de10nano_system_qsys.tcl
|
||||
M_DEPS += ../../common/de10nano/de10nano_system_assign.tcl
|
||||
|
||||
LIB_DEPS += axi_dmac
|
||||
LIB_DEPS += axi_hdmi_tx
|
||||
LIB_DEPS += axi_pwm_gen
|
||||
LIB_DEPS += axi_sysid
|
||||
LIB_DEPS += spi_engine/axi_spi_engine
|
||||
LIB_DEPS += spi_engine/spi_engine_execution
|
||||
LIB_DEPS += spi_engine/spi_engine_interconnect
|
||||
LIB_DEPS += spi_engine/spi_engine_offload
|
||||
LIB_DEPS += sysid_rom
|
||||
|
||||
include ../../scripts/project-intel.mk
|
||||
|
|
@ -0,0 +1,5 @@
|
|||
create_clock -period "20.000 ns" -name sys_clk [get_ports {sys_clk}]
|
||||
create_clock -period "16.666 ns" -name usb1_clk [get_ports {usb1_clk}]
|
||||
|
||||
derive_pll_clocks
|
||||
derive_clock_uncertainty
|
||||
|
|
@ -0,0 +1,61 @@
|
|||
set REQUIRED_QUARTUS_VERSION 21.1.0
|
||||
set QUARTUS_PRO_ISUSED 0
|
||||
|
||||
source ../../../scripts/adi_env.tcl
|
||||
source ../../scripts/adi_project_intel.tcl
|
||||
|
||||
adi_project cn0561_de10nano
|
||||
|
||||
source $ad_hdl_dir/projects/common/de10nano/de10nano_system_assign.tcl
|
||||
|
||||
#
|
||||
## down-grade Critical Warning related to asynchronous RAM in DMAC
|
||||
#
|
||||
## "mixed_port_feed_through_mode" parameter of RAM can not have value "old"
|
||||
set_global_assignment -name MESSAGE_DISABLE 15003
|
||||
|
||||
# files
|
||||
|
||||
# SPI interface for ad7134
|
||||
|
||||
set_location_assignment PIN_AH12 -to cn0561_spi_sclk ; ## Arduino_IO13
|
||||
set_location_assignment PIN_AH11 -to cn0561_spi_sdi ; ## Arduino_IO12
|
||||
set_location_assignment PIN_AG16 -to cn0561_spi_sdo ; ## Arduino_IO11
|
||||
set_location_assignment PIN_AF15 -to cn0561_spi_cs ; ## Arduino_IO10
|
||||
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to cn0561_spi_sclk
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to cn0561_spi_sdi
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to cn0561_spi_sdo
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to cn0561_spi_cs
|
||||
|
||||
# I2C
|
||||
|
||||
set_location_assignment PIN_AG11 -to i2c_scl ; ## Arduino_IO15
|
||||
set_location_assignment PIN_AH9 -to i2c_sda ; ## Arduino_IO14
|
||||
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to i2c_scl
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to i2c_sda
|
||||
|
||||
# reset and GPIO signals
|
||||
|
||||
set_location_assignment PIN_AF13 -to cn0561_pdn ; ## Arduino_IO1
|
||||
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to cn0561_pdn
|
||||
|
||||
# synchronization and timing
|
||||
|
||||
set_location_assignment PIN_AG9 -to cn0561_odr ; ## Arduino_IO3
|
||||
set_location_assignment PIN_AG10 -to cn0561_dclk ; ## Arduino_IO2
|
||||
set_location_assignment PIN_U14 -to cn0561_din[0] ; ## Arduino_IO4
|
||||
set_location_assignment PIN_U13 -to cn0561_din[1] ; ## Arduino_IO5
|
||||
set_location_assignment PIN_AG8 -to cn0561_din[2] ; ## Arduino_IO6
|
||||
set_location_assignment PIN_AH8 -to cn0561_din[3] ; ## Arduino_IO7
|
||||
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to cn0561_odr
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to cn0561_dclk
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to cn0561_din[0]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to cn0561_din[1]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to cn0561_din[2]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to cn0561_din[3]
|
||||
|
||||
execute_flow -compile
|
||||
|
|
@ -0,0 +1,11 @@
|
|||
source $ad_hdl_dir/projects/scripts/adi_pd.tcl
|
||||
source $ad_hdl_dir/projects/common/de10nano/de10nano_system_qsys.tcl
|
||||
source ../common/cn0561_qsys.tcl
|
||||
|
||||
#system ID
|
||||
set_instance_parameter_value axi_sysid_0 {ROM_ADDR_BITS} {9}
|
||||
set_instance_parameter_value rom_sys_0 {ROM_ADDR_BITS} {9}
|
||||
|
||||
set_instance_parameter_value rom_sys_0 {PATH_TO_FILE} "[pwd]/mem_init_sys.txt"
|
||||
|
||||
sysid_gen_sys_init_file;
|
||||
|
|
@ -0,0 +1,286 @@
|
|||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright 2022 - 2023 (c) Analog Devices, Inc. All rights reserved.
|
||||
//
|
||||
// In this HDL repository, there are many different and unique modules, consisting
|
||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||
// developed independently, and may be accompanied by separate and unique license
|
||||
// terms.
|
||||
//
|
||||
// The user should read each of these license terms, and understand the
|
||||
// freedoms and responsibilities that he or she has by using this source/core.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE.
|
||||
//
|
||||
// Redistribution and use of source or resulting binaries, with or without modification
|
||||
// of this file, are permitted under one of the following two license terms:
|
||||
//
|
||||
// 1. The GNU General Public License version 2 as published by the
|
||||
// Free Software Foundation, which can be found in the top level directory
|
||||
// of this repository (LICENSE_GPL2), and also online at:
|
||||
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
|
||||
//
|
||||
// OR
|
||||
//
|
||||
// 2. An ADI specific BSD license, which can be found in the top level directory
|
||||
// of this repository (LICENSE_ADIBSD), and also on-line at:
|
||||
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
|
||||
// This will allow to generate bit files and not release the source code,
|
||||
// as long as it attaches to an ADI device.
|
||||
//
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
module system_top (
|
||||
|
||||
// clock and resets
|
||||
|
||||
input sys_clk,
|
||||
|
||||
// hps-ddr
|
||||
|
||||
output [ 14:0] ddr3_a,
|
||||
output [ 2:0] ddr3_ba,
|
||||
output ddr3_reset_n,
|
||||
output ddr3_ck_p,
|
||||
output ddr3_ck_n,
|
||||
output ddr3_cke,
|
||||
output ddr3_cs_n,
|
||||
output ddr3_ras_n,
|
||||
output ddr3_cas_n,
|
||||
output ddr3_we_n,
|
||||
inout [ 31:0] ddr3_dq,
|
||||
inout [ 3:0] ddr3_dqs_p,
|
||||
inout [ 3:0] ddr3_dqs_n,
|
||||
output [ 3:0] ddr3_dm,
|
||||
output ddr3_odt,
|
||||
input ddr3_rzq,
|
||||
|
||||
// hps-ethernet
|
||||
|
||||
output eth1_tx_clk,
|
||||
output eth1_tx_ctl,
|
||||
output [ 3:0] eth1_tx_d,
|
||||
input eth1_rx_clk,
|
||||
input eth1_rx_ctl,
|
||||
input [ 3:0] eth1_rx_d,
|
||||
output eth1_mdc,
|
||||
inout eth1_mdio,
|
||||
|
||||
// hps-sdio
|
||||
|
||||
output sdio_clk,
|
||||
inout sdio_cmd,
|
||||
inout [ 3:0] sdio_d,
|
||||
|
||||
// hps-spim1
|
||||
|
||||
output spim1_ss0,
|
||||
output spim1_clk,
|
||||
output spim1_mosi,
|
||||
input spim1_miso,
|
||||
|
||||
// hps-usb
|
||||
|
||||
input usb1_clk,
|
||||
output usb1_stp,
|
||||
input usb1_dir,
|
||||
input usb1_nxt,
|
||||
inout [ 7:0] usb1_d,
|
||||
|
||||
// hps-uart
|
||||
|
||||
input uart0_rx,
|
||||
output uart0_tx,
|
||||
inout hps_conv_usb_n,
|
||||
|
||||
// board gpio
|
||||
|
||||
output [ 7:0] gpio_bd_o,
|
||||
input [ 5:0] gpio_bd_i,
|
||||
|
||||
// hdmi
|
||||
|
||||
output hdmi_out_clk,
|
||||
output hdmi_vsync,
|
||||
output hdmi_hsync,
|
||||
output hdmi_data_e,
|
||||
output [ 23:0] hdmi_data,
|
||||
|
||||
inout hdmi_i2c_scl,
|
||||
inout hdmi_i2c_sda,
|
||||
|
||||
inout i2c_sda,
|
||||
inout i2c_scl,
|
||||
|
||||
output ltc2308_cs,
|
||||
output ltc2308_sclk,
|
||||
output ltc2308_mosi,
|
||||
input ltc2308_miso,
|
||||
|
||||
// cn0561 SPI configuration interface
|
||||
|
||||
input cn0561_spi_sdi,
|
||||
output cn0561_spi_sdo,
|
||||
output cn0561_spi_sclk,
|
||||
output cn0561_spi_cs,
|
||||
|
||||
// cn0561 data interface
|
||||
|
||||
output cn0561_dclk,
|
||||
input [ 3:0] cn0561_din,
|
||||
output cn0561_odr,
|
||||
|
||||
output cn0561_pdn
|
||||
);
|
||||
|
||||
// internal signals
|
||||
|
||||
wire sys_resetn;
|
||||
wire [ 63:0] gpio_i;
|
||||
wire [ 63:0] gpio_o;
|
||||
|
||||
wire i2c1_scl;
|
||||
wire i2c1_scl_oe;
|
||||
wire i2c1_out_data;
|
||||
wire i2c1_sda_oe;
|
||||
|
||||
wire i2c0_out_data;
|
||||
wire i2c0_sda;
|
||||
wire i2c0_out_clk;
|
||||
wire i2c0_scl_in_clk;
|
||||
|
||||
// unused
|
||||
assign gpio_i[63:33] = gpio_o[63:33];
|
||||
assign gpio_i[31:14] = gpio_o[31:14];
|
||||
assign gpio_i[ 7: 0] = gpio_o[ 7: 0];
|
||||
|
||||
// GPIO outputs
|
||||
assign ltc2308_cs = gpio_o[41];
|
||||
assign cn0561_pdn = gpio_o[32];
|
||||
assign gpio_bd_o[7:0] = gpio_o[7:0];
|
||||
|
||||
// GPIO inputs
|
||||
assign gpio_i[13:8] = gpio_bd_i[5:0];
|
||||
|
||||
// IO Buffers for I2C
|
||||
|
||||
ALT_IOBUF scl_iobuf (
|
||||
.i(1'b0),
|
||||
.oe(i2c1_scl_oe),
|
||||
.o(i2c1_scl),
|
||||
.io(i2c_scl));
|
||||
|
||||
ALT_IOBUF sda_iobuf (
|
||||
.i(1'b0),
|
||||
.oe(i2c1_sda_oe),
|
||||
.o(i2c1_sda),
|
||||
.io(i2c_sda));
|
||||
|
||||
ALT_IOBUF scl_video_iobuf (
|
||||
.i(1'b0),
|
||||
.oe(i2c0_out_clk),
|
||||
.o(i2c0_scl_in_clk),
|
||||
.io(hdmi_i2c_scl));
|
||||
|
||||
ALT_IOBUF sda_video_iobuf (
|
||||
.i(1'b0),
|
||||
.oe(i2c0_out_data),
|
||||
.o(i2c0_sda),
|
||||
.io(hdmi_i2c_sda));
|
||||
|
||||
system_bd i_system_bd (
|
||||
.sys_clk_clk (sys_clk),
|
||||
.sys_hps_h2f_reset_reset_n (sys_resetn),
|
||||
.sys_hps_memory_mem_a (ddr3_a),
|
||||
.sys_hps_memory_mem_ba (ddr3_ba),
|
||||
.sys_hps_memory_mem_ck (ddr3_ck_p),
|
||||
.sys_hps_memory_mem_ck_n (ddr3_ck_n),
|
||||
.sys_hps_memory_mem_cke (ddr3_cke),
|
||||
.sys_hps_memory_mem_cs_n (ddr3_cs_n),
|
||||
.sys_hps_memory_mem_ras_n (ddr3_ras_n),
|
||||
.sys_hps_memory_mem_cas_n (ddr3_cas_n),
|
||||
.sys_hps_memory_mem_we_n (ddr3_we_n),
|
||||
.sys_hps_memory_mem_reset_n (ddr3_reset_n),
|
||||
.sys_hps_memory_mem_dq (ddr3_dq),
|
||||
.sys_hps_memory_mem_dqs (ddr3_dqs_p),
|
||||
.sys_hps_memory_mem_dqs_n (ddr3_dqs_n),
|
||||
.sys_hps_memory_mem_odt (ddr3_odt),
|
||||
.sys_hps_memory_mem_dm (ddr3_dm),
|
||||
.sys_hps_memory_oct_rzqin (ddr3_rzq),
|
||||
.sys_rst_reset_n (sys_resetn),
|
||||
.sys_hps_i2c0_out_data (i2c0_out_data),
|
||||
.sys_hps_i2c0_sda (i2c0_sda),
|
||||
.sys_hps_i2c0_clk_clk (i2c0_out_clk),
|
||||
.sys_hps_i2c0_scl_in_clk (i2c0_scl_in_clk),
|
||||
.sys_hps_hps_io_hps_io_emac1_inst_TX_CLK (eth1_tx_clk),
|
||||
.sys_hps_hps_io_hps_io_emac1_inst_TXD0 (eth1_tx_d[0]),
|
||||
.sys_hps_hps_io_hps_io_emac1_inst_TXD1 (eth1_tx_d[1]),
|
||||
.sys_hps_hps_io_hps_io_emac1_inst_TXD2 (eth1_tx_d[2]),
|
||||
.sys_hps_hps_io_hps_io_emac1_inst_TXD3 (eth1_tx_d[3]),
|
||||
.sys_hps_hps_io_hps_io_emac1_inst_RXD0 (eth1_rx_d[0]),
|
||||
.sys_hps_hps_io_hps_io_emac1_inst_MDIO (eth1_mdio),
|
||||
.sys_hps_hps_io_hps_io_emac1_inst_MDC (eth1_mdc),
|
||||
.sys_hps_hps_io_hps_io_emac1_inst_RX_CTL (eth1_rx_ctl),
|
||||
.sys_hps_hps_io_hps_io_emac1_inst_TX_CTL (eth1_tx_ctl),
|
||||
.sys_hps_hps_io_hps_io_emac1_inst_RX_CLK (eth1_rx_clk),
|
||||
.sys_hps_hps_io_hps_io_emac1_inst_RXD1 (eth1_rx_d[1]),
|
||||
.sys_hps_hps_io_hps_io_emac1_inst_RXD2 (eth1_rx_d[2]),
|
||||
.sys_hps_hps_io_hps_io_emac1_inst_RXD3 (eth1_rx_d[3]),
|
||||
.sys_hps_hps_io_hps_io_sdio_inst_CMD (sdio_cmd),
|
||||
.sys_hps_hps_io_hps_io_sdio_inst_D0 (sdio_d[0]),
|
||||
.sys_hps_hps_io_hps_io_sdio_inst_D1 (sdio_d[1]),
|
||||
.sys_hps_hps_io_hps_io_sdio_inst_CLK (sdio_clk),
|
||||
.sys_hps_hps_io_hps_io_sdio_inst_D2 (sdio_d[2]),
|
||||
.sys_hps_hps_io_hps_io_sdio_inst_D3 (sdio_d[3]),
|
||||
.sys_hps_hps_io_hps_io_usb1_inst_D0 (usb1_d[0]),
|
||||
.sys_hps_hps_io_hps_io_usb1_inst_D1 (usb1_d[1]),
|
||||
.sys_hps_hps_io_hps_io_usb1_inst_D2 (usb1_d[2]),
|
||||
.sys_hps_hps_io_hps_io_usb1_inst_D3 (usb1_d[3]),
|
||||
.sys_hps_hps_io_hps_io_usb1_inst_D4 (usb1_d[4]),
|
||||
.sys_hps_hps_io_hps_io_usb1_inst_D5 (usb1_d[5]),
|
||||
.sys_hps_hps_io_hps_io_usb1_inst_D6 (usb1_d[6]),
|
||||
.sys_hps_hps_io_hps_io_usb1_inst_D7 (usb1_d[7]),
|
||||
.sys_hps_hps_io_hps_io_usb1_inst_CLK (usb1_clk),
|
||||
.sys_hps_hps_io_hps_io_usb1_inst_STP (usb1_stp),
|
||||
.sys_hps_hps_io_hps_io_usb1_inst_DIR (usb1_dir),
|
||||
.sys_hps_hps_io_hps_io_usb1_inst_NXT (usb1_nxt),
|
||||
.sys_hps_hps_io_hps_io_uart0_inst_RX (uart0_rx),
|
||||
.sys_hps_hps_io_hps_io_uart0_inst_TX (uart0_tx),
|
||||
.sys_hps_hps_io_hps_io_spim1_inst_CLK (spim1_clk),
|
||||
.sys_hps_hps_io_hps_io_spim1_inst_MOSI (spim1_mosi),
|
||||
.sys_hps_hps_io_hps_io_spim1_inst_MISO (spim1_miso),
|
||||
.sys_hps_hps_io_hps_io_spim1_inst_SS0 (spim1_ss0),
|
||||
.sys_hps_hps_io_hps_io_gpio_inst_GPIO09 (hps_conv_usb_n),
|
||||
.sys_hps_i2c1_sda (i2c1_sda),
|
||||
.sys_hps_i2c1_out_data (i2c1_sda_oe),
|
||||
.sys_hps_i2c1_clk_clk (i2c1_scl_oe),
|
||||
.sys_hps_i2c1_scl_in_clk (i2c1_scl),
|
||||
.sys_gpio_bd_in_port (gpio_i[31:0]),
|
||||
.sys_gpio_bd_out_port (gpio_o[31:0]),
|
||||
.sys_gpio_in_export (gpio_i[63:32]),
|
||||
.sys_gpio_out_export (gpio_o[63:32]),
|
||||
.cn0561_spi_sdo_sdo (),
|
||||
.cn0561_spi_sdi_sdi (cn0561_din),
|
||||
.cn0561_spi_cs_cs (),
|
||||
.cn0561_spi_sclk_clk (cn0561_dclk),
|
||||
.ad4134_odr_if_pwm(cn0561_odr),
|
||||
.sys_spi_MISO (cn0561_spi_sdi),
|
||||
.sys_spi_MOSI (cn0561_spi_sdo),
|
||||
.sys_spi_SCLK (cn0561_spi_sclk),
|
||||
.sys_spi_SS_n (cn0561_spi_cs),
|
||||
.ltc2308_spi_MISO (ltc2308_miso),
|
||||
.ltc2308_spi_MOSI (ltc2308_mosi),
|
||||
.ltc2308_spi_SCLK (ltc2308_sclk),
|
||||
.ltc2308_spi_SS_n (),
|
||||
.axi_hdmi_tx_0_hdmi_if_h_clk (hdmi_out_clk),
|
||||
.axi_hdmi_tx_0_hdmi_if_h24_hsync (hdmi_hsync),
|
||||
.axi_hdmi_tx_0_hdmi_if_h24_vsync (hdmi_vsync),
|
||||
.axi_hdmi_tx_0_hdmi_if_h24_data_e (hdmi_data_e),
|
||||
.axi_hdmi_tx_0_hdmi_if_h24_data (hdmi_data));
|
||||
|
||||
endmodule
|
||||
Loading…
Reference in New Issue