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a5gt: updates to match a5gt

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Rejeesh Kutty 2014-08-25 10:46:59 -04:00
parent 76ffb939e5
commit cb29b83b05
4 changed files with 288 additions and 255 deletions
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19
projects/common/a5gt/a5gt_system_assign.tcl
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@ -1,4 +1,13 @@
# device settings
set_global_assignment -name FAMILY "Arria V"
set_global_assignment -name DEVICE 5AGTFD7K3F40I3
set_global_assignment -name TOP_LEVEL_ENTITY system_top
set_global_assignment -name SDC_FILE system_constr.sdc
set_global_assignment -name QSYS_FILE system_bd.qsys
set_global_assignment -name VERILOG_FILE system_top.v
# clocks and resets
set_location_assignment PIN_C34 -to sys_clk
@ -784,4 +793,14 @@ set_instance_assignment -name IO_STANDARD "2.5 V" -to dip_switches[5]
set_instance_assignment -name IO_STANDARD "2.5 V" -to dip_switches[6]
set_instance_assignment -name IO_STANDARD "2.5 V" -to dip_switches[7]
# globals
set_global_assignment -name SYNCHRONIZER_IDENTIFICATION AUTO
set_global_assignment -name ENABLE_ADVANCED_IO_TIMING ON
set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER ON
set_global_assignment -name TIMEQUEST_DO_REPORT_TIMING ON
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL ON
set_global_assignment -name TIMEQUEST_REPORT_SCRIPT system_timing.tcl
set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION OFF

387
projects/fmcjesdadc1/a5gt/system_bd.qsys
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File diff suppressed because one or more lines are too long

20
projects/fmcjesdadc1/a5gt/system_project.tcl
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@ -4,17 +4,11 @@ load_package flow
source ../../scripts/adi_env.tcl
project_new fmcjesdadc1_a5gt -overwrite
set_global_assignment -name FAMILY "Arria V"
set_global_assignment -name DEVICE 5AGTFD7K3F40I3
set_global_assignment -name TOP_LEVEL_ENTITY system_top
set_global_assignment -name SDC_FILE system_constr.sdc
set_global_assignment -name QSYS_FILE system_bd.qsys
source $ad_hdl_dir/projects/common/a5gt/a5gt_system_assign.tcl
set_global_assignment -name VERILOG_FILE $ad_hdl_dir/library/common/altera/ad_jesd_align.v
set_global_assignment -name VERILOG_FILE $ad_hdl_dir/library/common/altera/ad_xcvr_rx_rst.v
set_global_assignment -name VERILOG_FILE ../common/fmcjesdadc1_spi.v
set_global_assignment -name VERILOG_FILE system_top.v
source $ad_hdl_dir/projects/common/a5gt/a5gt_system_assign.tcl
# reference clock
@ -61,15 +55,5 @@ set_instance_assignment -name IO_STANDARD "2.5 V" -to spi_csn
set_instance_assignment -name IO_STANDARD "2.5 V" -to spi_clk
set_instance_assignment -name IO_STANDARD "2.5 V" -to spi_sdio
# globals
set_global_assignment -name SYNCHRONIZER_IDENTIFICATION AUTO
set_global_assignment -name ENABLE_ADVANCED_IO_TIMING ON
set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER ON
set_global_assignment -name TIMEQUEST_DO_REPORT_TIMING ON
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL ON
set_global_assignment -name TIMEQUEST_REPORT_SCRIPT system_timing.tcl
set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION OFF
execute_flow -compile

117
projects/fmcjesdadc1/a5gt/system_top.v
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@ -159,6 +159,10 @@ module system_top (
reg rx_sysref_m2 = 'd0;
reg rx_sysref_m3 = 'd0;
reg rx_sysref = 'd0;
reg dma0_wr = 'd0;
reg [ 63:0] dma0_wdata = 'd0;
reg dma1_wr = 'd0;
reg [ 63:0] dma1_wdata = 'd0;
// internal clocks and resets
@ -176,22 +180,18 @@ module system_top (
wire eth_tx_reset_s;
wire eth_tx_mode_1g_s;
wire eth_tx_mode_10m_100m_n_s;
wire spi_csn_s;
wire spi_clk_s;
wire spi_mosi_s;
wire spi_miso_s;
wire [ 63:0] adc0_ddata_s;
wire adc0_dsync_s;
wire spi_mosi;
wire spi_miso;
wire adc0_enable_a_s;
wire [ 31:0] adc0_data_a_s;
wire adc0_enable_b_s;
wire [ 31:0] adc0_data_b_s;
wire adc0_dovf_s;
wire adc0_dwr_s;
wire adc0_mon_valid_s;
wire [ 55:0] adc0_mon_data_s;
wire [ 63:0] adc1_ddata_s;
wire adc1_dsync_s;
wire adc1_enable_a_s;
wire [ 31:0] adc1_data_a_s;
wire adc1_enable_b_s;
wire [ 31:0] adc1_data_b_s;
wire adc1_dovf_s;
wire adc1_dwr_s;
wire adc1_mon_valid_s;
wire [ 55:0] adc1_mon_data_s;
wire [ 3:0] rx_ip_sof_s;
wire [127:0] rx_ip_data_s;
wire [127:0] rx_data_s;
@ -235,9 +235,22 @@ module system_top (
rx_sysref <= rx_sysref_m2 & ~rx_sysref_m3;
end
always @(posedge rx_clk) begin
dma0_wr <= adc0_enable_a_s & adc0_enable_b_s;
dma0_wdata <= { adc0_data_b_s[31:16],
adc0_data_a_s[31:16],
adc0_data_b_s[15: 0],
adc0_data_a_s[15: 0]};
dma1_wr <= adc1_enable_a_s & adc1_enable_b_s;
dma1_wdata <= { adc1_data_b_s[31:16],
adc1_data_a_s[31:16],
adc1_data_b_s[15: 0],
adc1_data_a_s[15: 0]};
end
sld_signaltap #(
.sld_advanced_trigger_entity ("basic,1,"),
.sld_data_bits (114),
.sld_data_bits (130),
.sld_data_bit_cntr_bits (8),
.sld_enable_advanced_trigger (0),
.sld_mem_address_bits (10),
@ -255,7 +268,12 @@ module system_top (
.sld_trigger_level_pipeline (1))
i_signaltap (
.acq_clk (rx_clk),
.acq_data_in ({rx_sysref, rx_sync, adc1_mon_data_s, adc0_mon_data_s}),
.acq_data_in ({ rx_sysref,
rx_sync,
adc1_data_b_s,
adc1_data_a_s,
adc0_data_b_s,
adc0_data_a_s}),
.acq_trigger_in ({rx_sysref, rx_sync}));
genvar n;
@ -290,14 +308,11 @@ module system_top (
.rx_rst_state (rx_rst_state_s));
fmcjesdadc1_spi i_fmcjesdadc1_spi (
.sys_clk (sys_clk),
.spi4_csn (spi_csn_s),
.spi4_clk (spi_clk_s),
.spi4_mosi (spi_mosi_s),
.spi4_miso (spi_miso_s),
.spi3_csn (spi_csn),
.spi3_clk (spi_clk),
.spi3_sdio (spi_sdio));
.spi_csn (spi_csn),
.spi_clk (spi_clk),
.spi_mosi (spi_mosi),
.spi_miso (spi_miso),
.spi_sdio (spi_sdio));
system_bd i_system_bd (
.sys_clk_clk (sys_clk),
@ -305,7 +320,6 @@ module system_top (
.sys_125m_clk_clk (sys_125m_clk),
.sys_25m_clk_clk (sys_25m_clk),
.sys_2m5_clk_clk (sys_2m5_clk),
.sys_pll_locked_export (sys_pll_locked_s),
.sys_ddr3_phy_mem_a (ddr3_a),
.sys_ddr3_phy_mem_ba (ddr3_ba),
.sys_ddr3_phy_mem_ck (ddr3_clk_p),
@ -338,40 +352,42 @@ module system_top (
.sys_ethernet_mdio_mdio_oen (eth_mdio_t),
.sys_gpio_in_port ({rx_xcvr_status_s, 5'd0, push_buttons, dip_switches}),
.sys_gpio_out_port ({14'd0, rx_sw_rstn_s, rx_sysref_s, led_grn, led_red}),
.sys_spi_MISO (spi_miso_s),
.sys_spi_MOSI (spi_mosi_s),
.sys_spi_SCLK (spi_clk_s),
.sys_spi_SS_n (spi_csn_s),
.sys_spi_MISO (spi_miso),
.sys_spi_MOSI (spi_mosi),
.sys_spi_SCLK (spi_clk),
.sys_spi_SS_n (spi_csn),
.axi_ad9250_0_xcvr_clk_clk (rx_clk),
.axi_ad9250_0_xcvr_data_data (rx_data_s[63:0]),
.axi_ad9250_0_adc_clock_clk (adc0_clk),
.axi_ad9250_0_adc_dma_if_ddata (adc0_ddata_s),
.axi_ad9250_0_adc_dma_if_dsync (adc0_dsync_s),
.axi_ad9250_0_adc_dma_if_dovf (adc0_dovf_s),
.axi_ad9250_0_adc_dma_if_dunf (1'b0),
.axi_ad9250_0_adc_dma_if_dwr (adc0_dwr_s),
.axi_ad9250_0_adc_mon_if_valid (adc0_mon_valid_s),
.axi_ad9250_0_adc_mon_if_data (adc0_mon_data_s),
.axi_ad9250_0_adc_dma_if_adc_valid_a (),
.axi_ad9250_0_adc_dma_if_adc_enable_a (adc0_enable_a_s),
.axi_ad9250_0_adc_dma_if_adc_data_a (adc0_data_a_s),
.axi_ad9250_0_adc_dma_if_adc_valid_b (),
.axi_ad9250_0_adc_dma_if_adc_enable_b (adc0_enable_b_s),
.axi_ad9250_0_adc_dma_if_adc_data_b (adc0_data_b_s),
.axi_ad9250_0_adc_dma_if_adc_dovf (adc0_dovf_s),
.axi_ad9250_0_adc_dma_if_adc_dunf (1'b0),
.axi_dmac_0_fifo_wr_clock_clk (adc0_clk),
.axi_dmac_0_fifo_wr_if_ovf (adc0_dovf_s),
.axi_dmac_0_fifo_wr_if_wren (adc0_dwr_s),
.axi_dmac_0_fifo_wr_if_data (adc0_ddata_s),
.axi_dmac_0_fifo_wr_if_sync (adc0_dsync_s),
.axi_dmac_0_fifo_wr_if_wren (dma0_wr),
.axi_dmac_0_fifo_wr_if_data (dma0_wdata),
.axi_dmac_0_fifo_wr_if_sync (1'b1),
.axi_ad9250_1_xcvr_clk_clk (rx_clk),
.axi_ad9250_1_xcvr_data_data (rx_data_s[127:64]),
.axi_ad9250_1_adc_clock_clk (adc1_clk),
.axi_ad9250_1_adc_dma_if_ddata (adc1_ddata_s),
.axi_ad9250_1_adc_dma_if_dsync (adc1_dsync_s),
.axi_ad9250_1_adc_dma_if_dovf (adc1_dovf_s),
.axi_ad9250_1_adc_dma_if_dunf (1'b0),
.axi_ad9250_1_adc_dma_if_dwr (adc1_dwr_s),
.axi_ad9250_1_adc_mon_if_valid (adc1_mon_valid_s),
.axi_ad9250_1_adc_mon_if_data (adc1_mon_data_s),
.axi_ad9250_1_adc_dma_if_adc_valid_a (),
.axi_ad9250_1_adc_dma_if_adc_enable_a (adc1_enable_a_s),
.axi_ad9250_1_adc_dma_if_adc_data_a (adc1_data_a_s),
.axi_ad9250_1_adc_dma_if_adc_valid_b (),
.axi_ad9250_1_adc_dma_if_adc_enable_b (adc1_enable_b_s),
.axi_ad9250_1_adc_dma_if_adc_data_b (adc1_data_b_s),
.axi_ad9250_1_adc_dma_if_adc_dovf (adc1_dovf_s),
.axi_ad9250_1_adc_dma_if_adc_dunf (1'b0),
.axi_dmac_1_fifo_wr_clock_clk (adc1_clk),
.axi_dmac_1_fifo_wr_if_ovf (adc1_dovf_s),
.axi_dmac_1_fifo_wr_if_wren (adc1_dwr_s),
.axi_dmac_1_fifo_wr_if_data (adc1_ddata_s),
.axi_dmac_1_fifo_wr_if_sync (adc1_dsync_s),
.axi_dmac_1_fifo_wr_if_wren (dma1_wr),
.axi_dmac_1_fifo_wr_if_data (dma1_wdata),
.axi_dmac_1_fifo_wr_if_sync (1'b1),
.sys_jesd204b_s1_rx_link_data (rx_ip_data_s),
.sys_jesd204b_s1_rx_link_valid (),
.sys_jesd204b_s1_rx_link_ready (1'b1),
@ -388,7 +404,8 @@ module system_top (
.sys_jesd204b_s1_rx_cal_busy_export (rx_cal_busy_s),
.sys_jesd204b_s1_ref_clk_clk (ref_clk),
.sys_jesd204b_s1_rx_clk_clk (rx_clk),
.sys_jesd204b_s1_pll_locked_export (rx_pll_locked_s));
.sys_jesd204b_s1_pll_locked_export (rx_pll_locked_s),
.sys_pll_locked_export (sys_pll_locked_s));
endmodule