diff --git a/library/xilinx/util_adxcvr/util_adxcvr.v b/library/xilinx/util_adxcvr/util_adxcvr.v index fba232735..a65d8a89f 100644 --- a/library/xilinx/util_adxcvr/util_adxcvr.v +++ b/library/xilinx/util_adxcvr/util_adxcvr.v @@ -42,6 +42,10 @@ module util_adxcvr #( parameter integer XCVR_TYPE = 0, + parameter LINK_MODE = 1, // 2 - 64B/66B; 1 - 8B/10B + /* Only 4 is supported at the moment for 8b/10b and 8 for 64b */ + parameter DATA_PATH_WIDTH = LINK_MODE == 2 ? 8 : 4, + // qpll-configuration parameter integer QPLL_REFCLK_DIV = 1, @@ -101,14 +105,18 @@ module util_adxcvr #( parameter [ 5:0] RXCDR_CFG3_GEN2 = 6'b011010, parameter [15:0] RXCDR_CFG3_GEN3 = 16'b0000000000010010, parameter [15:0] RXCDR_CFG3_GEN4 = 16'b0000000000100100, + parameter [15:0] RXDFE_KH_CFG2 = 16'h0200, + parameter [15:0] RXDFE_KH_CFG3 = 16'h4101, parameter [ 1:0] RX_WIDEMODE_CDR = 2'b00, parameter [ 0:0] RX_XMODE_SEL = 1'b1, parameter integer TXDRV_FREQBAND = 0, + parameter [15:0] TXFE_CFG0 = 16'b0000001111000010, parameter [15:0] TXFE_CFG1 = 16'b0110110000000000, parameter [15:0] TXFE_CFG2 = 16'b0110110000000000, parameter [15:0] TXFE_CFG3 = 16'b0110110000000000, parameter [15:0] TXPI_CFG0 = 16'b0000001100000000, parameter [15:0] TXPI_CFG1 = 16'b0001000000000000, + parameter integer TXSWBST_EN = 0, parameter integer RX_LANE_INVERT = 0) ( input up_rstn, @@ -119,22 +127,25 @@ module util_adxcvr #( input cpll_ref_clk_0, input up_cpll_rst_0, - input rx_0_p, - input rx_0_n, - output rx_out_clk_0, - input rx_clk_0, - output [ 3:0] rx_charisk_0, - output [ 3:0] rx_disperr_0, - output [ 3:0] rx_notintable_0, - output [31:0] rx_data_0, - input rx_calign_0, + input rx_0_p, + input rx_0_n, + output rx_out_clk_0, + input rx_clk_0, + output [DATA_PATH_WIDTH-1:0] rx_charisk_0, + output [DATA_PATH_WIDTH-1:0] rx_disperr_0, + output [DATA_PATH_WIDTH-1:0] rx_notintable_0, + output [DATA_PATH_WIDTH*8-1:0] rx_data_0, + input rx_calign_0, + output [1:0] rx_header_0, + output rx_block_sync_0, - output tx_0_p, - output tx_0_n, - output tx_out_clk_0, - input tx_clk_0, - input [ 3:0] tx_charisk_0, - input [31:0] tx_data_0, + output tx_0_p, + output tx_0_n, + output tx_out_clk_0, + input tx_clk_0, + input [DATA_PATH_WIDTH-1:0] tx_charisk_0, + input [DATA_PATH_WIDTH*8-1:0] tx_data_0, + input [1:0] tx_header_0, input up_cm_enb_0, input [11:0] up_cm_addr_0, @@ -190,22 +201,25 @@ module util_adxcvr #( input cpll_ref_clk_1, input up_cpll_rst_1, - input rx_1_p, - input rx_1_n, - output rx_out_clk_1, - input rx_clk_1, - output [ 3:0] rx_charisk_1, - output [ 3:0] rx_disperr_1, - output [ 3:0] rx_notintable_1, - output [31:0] rx_data_1, - input rx_calign_1, + input rx_1_p, + input rx_1_n, + output rx_out_clk_1, + input rx_clk_1, + output [DATA_PATH_WIDTH-1:0] rx_charisk_1, + output [DATA_PATH_WIDTH-1:0] rx_disperr_1, + output [DATA_PATH_WIDTH-1:0] rx_notintable_1, + output [DATA_PATH_WIDTH*8-1:0] rx_data_1, + input rx_calign_1, + output [1:0] rx_header_1, + output rx_block_sync_1, - output tx_1_p, - output tx_1_n, - output tx_out_clk_1, - input tx_clk_1, - input [ 3:0] tx_charisk_1, - input [31:0] tx_data_1, + output tx_1_p, + output tx_1_n, + output tx_out_clk_1, + input tx_clk_1, + input [DATA_PATH_WIDTH-1:0] tx_charisk_1, + input [DATA_PATH_WIDTH*8-1:0] tx_data_1, + input [1:0] tx_header_1, input up_es_enb_1, input [11:0] up_es_addr_1, @@ -255,22 +269,25 @@ module util_adxcvr #( input cpll_ref_clk_2, input up_cpll_rst_2, - input rx_2_p, - input rx_2_n, - output rx_out_clk_2, - input rx_clk_2, - output [ 3:0] rx_charisk_2, - output [ 3:0] rx_disperr_2, - output [ 3:0] rx_notintable_2, - output [31:0] rx_data_2, - input rx_calign_2, + input rx_2_p, + input rx_2_n, + output rx_out_clk_2, + input rx_clk_2, + output [DATA_PATH_WIDTH-1:0] rx_charisk_2, + output [DATA_PATH_WIDTH-1:0] rx_disperr_2, + output [DATA_PATH_WIDTH-1:0] rx_notintable_2, + output [DATA_PATH_WIDTH*8-1:0] rx_data_2, + input rx_calign_2, + output [1:0] rx_header_2, + output rx_block_sync_2, - output tx_2_p, - output tx_2_n, - output tx_out_clk_2, - input tx_clk_2, - input [ 3:0] tx_charisk_2, - input [31:0] tx_data_2, + output tx_2_p, + output tx_2_n, + output tx_out_clk_2, + input tx_clk_2, + input [DATA_PATH_WIDTH-1:0] tx_charisk_2, + input [DATA_PATH_WIDTH*8-1:0] tx_data_2, + input [1:0] tx_header_2, input up_es_enb_2, input [11:0] up_es_addr_2, @@ -320,22 +337,25 @@ module util_adxcvr #( input cpll_ref_clk_3, input up_cpll_rst_3, - input rx_3_p, - input rx_3_n, - output rx_out_clk_3, - input rx_clk_3, - output [ 3:0] rx_charisk_3, - output [ 3:0] rx_disperr_3, - output [ 3:0] rx_notintable_3, - output [31:0] rx_data_3, - input rx_calign_3, + input rx_3_p, + input rx_3_n, + output rx_out_clk_3, + input rx_clk_3, + output [DATA_PATH_WIDTH-1:0] rx_charisk_3, + output [DATA_PATH_WIDTH-1:0] rx_disperr_3, + output [DATA_PATH_WIDTH-1:0] rx_notintable_3, + output [DATA_PATH_WIDTH*8-1:0] rx_data_3, + input rx_calign_3, + output [1:0] rx_header_3, + output rx_block_sync_3, - output tx_3_p, - output tx_3_n, - output tx_out_clk_3, - input tx_clk_3, - input [ 3:0] tx_charisk_3, - input [31:0] tx_data_3, + output tx_3_p, + output tx_3_n, + output tx_out_clk_3, + input tx_clk_3, + input [DATA_PATH_WIDTH-1:0] tx_charisk_3, + input [DATA_PATH_WIDTH*8-1:0] tx_data_3, + input [1:0] tx_header_3, input up_es_enb_3, input [11:0] up_es_addr_3, @@ -387,22 +407,25 @@ module util_adxcvr #( input cpll_ref_clk_4, input up_cpll_rst_4, - input rx_4_p, - input rx_4_n, - output rx_out_clk_4, - input rx_clk_4, - output [ 3:0] rx_charisk_4, - output [ 3:0] rx_disperr_4, - output [ 3:0] rx_notintable_4, - output [31:0] rx_data_4, - input rx_calign_4, + input rx_4_p, + input rx_4_n, + output rx_out_clk_4, + input rx_clk_4, + output [DATA_PATH_WIDTH-1:0] rx_charisk_4, + output [DATA_PATH_WIDTH-1:0] rx_disperr_4, + output [DATA_PATH_WIDTH-1:0] rx_notintable_4, + output [DATA_PATH_WIDTH*8-1:0] rx_data_4, + input rx_calign_4, + output [1:0] rx_header_4, + output rx_block_sync_4, - output tx_4_p, - output tx_4_n, - output tx_out_clk_4, - input tx_clk_4, - input [ 3:0] tx_charisk_4, - input [31:0] tx_data_4, + output tx_4_p, + output tx_4_n, + output tx_out_clk_4, + input tx_clk_4, + input [DATA_PATH_WIDTH-1:0] tx_charisk_4, + input [DATA_PATH_WIDTH*8-1:0] tx_data_4, + input [1:0] tx_header_4, input up_cm_enb_4, input [11:0] up_cm_addr_4, @@ -458,22 +481,25 @@ module util_adxcvr #( input cpll_ref_clk_5, input up_cpll_rst_5, - input rx_5_p, - input rx_5_n, - output rx_out_clk_5, - input rx_clk_5, - output [ 3:0] rx_charisk_5, - output [ 3:0] rx_disperr_5, - output [ 3:0] rx_notintable_5, - output [31:0] rx_data_5, - input rx_calign_5, + input rx_5_p, + input rx_5_n, + output rx_out_clk_5, + input rx_clk_5, + output [DATA_PATH_WIDTH-1:0] rx_charisk_5, + output [DATA_PATH_WIDTH-1:0] rx_disperr_5, + output [DATA_PATH_WIDTH-1:0] rx_notintable_5, + output [DATA_PATH_WIDTH*8-1:0] rx_data_5, + input rx_calign_5, + output [1:0] rx_header_5, + output rx_block_sync_5, - output tx_5_p, - output tx_5_n, - output tx_out_clk_5, - input tx_clk_5, - input [ 3:0] tx_charisk_5, - input [31:0] tx_data_5, + output tx_5_p, + output tx_5_n, + output tx_out_clk_5, + input tx_clk_5, + input [DATA_PATH_WIDTH-1:0] tx_charisk_5, + input [DATA_PATH_WIDTH*8-1:0] tx_data_5, + input [1:0] tx_header_5, input up_es_enb_5, input [11:0] up_es_addr_5, @@ -523,22 +549,25 @@ module util_adxcvr #( input cpll_ref_clk_6, input up_cpll_rst_6, - input rx_6_p, - input rx_6_n, - output rx_out_clk_6, - input rx_clk_6, - output [ 3:0] rx_charisk_6, - output [ 3:0] rx_disperr_6, - output [ 3:0] rx_notintable_6, - output [31:0] rx_data_6, - input rx_calign_6, + input rx_6_p, + input rx_6_n, + output rx_out_clk_6, + input rx_clk_6, + output [DATA_PATH_WIDTH-1:0] rx_charisk_6, + output [DATA_PATH_WIDTH-1:0] rx_disperr_6, + output [DATA_PATH_WIDTH-1:0] rx_notintable_6, + output [DATA_PATH_WIDTH*8-1:0] rx_data_6, + input rx_calign_6, + output [1:0] rx_header_6, + output rx_block_sync_6, - output tx_6_p, - output tx_6_n, - output tx_out_clk_6, - input tx_clk_6, - input [ 3:0] tx_charisk_6, - input [31:0] tx_data_6, + output tx_6_p, + output tx_6_n, + output tx_out_clk_6, + input tx_clk_6, + input [DATA_PATH_WIDTH-1:0] tx_charisk_6, + input [DATA_PATH_WIDTH*8-1:0] tx_data_6, + input [1:0] tx_header_6, input up_es_enb_6, input [11:0] up_es_addr_6, @@ -588,22 +617,25 @@ module util_adxcvr #( input cpll_ref_clk_7, input up_cpll_rst_7, - input rx_7_p, - input rx_7_n, - output rx_out_clk_7, - input rx_clk_7, - output [ 3:0] rx_charisk_7, - output [ 3:0] rx_disperr_7, - output [ 3:0] rx_notintable_7, - output [31:0] rx_data_7, - input rx_calign_7, + input rx_7_p, + input rx_7_n, + output rx_out_clk_7, + input rx_clk_7, + output [DATA_PATH_WIDTH-1:0] rx_charisk_7, + output [DATA_PATH_WIDTH-1:0] rx_disperr_7, + output [DATA_PATH_WIDTH-1:0] rx_notintable_7, + output [DATA_PATH_WIDTH*8-1:0] rx_data_7, + input rx_calign_7, + output [1:0] rx_header_7, + output rx_block_sync_7, - output tx_7_p, - output tx_7_n, - output tx_out_clk_7, - input tx_clk_7, - input [ 3:0] tx_charisk_7, - input [31:0] tx_data_7, + output tx_7_p, + output tx_7_n, + output tx_out_clk_7, + input tx_clk_7, + input [DATA_PATH_WIDTH-1:0] tx_charisk_7, + input [DATA_PATH_WIDTH*8-1:0] tx_data_7, + input [1:0] tx_header_7, input up_es_enb_7, input [11:0] up_es_addr_7, @@ -655,22 +687,25 @@ module util_adxcvr #( input cpll_ref_clk_8, input up_cpll_rst_8, - input rx_8_p, - input rx_8_n, - output rx_out_clk_8, - input rx_clk_8, - output [ 3:0] rx_charisk_8, - output [ 3:0] rx_disperr_8, - output [ 3:0] rx_notintable_8, - output [31:0] rx_data_8, - input rx_calign_8, + input rx_8_p, + input rx_8_n, + output rx_out_clk_8, + input rx_clk_8, + output [DATA_PATH_WIDTH-1:0] rx_charisk_8, + output [DATA_PATH_WIDTH-1:0] rx_disperr_8, + output [DATA_PATH_WIDTH-1:0] rx_notintable_8, + output [DATA_PATH_WIDTH*8-1:0] rx_data_8, + input rx_calign_8, + output [1:0] rx_header_8, + output rx_block_sync_8, - output tx_8_p, - output tx_8_n, - output tx_out_clk_8, - input tx_clk_8, - input [ 3:0] tx_charisk_8, - input [31:0] tx_data_8, + output tx_8_p, + output tx_8_n, + output tx_out_clk_8, + input tx_clk_8, + input [DATA_PATH_WIDTH-1:0] tx_charisk_8, + input [DATA_PATH_WIDTH*8-1:0] tx_data_8, + input [1:0] tx_header_8, input up_cm_enb_8, input [11:0] up_cm_addr_8, @@ -726,22 +761,25 @@ module util_adxcvr #( input cpll_ref_clk_9, input up_cpll_rst_9, - input rx_9_p, - input rx_9_n, - output rx_out_clk_9, - input rx_clk_9, - output [ 3:0] rx_charisk_9, - output [ 3:0] rx_disperr_9, - output [ 3:0] rx_notintable_9, - output [31:0] rx_data_9, - input rx_calign_9, + input rx_9_p, + input rx_9_n, + output rx_out_clk_9, + input rx_clk_9, + output [DATA_PATH_WIDTH-1:0] rx_charisk_9, + output [DATA_PATH_WIDTH-1:0] rx_disperr_9, + output [DATA_PATH_WIDTH-1:0] rx_notintable_9, + output [DATA_PATH_WIDTH*8-1:0] rx_data_9, + input rx_calign_9, + output [1:0] rx_header_9, + output rx_block_sync_9, - output tx_9_p, - output tx_9_n, - output tx_out_clk_9, - input tx_clk_9, - input [ 3:0] tx_charisk_9, - input [31:0] tx_data_9, + output tx_9_p, + output tx_9_n, + output tx_out_clk_9, + input tx_clk_9, + input [DATA_PATH_WIDTH-1:0] tx_charisk_9, + input [DATA_PATH_WIDTH*8-1:0] tx_data_9, + input [1:0] tx_header_9, input up_es_enb_9, input [11:0] up_es_addr_9, @@ -791,22 +829,25 @@ module util_adxcvr #( input cpll_ref_clk_10, input up_cpll_rst_10, - input rx_10_p, - input rx_10_n, - output rx_out_clk_10, - input rx_clk_10, - output [ 3:0] rx_charisk_10, - output [ 3:0] rx_disperr_10, - output [ 3:0] rx_notintable_10, - output [31:0] rx_data_10, - input rx_calign_10, + input rx_10_p, + input rx_10_n, + output rx_out_clk_10, + input rx_clk_10, + output [DATA_PATH_WIDTH-1:0] rx_charisk_10, + output [DATA_PATH_WIDTH-1:0] rx_disperr_10, + output [DATA_PATH_WIDTH-1:0] rx_notintable_10, + output [DATA_PATH_WIDTH*8-1:0] rx_data_10, + input rx_calign_10, + output [1:0] rx_header_10, + output rx_block_sync_10, - output tx_10_p, - output tx_10_n, - output tx_out_clk_10, - input tx_clk_10, - input [ 3:0] tx_charisk_10, - input [31:0] tx_data_10, + output tx_10_p, + output tx_10_n, + output tx_out_clk_10, + input tx_clk_10, + input [DATA_PATH_WIDTH-1:0] tx_charisk_10, + input [DATA_PATH_WIDTH*8-1:0] tx_data_10, + input [1:0] tx_header_10, input up_es_enb_10, input [11:0] up_es_addr_10, @@ -856,22 +897,25 @@ module util_adxcvr #( input cpll_ref_clk_11, input up_cpll_rst_11, - input rx_11_p, - input rx_11_n, - output rx_out_clk_11, - input rx_clk_11, - output [ 3:0] rx_charisk_11, - output [ 3:0] rx_disperr_11, - output [ 3:0] rx_notintable_11, - output [31:0] rx_data_11, - input rx_calign_11, + input rx_11_p, + input rx_11_n, + output rx_out_clk_11, + input rx_clk_11, + output [DATA_PATH_WIDTH-1:0] rx_charisk_11, + output [DATA_PATH_WIDTH-1:0] rx_disperr_11, + output [DATA_PATH_WIDTH-1:0] rx_notintable_11, + output [DATA_PATH_WIDTH*8-1:0] rx_data_11, + input rx_calign_11, + output [1:0] rx_header_11, + output rx_block_sync_11, - output tx_11_p, - output tx_11_n, - output tx_out_clk_11, - input tx_clk_11, - input [ 3:0] tx_charisk_11, - input [31:0] tx_data_11, + output tx_11_p, + output tx_11_n, + output tx_out_clk_11, + input tx_clk_11, + input [DATA_PATH_WIDTH-1:0] tx_charisk_11, + input [DATA_PATH_WIDTH*8-1:0] tx_data_11, + input [1:0] tx_header_11, input up_es_enb_11, input [11:0] up_es_addr_11, @@ -923,22 +967,25 @@ module util_adxcvr #( input cpll_ref_clk_12, input up_cpll_rst_12, - input rx_12_p, - input rx_12_n, - output rx_out_clk_12, - input rx_clk_12, - output [ 3:0] rx_charisk_12, - output [ 3:0] rx_disperr_12, - output [ 3:0] rx_notintable_12, - output [31:0] rx_data_12, - input rx_calign_12, + input rx_12_p, + input rx_12_n, + output rx_out_clk_12, + input rx_clk_12, + output [DATA_PATH_WIDTH-1:0] rx_charisk_12, + output [DATA_PATH_WIDTH-1:0] rx_disperr_12, + output [DATA_PATH_WIDTH-1:0] rx_notintable_12, + output [DATA_PATH_WIDTH*8-1:0] rx_data_12, + input rx_calign_12, + output [1:0] rx_header_12, + output rx_block_sync_12, - output tx_12_p, - output tx_12_n, - output tx_out_clk_12, - input tx_clk_12, - input [ 3:0] tx_charisk_12, - input [31:0] tx_data_12, + output tx_12_p, + output tx_12_n, + output tx_out_clk_12, + input tx_clk_12, + input [DATA_PATH_WIDTH-1:0] tx_charisk_12, + input [DATA_PATH_WIDTH*8-1:0] tx_data_12, + input [1:0] tx_header_12, input up_cm_enb_12, input [11:0] up_cm_addr_12, @@ -994,22 +1041,25 @@ module util_adxcvr #( input cpll_ref_clk_13, input up_cpll_rst_13, - input rx_13_p, - input rx_13_n, - output rx_out_clk_13, - input rx_clk_13, - output [ 3:0] rx_charisk_13, - output [ 3:0] rx_disperr_13, - output [ 3:0] rx_notintable_13, - output [31:0] rx_data_13, - input rx_calign_13, + input rx_13_p, + input rx_13_n, + output rx_out_clk_13, + input rx_clk_13, + output [DATA_PATH_WIDTH-1:0] rx_charisk_13, + output [DATA_PATH_WIDTH-1:0] rx_disperr_13, + output [DATA_PATH_WIDTH-1:0] rx_notintable_13, + output [DATA_PATH_WIDTH*8-1:0] rx_data_13, + input rx_calign_13, + output [1:0] rx_header_13, + output rx_block_sync_13, - output tx_13_p, - output tx_13_n, - output tx_out_clk_13, - input tx_clk_13, - input [ 3:0] tx_charisk_13, - input [31:0] tx_data_13, + output tx_13_p, + output tx_13_n, + output tx_out_clk_13, + input tx_clk_13, + input [DATA_PATH_WIDTH-1:0] tx_charisk_13, + input [DATA_PATH_WIDTH*8-1:0] tx_data_13, + input [1:0] tx_header_13, input up_es_enb_13, input [11:0] up_es_addr_13, @@ -1059,22 +1109,25 @@ module util_adxcvr #( input cpll_ref_clk_14, input up_cpll_rst_14, - input rx_14_p, - input rx_14_n, - output rx_out_clk_14, - input rx_clk_14, - output [ 3:0] rx_charisk_14, - output [ 3:0] rx_disperr_14, - output [ 3:0] rx_notintable_14, - output [31:0] rx_data_14, - input rx_calign_14, + input rx_14_p, + input rx_14_n, + output rx_out_clk_14, + input rx_clk_14, + output [DATA_PATH_WIDTH-1:0] rx_charisk_14, + output [DATA_PATH_WIDTH-1:0] rx_disperr_14, + output [DATA_PATH_WIDTH-1:0] rx_notintable_14, + output [DATA_PATH_WIDTH*8-1:0] rx_data_14, + input rx_calign_14, + output [1:0] rx_header_14, + output rx_block_sync_14, - output tx_14_p, - output tx_14_n, - output tx_out_clk_14, - input tx_clk_14, - input [ 3:0] tx_charisk_14, - input [31:0] tx_data_14, + output tx_14_p, + output tx_14_n, + output tx_out_clk_14, + input tx_clk_14, + input [DATA_PATH_WIDTH-1:0] tx_charisk_14, + input [DATA_PATH_WIDTH*8-1:0] tx_data_14, + input [1:0] tx_header_14, input up_es_enb_14, input [11:0] up_es_addr_14, @@ -1124,22 +1177,25 @@ module util_adxcvr #( input cpll_ref_clk_15, input up_cpll_rst_15, - input rx_15_p, - input rx_15_n, - output rx_out_clk_15, - input rx_clk_15, - output [ 3:0] rx_charisk_15, - output [ 3:0] rx_disperr_15, - output [ 3:0] rx_notintable_15, - output [31:0] rx_data_15, - input rx_calign_15, + input rx_15_p, + input rx_15_n, + output rx_out_clk_15, + input rx_clk_15, + output [DATA_PATH_WIDTH-1:0] rx_charisk_15, + output [DATA_PATH_WIDTH-1:0] rx_disperr_15, + output [DATA_PATH_WIDTH-1:0] rx_notintable_15, + output [DATA_PATH_WIDTH*8-1:0] rx_data_15, + input rx_calign_15, + output [1:0] rx_header_15, + output rx_block_sync_15, - output tx_15_p, - output tx_15_n, - output tx_out_clk_15, - input tx_clk_15, - input [ 3:0] tx_charisk_15, - input [31:0] tx_data_15, + output tx_15_p, + output tx_15_n, + output tx_out_clk_15, + input tx_clk_15, + input [DATA_PATH_WIDTH-1:0] tx_charisk_15, + input [DATA_PATH_WIDTH*8-1:0] tx_data_15, + input [1:0] tx_header_15, input up_es_enb_15, input [11:0] up_es_addr_15, @@ -1295,6 +1351,8 @@ module util_adxcvr #( if (NUM_OF_LANES >= 1) begin util_adxcvr_xch #( .XCVR_TYPE (XCVR_TYPE), + .LINK_MODE (LINK_MODE), + .DATA_PATH_WIDTH (DATA_PATH_WIDTH), .CPLL_FBDIV (CPLL_FBDIV), .CPLL_FBDIV_4_5 (CPLL_FBDIV_4_5), .CPLL_CFG0 (CPLL_CFG0), @@ -1321,14 +1379,18 @@ module util_adxcvr #( .RXCDR_CFG3_GEN2 (RXCDR_CFG3_GEN2), .RXCDR_CFG3_GEN3 (RXCDR_CFG3_GEN3), .RXCDR_CFG3_GEN4 (RXCDR_CFG3_GEN4), + .RXDFE_KH_CFG2 (RXDFE_KH_CFG2), + .RXDFE_KH_CFG3 (RXDFE_KH_CFG3), .RX_WIDEMODE_CDR (RX_WIDEMODE_CDR), .RX_XMODE_SEL (RX_XMODE_SEL), .TXDRV_FREQBAND (TXDRV_FREQBAND), + .TXFE_CFG0 (TXFE_CFG0), .TXFE_CFG1 (TXFE_CFG1), .TXFE_CFG2 (TXFE_CFG2), .TXFE_CFG3 (TXFE_CFG3), .TXPI_CFG0 (TXPI_CFG0), .TXPI_CFG1 (TXPI_CFG1), + .TXSWBST_EN (TXSWBST_EN), .CH_HSPMUX (CH_HSPMUX), .PREIQ_FREQ_BST (PREIQ_FREQ_BST), .RXPI_CFG0 (RXPI_CFG0), @@ -1352,12 +1414,15 @@ module util_adxcvr #( .rx_notintable (rx_notintable_0), .rx_data (rx_data_0), .rx_calign (rx_calign_0), + .rx_header(rx_header_0), + .rx_block_sync(rx_block_sync_0), .tx_p (tx_0_p), .tx_n (tx_0_n), .tx_out_clk (tx_out_clk_0), .tx_clk (tx_clk_0), .tx_charisk (tx_charisk_0), .tx_data (tx_data_0), + .tx_header (tx_header_0), .up_rstn (up_rstn), .up_clk (up_clk), .up_es_enb (up_es_enb_0), @@ -1431,6 +1496,8 @@ module util_adxcvr #( if (NUM_OF_LANES >= 2) begin util_adxcvr_xch #( .XCVR_TYPE (XCVR_TYPE), + .LINK_MODE (LINK_MODE), + .DATA_PATH_WIDTH (DATA_PATH_WIDTH), .CPLL_FBDIV (CPLL_FBDIV), .CPLL_FBDIV_4_5 (CPLL_FBDIV_4_5), .CPLL_CFG0 (CPLL_CFG0), @@ -1457,14 +1524,18 @@ module util_adxcvr #( .RXCDR_CFG3_GEN2 (RXCDR_CFG3_GEN2), .RXCDR_CFG3_GEN3 (RXCDR_CFG3_GEN3), .RXCDR_CFG3_GEN4 (RXCDR_CFG3_GEN4), + .RXDFE_KH_CFG2 (RXDFE_KH_CFG2), + .RXDFE_KH_CFG3 (RXDFE_KH_CFG3), .RX_WIDEMODE_CDR (RX_WIDEMODE_CDR), .RX_XMODE_SEL (RX_XMODE_SEL), .TXDRV_FREQBAND (TXDRV_FREQBAND), + .TXFE_CFG0 (TXFE_CFG0), .TXFE_CFG1 (TXFE_CFG1), .TXFE_CFG2 (TXFE_CFG2), .TXFE_CFG3 (TXFE_CFG3), .TXPI_CFG0 (TXPI_CFG0), .TXPI_CFG1 (TXPI_CFG1), + .TXSWBST_EN (TXSWBST_EN), .CH_HSPMUX (CH_HSPMUX), .PREIQ_FREQ_BST (PREIQ_FREQ_BST), .RXPI_CFG0 (RXPI_CFG0), @@ -1488,12 +1559,15 @@ module util_adxcvr #( .rx_notintable (rx_notintable_1), .rx_data (rx_data_1), .rx_calign (rx_calign_1), + .rx_header(rx_header_1), + .rx_block_sync(rx_block_sync_1), .tx_p (tx_1_p), .tx_n (tx_1_n), .tx_out_clk (tx_out_clk_1), .tx_clk (tx_clk_1), .tx_charisk (tx_charisk_1), .tx_data (tx_data_1), + .tx_header (tx_header_1), .up_rstn (up_rstn), .up_clk (up_clk), .up_es_enb (up_es_enb_1), @@ -1567,6 +1641,8 @@ module util_adxcvr #( if (NUM_OF_LANES >= 3) begin util_adxcvr_xch #( .XCVR_TYPE (XCVR_TYPE), + .LINK_MODE (LINK_MODE), + .DATA_PATH_WIDTH (DATA_PATH_WIDTH), .CPLL_FBDIV (CPLL_FBDIV), .CPLL_FBDIV_4_5 (CPLL_FBDIV_4_5), .CPLL_CFG0 (CPLL_CFG0), @@ -1593,14 +1669,18 @@ module util_adxcvr #( .RXCDR_CFG3_GEN2 (RXCDR_CFG3_GEN2), .RXCDR_CFG3_GEN3 (RXCDR_CFG3_GEN3), .RXCDR_CFG3_GEN4 (RXCDR_CFG3_GEN4), + .RXDFE_KH_CFG2 (RXDFE_KH_CFG2), + .RXDFE_KH_CFG3 (RXDFE_KH_CFG3), .RX_WIDEMODE_CDR (RX_WIDEMODE_CDR), .RX_XMODE_SEL (RX_XMODE_SEL), .TXDRV_FREQBAND (TXDRV_FREQBAND), + .TXFE_CFG0 (TXFE_CFG0), .TXFE_CFG1 (TXFE_CFG1), .TXFE_CFG2 (TXFE_CFG2), .TXFE_CFG3 (TXFE_CFG3), .TXPI_CFG0 (TXPI_CFG0), .TXPI_CFG1 (TXPI_CFG1), + .TXSWBST_EN (TXSWBST_EN), .CH_HSPMUX (CH_HSPMUX), .PREIQ_FREQ_BST (PREIQ_FREQ_BST), .RXPI_CFG0 (RXPI_CFG0), @@ -1624,12 +1704,15 @@ module util_adxcvr #( .rx_notintable (rx_notintable_2), .rx_data (rx_data_2), .rx_calign (rx_calign_2), + .rx_header(rx_header_2), + .rx_block_sync(rx_block_sync_2), .tx_p (tx_2_p), .tx_n (tx_2_n), .tx_out_clk (tx_out_clk_2), .tx_clk (tx_clk_2), .tx_charisk (tx_charisk_2), .tx_data (tx_data_2), + .tx_header (tx_header_2), .up_rstn (up_rstn), .up_clk (up_clk), .up_es_enb (up_es_enb_2), @@ -1703,6 +1786,8 @@ module util_adxcvr #( if (NUM_OF_LANES >= 4) begin util_adxcvr_xch #( .XCVR_TYPE (XCVR_TYPE), + .LINK_MODE (LINK_MODE), + .DATA_PATH_WIDTH (DATA_PATH_WIDTH), .CPLL_FBDIV (CPLL_FBDIV), .CPLL_FBDIV_4_5 (CPLL_FBDIV_4_5), .CPLL_CFG0 (CPLL_CFG0), @@ -1729,14 +1814,18 @@ module util_adxcvr #( .RXCDR_CFG3_GEN2 (RXCDR_CFG3_GEN2), .RXCDR_CFG3_GEN3 (RXCDR_CFG3_GEN3), .RXCDR_CFG3_GEN4 (RXCDR_CFG3_GEN4), + .RXDFE_KH_CFG2 (RXDFE_KH_CFG2), + .RXDFE_KH_CFG3 (RXDFE_KH_CFG3), .RX_WIDEMODE_CDR (RX_WIDEMODE_CDR), .RX_XMODE_SEL (RX_XMODE_SEL), .TXDRV_FREQBAND (TXDRV_FREQBAND), + .TXFE_CFG0 (TXFE_CFG0), .TXFE_CFG1 (TXFE_CFG1), .TXFE_CFG2 (TXFE_CFG2), .TXFE_CFG3 (TXFE_CFG3), .TXPI_CFG0 (TXPI_CFG0), .TXPI_CFG1 (TXPI_CFG1), + .TXSWBST_EN (TXSWBST_EN), .CH_HSPMUX (CH_HSPMUX), .PREIQ_FREQ_BST (PREIQ_FREQ_BST), .RXPI_CFG0 (RXPI_CFG0), @@ -1760,12 +1849,15 @@ module util_adxcvr #( .rx_notintable (rx_notintable_3), .rx_data (rx_data_3), .rx_calign (rx_calign_3), + .rx_header(rx_header_3), + .rx_block_sync(rx_block_sync_3), .tx_p (tx_3_p), .tx_n (tx_3_n), .tx_out_clk (tx_out_clk_3), .tx_clk (tx_clk_3), .tx_charisk (tx_charisk_3), .tx_data (tx_data_3), + .tx_header (tx_header_3), .up_rstn (up_rstn), .up_clk (up_clk), .up_es_enb (up_es_enb_3), @@ -1888,6 +1980,8 @@ module util_adxcvr #( if (NUM_OF_LANES >= 5) begin util_adxcvr_xch #( .XCVR_TYPE (XCVR_TYPE), + .LINK_MODE (LINK_MODE), + .DATA_PATH_WIDTH (DATA_PATH_WIDTH), .CPLL_FBDIV (CPLL_FBDIV), .CPLL_FBDIV_4_5 (CPLL_FBDIV_4_5), .CPLL_CFG0 (CPLL_CFG0), @@ -1914,14 +2008,18 @@ module util_adxcvr #( .RXCDR_CFG3_GEN2 (RXCDR_CFG3_GEN2), .RXCDR_CFG3_GEN3 (RXCDR_CFG3_GEN3), .RXCDR_CFG3_GEN4 (RXCDR_CFG3_GEN4), + .RXDFE_KH_CFG2 (RXDFE_KH_CFG2), + .RXDFE_KH_CFG3 (RXDFE_KH_CFG3), .RX_WIDEMODE_CDR (RX_WIDEMODE_CDR), .RX_XMODE_SEL (RX_XMODE_SEL), .TXDRV_FREQBAND (TXDRV_FREQBAND), + .TXFE_CFG0 (TXFE_CFG0), .TXFE_CFG1 (TXFE_CFG1), .TXFE_CFG2 (TXFE_CFG2), .TXFE_CFG3 (TXFE_CFG3), .TXPI_CFG0 (TXPI_CFG0), .TXPI_CFG1 (TXPI_CFG1), + .TXSWBST_EN (TXSWBST_EN), .CH_HSPMUX (CH_HSPMUX), .PREIQ_FREQ_BST (PREIQ_FREQ_BST), .RXPI_CFG0 (RXPI_CFG0), @@ -1945,12 +2043,15 @@ module util_adxcvr #( .rx_notintable (rx_notintable_4), .rx_data (rx_data_4), .rx_calign (rx_calign_4), + .rx_header(rx_header_4), + .rx_block_sync(rx_block_sync_4), .tx_p (tx_4_p), .tx_n (tx_4_n), .tx_out_clk (tx_out_clk_4), .tx_clk (tx_clk_4), .tx_charisk (tx_charisk_4), .tx_data (tx_data_4), + .tx_header (tx_header_4), .up_rstn (up_rstn), .up_clk (up_clk), .up_es_enb (up_es_enb_4), @@ -2024,6 +2125,8 @@ module util_adxcvr #( if (NUM_OF_LANES >= 6) begin util_adxcvr_xch #( .XCVR_TYPE (XCVR_TYPE), + .LINK_MODE (LINK_MODE), + .DATA_PATH_WIDTH (DATA_PATH_WIDTH), .CPLL_FBDIV (CPLL_FBDIV), .CPLL_FBDIV_4_5 (CPLL_FBDIV_4_5), .CPLL_CFG0 (CPLL_CFG0), @@ -2050,14 +2153,18 @@ module util_adxcvr #( .RXCDR_CFG3_GEN2 (RXCDR_CFG3_GEN2), .RXCDR_CFG3_GEN3 (RXCDR_CFG3_GEN3), .RXCDR_CFG3_GEN4 (RXCDR_CFG3_GEN4), + .RXDFE_KH_CFG2 (RXDFE_KH_CFG2), + .RXDFE_KH_CFG3 (RXDFE_KH_CFG3), .RX_WIDEMODE_CDR (RX_WIDEMODE_CDR), .RX_XMODE_SEL (RX_XMODE_SEL), .TXDRV_FREQBAND (TXDRV_FREQBAND), + .TXFE_CFG0 (TXFE_CFG0), .TXFE_CFG1 (TXFE_CFG1), .TXFE_CFG2 (TXFE_CFG2), .TXFE_CFG3 (TXFE_CFG3), .TXPI_CFG0 (TXPI_CFG0), .TXPI_CFG1 (TXPI_CFG1), + .TXSWBST_EN (TXSWBST_EN), .CH_HSPMUX (CH_HSPMUX), .PREIQ_FREQ_BST (PREIQ_FREQ_BST), .RXPI_CFG0 (RXPI_CFG0), @@ -2081,12 +2188,15 @@ module util_adxcvr #( .rx_notintable (rx_notintable_5), .rx_data (rx_data_5), .rx_calign (rx_calign_5), + .rx_header(rx_header_5), + .rx_block_sync(rx_block_sync_5), .tx_p (tx_5_p), .tx_n (tx_5_n), .tx_out_clk (tx_out_clk_5), .tx_clk (tx_clk_5), .tx_charisk (tx_charisk_5), .tx_data (tx_data_5), + .tx_header (tx_header_5), .up_rstn (up_rstn), .up_clk (up_clk), .up_es_enb (up_es_enb_5), @@ -2160,6 +2270,8 @@ module util_adxcvr #( if (NUM_OF_LANES >= 7) begin util_adxcvr_xch #( .XCVR_TYPE (XCVR_TYPE), + .LINK_MODE (LINK_MODE), + .DATA_PATH_WIDTH (DATA_PATH_WIDTH), .CPLL_FBDIV (CPLL_FBDIV), .CPLL_FBDIV_4_5 (CPLL_FBDIV_4_5), .CPLL_CFG0 (CPLL_CFG0), @@ -2186,14 +2298,18 @@ module util_adxcvr #( .RXCDR_CFG3_GEN2 (RXCDR_CFG3_GEN2), .RXCDR_CFG3_GEN3 (RXCDR_CFG3_GEN3), .RXCDR_CFG3_GEN4 (RXCDR_CFG3_GEN4), + .RXDFE_KH_CFG2 (RXDFE_KH_CFG2), + .RXDFE_KH_CFG3 (RXDFE_KH_CFG3), .RX_WIDEMODE_CDR (RX_WIDEMODE_CDR), .RX_XMODE_SEL (RX_XMODE_SEL), .TXDRV_FREQBAND (TXDRV_FREQBAND), + .TXFE_CFG0 (TXFE_CFG0), .TXFE_CFG1 (TXFE_CFG1), .TXFE_CFG2 (TXFE_CFG2), .TXFE_CFG3 (TXFE_CFG3), .TXPI_CFG0 (TXPI_CFG0), .TXPI_CFG1 (TXPI_CFG1), + .TXSWBST_EN (TXSWBST_EN), .CH_HSPMUX (CH_HSPMUX), .PREIQ_FREQ_BST (PREIQ_FREQ_BST), .RXPI_CFG0 (RXPI_CFG0), @@ -2217,12 +2333,15 @@ module util_adxcvr #( .rx_notintable (rx_notintable_6), .rx_data (rx_data_6), .rx_calign (rx_calign_6), + .rx_header(rx_header_6), + .rx_block_sync(rx_block_sync_6), .tx_p (tx_6_p), .tx_n (tx_6_n), .tx_out_clk (tx_out_clk_6), .tx_clk (tx_clk_6), .tx_charisk (tx_charisk_6), .tx_data (tx_data_6), + .tx_header (tx_header_6), .up_rstn (up_rstn), .up_clk (up_clk), .up_es_enb (up_es_enb_6), @@ -2296,6 +2415,8 @@ module util_adxcvr #( if (NUM_OF_LANES >= 8) begin util_adxcvr_xch #( .XCVR_TYPE (XCVR_TYPE), + .LINK_MODE (LINK_MODE), + .DATA_PATH_WIDTH (DATA_PATH_WIDTH), .CPLL_FBDIV (CPLL_FBDIV), .CPLL_FBDIV_4_5 (CPLL_FBDIV_4_5), .CPLL_CFG0 (CPLL_CFG0), @@ -2322,14 +2443,18 @@ module util_adxcvr #( .RXCDR_CFG3_GEN2 (RXCDR_CFG3_GEN2), .RXCDR_CFG3_GEN3 (RXCDR_CFG3_GEN3), .RXCDR_CFG3_GEN4 (RXCDR_CFG3_GEN4), + .RXDFE_KH_CFG2 (RXDFE_KH_CFG2), + .RXDFE_KH_CFG3 (RXDFE_KH_CFG3), .RX_WIDEMODE_CDR (RX_WIDEMODE_CDR), .RX_XMODE_SEL (RX_XMODE_SEL), .TXDRV_FREQBAND (TXDRV_FREQBAND), + .TXFE_CFG0 (TXFE_CFG0), .TXFE_CFG1 (TXFE_CFG1), .TXFE_CFG2 (TXFE_CFG2), .TXFE_CFG3 (TXFE_CFG3), .TXPI_CFG0 (TXPI_CFG0), .TXPI_CFG1 (TXPI_CFG1), + .TXSWBST_EN (TXSWBST_EN), .CH_HSPMUX (CH_HSPMUX), .PREIQ_FREQ_BST (PREIQ_FREQ_BST), .RXPI_CFG0 (RXPI_CFG0), @@ -2353,12 +2478,15 @@ module util_adxcvr #( .rx_notintable (rx_notintable_7), .rx_data (rx_data_7), .rx_calign (rx_calign_7), + .rx_header(rx_header_7), + .rx_block_sync(rx_block_sync_7), .tx_p (tx_7_p), .tx_n (tx_7_n), .tx_out_clk (tx_out_clk_7), .tx_clk (tx_clk_7), .tx_charisk (tx_charisk_7), .tx_data (tx_data_7), + .tx_header (tx_header_7), .up_rstn (up_rstn), .up_clk (up_clk), .up_es_enb (up_es_enb_7), @@ -2481,6 +2609,8 @@ module util_adxcvr #( if (NUM_OF_LANES >= 9) begin util_adxcvr_xch #( .XCVR_TYPE (XCVR_TYPE), + .LINK_MODE (LINK_MODE), + .DATA_PATH_WIDTH (DATA_PATH_WIDTH), .CPLL_FBDIV (CPLL_FBDIV), .CPLL_FBDIV_4_5 (CPLL_FBDIV_4_5), .CPLL_CFG0 (CPLL_CFG0), @@ -2507,14 +2637,18 @@ module util_adxcvr #( .RXCDR_CFG3_GEN2 (RXCDR_CFG3_GEN2), .RXCDR_CFG3_GEN3 (RXCDR_CFG3_GEN3), .RXCDR_CFG3_GEN4 (RXCDR_CFG3_GEN4), + .RXDFE_KH_CFG2 (RXDFE_KH_CFG2), + .RXDFE_KH_CFG3 (RXDFE_KH_CFG3), .RX_WIDEMODE_CDR (RX_WIDEMODE_CDR), .RX_XMODE_SEL (RX_XMODE_SEL), .TXDRV_FREQBAND (TXDRV_FREQBAND), + .TXFE_CFG0 (TXFE_CFG0), .TXFE_CFG1 (TXFE_CFG1), .TXFE_CFG2 (TXFE_CFG2), .TXFE_CFG3 (TXFE_CFG3), .TXPI_CFG0 (TXPI_CFG0), .TXPI_CFG1 (TXPI_CFG1), + .TXSWBST_EN (TXSWBST_EN), .CH_HSPMUX (CH_HSPMUX), .PREIQ_FREQ_BST (PREIQ_FREQ_BST), .RXPI_CFG0 (RXPI_CFG0), @@ -2538,12 +2672,15 @@ module util_adxcvr #( .rx_notintable (rx_notintable_8), .rx_data (rx_data_8), .rx_calign (rx_calign_8), + .rx_header(rx_header_8), + .rx_block_sync(rx_block_sync_8), .tx_p (tx_8_p), .tx_n (tx_8_n), .tx_out_clk (tx_out_clk_8), .tx_clk (tx_clk_8), .tx_charisk (tx_charisk_8), .tx_data (tx_data_8), + .tx_header (tx_header_8), .up_rstn (up_rstn), .up_clk (up_clk), .up_es_enb (up_es_enb_8), @@ -2617,6 +2754,8 @@ module util_adxcvr #( if (NUM_OF_LANES >= 10) begin util_adxcvr_xch #( .XCVR_TYPE (XCVR_TYPE), + .LINK_MODE (LINK_MODE), + .DATA_PATH_WIDTH (DATA_PATH_WIDTH), .CPLL_FBDIV (CPLL_FBDIV), .CPLL_FBDIV_4_5 (CPLL_FBDIV_4_5), .CPLL_CFG0 (CPLL_CFG0), @@ -2643,14 +2782,18 @@ module util_adxcvr #( .RXCDR_CFG3_GEN2 (RXCDR_CFG3_GEN2), .RXCDR_CFG3_GEN3 (RXCDR_CFG3_GEN3), .RXCDR_CFG3_GEN4 (RXCDR_CFG3_GEN4), + .RXDFE_KH_CFG2 (RXDFE_KH_CFG2), + .RXDFE_KH_CFG3 (RXDFE_KH_CFG3), .RX_WIDEMODE_CDR (RX_WIDEMODE_CDR), .RX_XMODE_SEL (RX_XMODE_SEL), .TXDRV_FREQBAND (TXDRV_FREQBAND), + .TXFE_CFG0 (TXFE_CFG0), .TXFE_CFG1 (TXFE_CFG1), .TXFE_CFG2 (TXFE_CFG2), .TXFE_CFG3 (TXFE_CFG3), .TXPI_CFG0 (TXPI_CFG0), .TXPI_CFG1 (TXPI_CFG1), + .TXSWBST_EN (TXSWBST_EN), .CH_HSPMUX (CH_HSPMUX), .PREIQ_FREQ_BST (PREIQ_FREQ_BST), .RXPI_CFG0 (RXPI_CFG0), @@ -2674,12 +2817,15 @@ module util_adxcvr #( .rx_notintable (rx_notintable_9), .rx_data (rx_data_9), .rx_calign (rx_calign_9), + .rx_header(rx_header_9), + .rx_block_sync(rx_block_sync_9), .tx_p (tx_9_p), .tx_n (tx_9_n), .tx_out_clk (tx_out_clk_9), .tx_clk (tx_clk_9), .tx_charisk (tx_charisk_9), .tx_data (tx_data_9), + .tx_header (tx_header_9), .up_rstn (up_rstn), .up_clk (up_clk), .up_es_enb (up_es_enb_9), @@ -2753,6 +2899,8 @@ module util_adxcvr #( if (NUM_OF_LANES >= 11) begin util_adxcvr_xch #( .XCVR_TYPE (XCVR_TYPE), + .LINK_MODE (LINK_MODE), + .DATA_PATH_WIDTH (DATA_PATH_WIDTH), .CPLL_FBDIV (CPLL_FBDIV), .CPLL_FBDIV_4_5 (CPLL_FBDIV_4_5), .CPLL_CFG0 (CPLL_CFG0), @@ -2779,14 +2927,18 @@ module util_adxcvr #( .RXCDR_CFG3_GEN2 (RXCDR_CFG3_GEN2), .RXCDR_CFG3_GEN3 (RXCDR_CFG3_GEN3), .RXCDR_CFG3_GEN4 (RXCDR_CFG3_GEN4), + .RXDFE_KH_CFG2 (RXDFE_KH_CFG2), + .RXDFE_KH_CFG3 (RXDFE_KH_CFG3), .RX_WIDEMODE_CDR (RX_WIDEMODE_CDR), .RX_XMODE_SEL (RX_XMODE_SEL), .TXDRV_FREQBAND (TXDRV_FREQBAND), + .TXFE_CFG0 (TXFE_CFG0), .TXFE_CFG1 (TXFE_CFG1), .TXFE_CFG2 (TXFE_CFG2), .TXFE_CFG3 (TXFE_CFG3), .TXPI_CFG0 (TXPI_CFG0), .TXPI_CFG1 (TXPI_CFG1), + .TXSWBST_EN (TXSWBST_EN), .CH_HSPMUX (CH_HSPMUX), .PREIQ_FREQ_BST (PREIQ_FREQ_BST), .RXPI_CFG0 (RXPI_CFG0), @@ -2810,12 +2962,15 @@ module util_adxcvr #( .rx_notintable (rx_notintable_10), .rx_data (rx_data_10), .rx_calign (rx_calign_10), + .rx_header(rx_header_10), + .rx_block_sync(rx_block_sync_10), .tx_p (tx_10_p), .tx_n (tx_10_n), .tx_out_clk (tx_out_clk_10), .tx_clk (tx_clk_10), .tx_charisk (tx_charisk_10), .tx_data (tx_data_10), + .tx_header (tx_header_10), .up_rstn (up_rstn), .up_clk (up_clk), .up_es_enb (up_es_enb_10), @@ -2889,6 +3044,8 @@ module util_adxcvr #( if (NUM_OF_LANES >= 12) begin util_adxcvr_xch #( .XCVR_TYPE (XCVR_TYPE), + .LINK_MODE (LINK_MODE), + .DATA_PATH_WIDTH (DATA_PATH_WIDTH), .CPLL_FBDIV (CPLL_FBDIV), .CPLL_FBDIV_4_5 (CPLL_FBDIV_4_5), .CPLL_CFG0 (CPLL_CFG0), @@ -2915,14 +3072,18 @@ module util_adxcvr #( .RXCDR_CFG3_GEN2 (RXCDR_CFG3_GEN2), .RXCDR_CFG3_GEN3 (RXCDR_CFG3_GEN3), .RXCDR_CFG3_GEN4 (RXCDR_CFG3_GEN4), + .RXDFE_KH_CFG2 (RXDFE_KH_CFG2), + .RXDFE_KH_CFG3 (RXDFE_KH_CFG3), .RX_WIDEMODE_CDR (RX_WIDEMODE_CDR), .RX_XMODE_SEL (RX_XMODE_SEL), .TXDRV_FREQBAND (TXDRV_FREQBAND), + .TXFE_CFG0 (TXFE_CFG0), .TXFE_CFG1 (TXFE_CFG1), .TXFE_CFG2 (TXFE_CFG2), .TXFE_CFG3 (TXFE_CFG3), .TXPI_CFG0 (TXPI_CFG0), .TXPI_CFG1 (TXPI_CFG1), + .TXSWBST_EN (TXSWBST_EN), .CH_HSPMUX (CH_HSPMUX), .PREIQ_FREQ_BST (PREIQ_FREQ_BST), .RXPI_CFG0 (RXPI_CFG0), @@ -2946,12 +3107,15 @@ module util_adxcvr #( .rx_notintable (rx_notintable_11), .rx_data (rx_data_11), .rx_calign (rx_calign_11), + .rx_header(rx_header_11), + .rx_block_sync(rx_block_sync_11), .tx_p (tx_11_p), .tx_n (tx_11_n), .tx_out_clk (tx_out_clk_11), .tx_clk (tx_clk_11), .tx_charisk (tx_charisk_11), .tx_data (tx_data_11), + .tx_header (tx_header_11), .up_rstn (up_rstn), .up_clk (up_clk), .up_es_enb (up_es_enb_11), @@ -3074,6 +3238,8 @@ module util_adxcvr #( if (NUM_OF_LANES >= 13) begin util_adxcvr_xch #( .XCVR_TYPE (XCVR_TYPE), + .LINK_MODE (LINK_MODE), + .DATA_PATH_WIDTH (DATA_PATH_WIDTH), .CPLL_FBDIV (CPLL_FBDIV), .CPLL_FBDIV_4_5 (CPLL_FBDIV_4_5), .CPLL_CFG0 (CPLL_CFG0), @@ -3100,14 +3266,18 @@ module util_adxcvr #( .RXCDR_CFG3_GEN2 (RXCDR_CFG3_GEN2), .RXCDR_CFG3_GEN3 (RXCDR_CFG3_GEN3), .RXCDR_CFG3_GEN4 (RXCDR_CFG3_GEN4), + .RXDFE_KH_CFG2 (RXDFE_KH_CFG2), + .RXDFE_KH_CFG3 (RXDFE_KH_CFG3), .RX_WIDEMODE_CDR (RX_WIDEMODE_CDR), .RX_XMODE_SEL (RX_XMODE_SEL), .TXDRV_FREQBAND (TXDRV_FREQBAND), + .TXFE_CFG0 (TXFE_CFG0), .TXFE_CFG1 (TXFE_CFG1), .TXFE_CFG2 (TXFE_CFG2), .TXFE_CFG3 (TXFE_CFG3), .TXPI_CFG0 (TXPI_CFG0), .TXPI_CFG1 (TXPI_CFG1), + .TXSWBST_EN (TXSWBST_EN), .CH_HSPMUX (CH_HSPMUX), .PREIQ_FREQ_BST (PREIQ_FREQ_BST), .RXPI_CFG0 (RXPI_CFG0), @@ -3131,12 +3301,15 @@ module util_adxcvr #( .rx_notintable (rx_notintable_12), .rx_data (rx_data_12), .rx_calign (rx_calign_12), + .rx_header(rx_header_12), + .rx_block_sync(rx_block_sync_12), .tx_p (tx_12_p), .tx_n (tx_12_n), .tx_out_clk (tx_out_clk_12), .tx_clk (tx_clk_12), .tx_charisk (tx_charisk_12), .tx_data (tx_data_12), + .tx_header (tx_header_12), .up_rstn (up_rstn), .up_clk (up_clk), .up_es_enb (up_es_enb_12), @@ -3210,6 +3383,8 @@ module util_adxcvr #( if (NUM_OF_LANES >= 14) begin util_adxcvr_xch #( .XCVR_TYPE (XCVR_TYPE), + .LINK_MODE (LINK_MODE), + .DATA_PATH_WIDTH (DATA_PATH_WIDTH), .CPLL_FBDIV (CPLL_FBDIV), .CPLL_FBDIV_4_5 (CPLL_FBDIV_4_5), .CPLL_CFG0 (CPLL_CFG0), @@ -3236,14 +3411,18 @@ module util_adxcvr #( .RXCDR_CFG3_GEN2 (RXCDR_CFG3_GEN2), .RXCDR_CFG3_GEN3 (RXCDR_CFG3_GEN3), .RXCDR_CFG3_GEN4 (RXCDR_CFG3_GEN4), + .RXDFE_KH_CFG2 (RXDFE_KH_CFG2), + .RXDFE_KH_CFG3 (RXDFE_KH_CFG3), .RX_WIDEMODE_CDR (RX_WIDEMODE_CDR), .RX_XMODE_SEL (RX_XMODE_SEL), .TXDRV_FREQBAND (TXDRV_FREQBAND), + .TXFE_CFG0 (TXFE_CFG0), .TXFE_CFG1 (TXFE_CFG1), .TXFE_CFG2 (TXFE_CFG2), .TXFE_CFG3 (TXFE_CFG3), .TXPI_CFG0 (TXPI_CFG0), .TXPI_CFG1 (TXPI_CFG1), + .TXSWBST_EN (TXSWBST_EN), .CH_HSPMUX (CH_HSPMUX), .PREIQ_FREQ_BST (PREIQ_FREQ_BST), .RXPI_CFG0 (RXPI_CFG0), @@ -3267,12 +3446,15 @@ module util_adxcvr #( .rx_notintable (rx_notintable_13), .rx_data (rx_data_13), .rx_calign (rx_calign_13), + .rx_header(rx_header_13), + .rx_block_sync(rx_block_sync_13), .tx_p (tx_13_p), .tx_n (tx_13_n), .tx_out_clk (tx_out_clk_13), .tx_clk (tx_clk_13), .tx_charisk (tx_charisk_13), .tx_data (tx_data_13), + .tx_header (tx_header_13), .up_rstn (up_rstn), .up_clk (up_clk), .up_es_enb (up_es_enb_13), @@ -3346,6 +3528,8 @@ module util_adxcvr #( if (NUM_OF_LANES >= 15) begin util_adxcvr_xch #( .XCVR_TYPE (XCVR_TYPE), + .LINK_MODE (LINK_MODE), + .DATA_PATH_WIDTH (DATA_PATH_WIDTH), .CPLL_FBDIV (CPLL_FBDIV), .CPLL_FBDIV_4_5 (CPLL_FBDIV_4_5), .CPLL_CFG0 (CPLL_CFG0), @@ -3372,14 +3556,18 @@ module util_adxcvr #( .RXCDR_CFG3_GEN2 (RXCDR_CFG3_GEN2), .RXCDR_CFG3_GEN3 (RXCDR_CFG3_GEN3), .RXCDR_CFG3_GEN4 (RXCDR_CFG3_GEN4), + .RXDFE_KH_CFG2 (RXDFE_KH_CFG2), + .RXDFE_KH_CFG3 (RXDFE_KH_CFG3), .RX_WIDEMODE_CDR (RX_WIDEMODE_CDR), .RX_XMODE_SEL (RX_XMODE_SEL), .TXDRV_FREQBAND (TXDRV_FREQBAND), + .TXFE_CFG0 (TXFE_CFG0), .TXFE_CFG1 (TXFE_CFG1), .TXFE_CFG2 (TXFE_CFG2), .TXFE_CFG3 (TXFE_CFG3), .TXPI_CFG0 (TXPI_CFG0), .TXPI_CFG1 (TXPI_CFG1), + .TXSWBST_EN (TXSWBST_EN), .CH_HSPMUX (CH_HSPMUX), .PREIQ_FREQ_BST (PREIQ_FREQ_BST), .RXPI_CFG0 (RXPI_CFG0), @@ -3403,12 +3591,15 @@ module util_adxcvr #( .rx_notintable (rx_notintable_14), .rx_data (rx_data_14), .rx_calign (rx_calign_14), + .rx_header(rx_header_14), + .rx_block_sync(rx_block_sync_14), .tx_p (tx_14_p), .tx_n (tx_14_n), .tx_out_clk (tx_out_clk_14), .tx_clk (tx_clk_14), .tx_charisk (tx_charisk_14), .tx_data (tx_data_14), + .tx_header (tx_header_14), .up_rstn (up_rstn), .up_clk (up_clk), .up_es_enb (up_es_enb_14), @@ -3482,6 +3673,8 @@ module util_adxcvr #( if (NUM_OF_LANES >= 16) begin util_adxcvr_xch #( .XCVR_TYPE (XCVR_TYPE), + .LINK_MODE (LINK_MODE), + .DATA_PATH_WIDTH (DATA_PATH_WIDTH), .CPLL_FBDIV (CPLL_FBDIV), .CPLL_FBDIV_4_5 (CPLL_FBDIV_4_5), .CPLL_CFG0 (CPLL_CFG0), @@ -3508,14 +3701,18 @@ module util_adxcvr #( .RXCDR_CFG3_GEN2 (RXCDR_CFG3_GEN2), .RXCDR_CFG3_GEN3 (RXCDR_CFG3_GEN3), .RXCDR_CFG3_GEN4 (RXCDR_CFG3_GEN4), + .RXDFE_KH_CFG2 (RXDFE_KH_CFG2), + .RXDFE_KH_CFG3 (RXDFE_KH_CFG3), .RX_WIDEMODE_CDR (RX_WIDEMODE_CDR), .RX_XMODE_SEL (RX_XMODE_SEL), .TXDRV_FREQBAND (TXDRV_FREQBAND), + .TXFE_CFG0 (TXFE_CFG0), .TXFE_CFG1 (TXFE_CFG1), .TXFE_CFG2 (TXFE_CFG2), .TXFE_CFG3 (TXFE_CFG3), .TXPI_CFG0 (TXPI_CFG0), .TXPI_CFG1 (TXPI_CFG1), + .TXSWBST_EN (TXSWBST_EN), .CH_HSPMUX (CH_HSPMUX), .PREIQ_FREQ_BST (PREIQ_FREQ_BST), .RXPI_CFG0 (RXPI_CFG0), @@ -3539,12 +3736,15 @@ module util_adxcvr #( .rx_notintable (rx_notintable_15), .rx_data (rx_data_15), .rx_calign (rx_calign_15), + .rx_header(rx_header_15), + .rx_block_sync(rx_block_sync_15), .tx_p (tx_15_p), .tx_n (tx_15_n), .tx_out_clk (tx_out_clk_15), .tx_clk (tx_clk_15), .tx_charisk (tx_charisk_15), .tx_data (tx_data_15), + .tx_header (tx_header_15), .up_rstn (up_rstn), .up_clk (up_clk), .up_es_enb (up_es_enb_15), diff --git a/library/xilinx/util_adxcvr/util_adxcvr_ip.tcl b/library/xilinx/util_adxcvr/util_adxcvr_ip.tcl index 87a8fb743..33014c428 100644 --- a/library/xilinx/util_adxcvr/util_adxcvr_ip.tcl +++ b/library/xilinx/util_adxcvr/util_adxcvr_ip.tcl @@ -6,6 +6,7 @@ source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl adi_ip_create util_adxcvr adi_ip_files util_adxcvr [list \ "$ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl" \ + "$ad_hdl_dir/library/jesd204/jesd204_common/sync_header_align.v" \ "util_adxcvr_constr.xdc" \ "util_adxcvr_xcm.v" \ "util_adxcvr_xch.v" \ @@ -19,6 +20,30 @@ adi_ip_bd util_adxcvr "bd/bd.tcl" adi_ip_add_core_dependencies { \ analog.com:user:util_cdc:1.0 \ } +set cc [ipx::current_core] + +# Arrange GUI page layout +set page0 [ipgui::get_pagespec -name "Page 0" -component $cc] +# Link layer mode +set p [ipgui::get_guiparamspec -name "LINK_MODE" -component $cc] +ipgui::move_param -component $cc -order 0 $p -parent $page0 +set_property -dict [list \ + "display_name" "Link Layer mode" \ + "tooltip" "Link Layer mode" \ + "widget" "comboBox" \ +] $p + +set_property -dict [list \ + value_validation_type pairs \ + value_validation_pairs {64B66B 2 8B10B 1} \ +] [ipx::get_user_parameters $p -of_objects $cc] + +# Data width selection +set param [ipx::get_user_parameters DATA_PATH_WIDTH -of_objects $cc] +set_property -dict [list \ + enablement_tcl_expr {$LINK_MODE==1} \ + value_tcl_expr {expr $LINK_MODE*4} \ +] $param ipx::remove_all_bus_interface [ipx::current_core] @@ -231,6 +256,12 @@ for {set n 0} {$n < 16} {incr n} { ipx::add_port_map rxdata [ipx::get_bus_interfaces rx_${n} -of_objects [ipx::current_core]] set_property physical_name rx_data_${n} [ipx::get_port_maps rxdata -of_objects \ [ipx::get_bus_interfaces rx_${n} -of_objects [ipx::current_core]]] + ipx::add_port_map rxheader [ipx::get_bus_interfaces rx_${n} -of_objects [ipx::current_core]] + set_property physical_name rx_header_${n} [ipx::get_port_maps rxheader -of_objects \ + [ipx::get_bus_interfaces rx_${n} -of_objects [ipx::current_core]]] + ipx::add_port_map rxblock_sync [ipx::get_bus_interfaces rx_${n} -of_objects [ipx::current_core]] + set_property physical_name rx_block_sync_${n} [ipx::get_port_maps rxblock_sync -of_objects \ + [ipx::get_bus_interfaces rx_${n} -of_objects [ipx::current_core]]] ipx::add_bus_interface tx_${n} [ipx::current_core] set_property abstraction_type_vlnv xilinx.com:display_jesd204:jesd204_tx_bus_rtl:1.0 \ @@ -244,6 +275,9 @@ for {set n 0} {$n < 16} {incr n} { ipx::add_port_map txdata [ipx::get_bus_interfaces tx_${n} -of_objects [ipx::current_core]] set_property physical_name tx_data_${n} [ipx::get_port_maps txdata -of_objects \ [ipx::get_bus_interfaces tx_${n} -of_objects [ipx::current_core]]] + ipx::add_port_map txheader [ipx::get_bus_interfaces tx_${n} -of_objects [ipx::current_core]] + set_property physical_name tx_header_${n} [ipx::get_port_maps txheader -of_objects \ + [ipx::get_bus_interfaces tx_${n} -of_objects [ipx::current_core]]] } diff --git a/library/xilinx/util_adxcvr/util_adxcvr_xch.v b/library/xilinx/util_adxcvr/util_adxcvr_xch.v index 902254ab6..869ae1fab 100644 --- a/library/xilinx/util_adxcvr/util_adxcvr_xch.v +++ b/library/xilinx/util_adxcvr/util_adxcvr_xch.v @@ -41,6 +41,10 @@ module util_adxcvr_xch #( parameter integer XCVR_TYPE = 0, + parameter LINK_MODE = 1, // 2 - 64B/66B; 1 - 8B/10B + /* Only 4 is supported at the moment for 8b/10b and 8 for 64b */ + parameter DATA_PATH_WIDTH = LINK_MODE == 2 ? 8 : 4, + parameter integer CPLL_FBDIV = 2, parameter integer CPLL_FBDIV_4_5 = 5, parameter [15:0] CPLL_CFG0 = 16'b0000000111111010, @@ -75,14 +79,18 @@ module util_adxcvr_xch #( parameter [ 5:0] RXCDR_CFG3_GEN2 = 6'b011010, parameter [15:0] RXCDR_CFG3_GEN3 = 16'b0000000000010010, parameter [15:0] RXCDR_CFG3_GEN4 = 16'b0000000000100100, + parameter [15:0] RXDFE_KH_CFG2 = 16'h0200, + parameter [15:0] RXDFE_KH_CFG3 = 16'h4101, parameter [ 1:0] RX_WIDEMODE_CDR = 2'b00, parameter [ 0:0] RX_XMODE_SEL = 1'b1, parameter integer TXDRV_FREQBAND = 0, + parameter [15:0] TXFE_CFG0 = 16'b0000001111000010, parameter [15:0] TXFE_CFG1 = 16'b0110110000000000, parameter [15:0] TXFE_CFG2 = 16'b0110110000000000, parameter [15:0] TXFE_CFG3 = 16'b0110110000000000, parameter [15:0] TXPI_CFG0 = 16'b0000001100000000, parameter [15:0] TXPI_CFG1 = 16'b0001000000000000, + parameter integer TXSWBST_EN = 0, parameter integer RX_POLARITY = 0) ( // pll interface @@ -101,23 +109,26 @@ module util_adxcvr_xch #( input rx_p, input rx_n, - output rx_out_clk, - input rx_clk, - output [ 3:0] rx_charisk, - output [ 3:0] rx_disperr, - output [ 3:0] rx_notintable, - output [31:0] rx_data, - input rx_calign, + output rx_out_clk, + input rx_clk, + output [DATA_PATH_WIDTH-1:0] rx_charisk, + output [DATA_PATH_WIDTH-1:0] rx_disperr, + output [DATA_PATH_WIDTH-1:0] rx_notintable, + output [DATA_PATH_WIDTH*8-1:0] rx_data, + input rx_calign, + output [1:0] rx_header, + output rx_block_sync, // transmit output tx_p, output tx_n, - output tx_out_clk, - input tx_clk, - input [ 3:0] tx_charisk, - input [31:0] tx_data, + output tx_out_clk, + input tx_clk, + input [DATA_PATH_WIDTH-1:0] tx_charisk, + input [DATA_PATH_WIDTH*8-1:0] tx_data, + input [1:0] tx_header, // up interface @@ -831,7 +842,7 @@ module util_adxcvr_xch #( .TXUSERRDY (up_tx_user_ready), .TXUSRCLK (tx_clk), .TXUSRCLK2 (tx_clk)); - // Emulate PRBS lock + // Emulate PRBS lock assign rx_prbslocked = ~rx_prbserr_sticky; end endgenerate @@ -2506,6 +2517,66 @@ module util_adxcvr_xch #( generate if (XCVR_TYPE == GTYE4_TRANSCEIVERS) begin + + localparam ALIGN_COMMA_ENABLE = LINK_MODE[1] ? 10'b0000000000 : 10'b1111111111; + localparam ALIGN_MCOMMA_DET = LINK_MODE[1] ? "FALSE" : "TRUE"; + localparam ALIGN_PCOMMA_DET = LINK_MODE[1] ? "FALSE" : "TRUE"; + localparam CBCC_DATA_SOURCE_SEL = LINK_MODE[1] ? "ENCODED" : "DECODED"; + localparam DEC_MCOMMA_DETECT = LINK_MODE[1] ? "FALSE" : "TRUE"; + localparam DEC_PCOMMA_DETECT = LINK_MODE[1] ? "FALSE" : "TRUE"; + localparam RXBUF_EN = LINK_MODE[1] ? "FALSE" : "TRUE"; + localparam TXBUF_EN = LINK_MODE[1] ? "FALSE" : "TRUE"; + localparam RX_DATA_WIDTH = LINK_MODE[1] ? 64 : 40; + localparam TX_DATA_WIDTH = LINK_MODE[1] ? 64 : 40; + localparam GEARBOX_MODE = LINK_MODE[1] ? 5'b10001 : 5'b00000; + localparam GEARBOX_EN = LINK_MODE[1] ? "TRUE" : "FALSE"; + localparam RX_INT_DATAWIDTH = LINK_MODE[1] ? 2 : 1; + localparam TX_INT_DATAWIDTH = LINK_MODE[1] ? 2 : 1; + localparam RX8B10BEN = LINK_MODE[1] ? 0 : 1; + localparam TX8B10BEN = LINK_MODE[1] ? 0 : 1; + localparam TX_RXDETECT_CFG = LINK_MODE[1] ? 14'h032 : 14'b00000000110010; + localparam RXGBOX_FIFO_INIT_RD_ADDR = LINK_MODE[1] ? 3 : 4; + localparam RXBUF_THRESH_UNDFLW = LINK_MODE[1] ? 4 : 3; + localparam RX_EYESCAN_VS_RANGE = LINK_MODE[1] ? 2 : 0; + localparam TXPHDLY_CFG1 = LINK_MODE[1] ? 16'h000E : 16'h000F; + localparam TXPH_CFG = LINK_MODE[1] ? 16'h0723 : 16'h0323; + + wire [1:0] rx_header_s; + wire [127:0] rx_data_s; + wire [127:0] tx_data_s; + wire rx_bitslip_s; + + if (LINK_MODE[1]) begin + + reg [3:0] rx_bitslip_d = 'h0; + reg rx_bitslip_req_s_d = 1'b0; + always @(posedge rx_clk) begin + rx_bitslip_d <= {rx_bitslip_d,rx_bitslip_s}; + rx_bitslip_req_s_d <= rx_bitslip_req_s; + end + assign rx_bitslip_s = rx_bitslip_req_s & ~rx_bitslip_req_s_d; + + // Sync header alignment + sync_header_align i_sync_header_align ( + .clk(rx_clk), + .reset(~rx_rst_done_s), + .i_data({rx_header_s,rx_data_s[63:0]}), + .i_slip(rx_bitslip_req_s), + .i_slip_done(rx_bitslip_d[3]), + .o_data(rx_data), + .o_header(rx_header), + .o_block_sync(rx_block_sync) + ); + assign tx_data_s = {64'd0, tx_data}; + + end else begin + + assign {rx_data_open_s, rx_data} = rx_data_s; + assign rx_bitslip_s = 1'b0; + assign tx_data_s = {96'd0, tx_data}; + + end + GTYE4_CHANNEL #( .ACJTAG_DEBUG_MODE (1'b0), .ACJTAG_MODE (1'b0), @@ -2514,18 +2585,18 @@ module util_adxcvr_xch #( .ADAPT_CFG1 (16'b1111101100011100), .ADAPT_CFG2 (16'b0000000000000000), .ALIGN_COMMA_DOUBLE ("FALSE"), - .ALIGN_COMMA_ENABLE (10'b1111111111), + .ALIGN_COMMA_ENABLE (ALIGN_COMMA_ENABLE), .ALIGN_COMMA_WORD (1), - .ALIGN_MCOMMA_DET ("TRUE"), + .ALIGN_MCOMMA_DET (ALIGN_MCOMMA_DET), .ALIGN_MCOMMA_VALUE (10'b1010000011), - .ALIGN_PCOMMA_DET ("TRUE"), + .ALIGN_PCOMMA_DET (ALIGN_PCOMMA_DET), .ALIGN_PCOMMA_VALUE (10'b0101111100), .A_RXOSCALRESET (1'b0), .A_RXPROGDIVRESET (1'b0), .A_RXTERMINATION (1'b1), .A_TXDIFFCTRL (5'b01100), .A_TXPROGDIVRESET (1'b0), - .CBCC_DATA_SOURCE_SEL ("DECODED"), + .CBCC_DATA_SOURCE_SEL (CBCC_DATA_SOURCE_SEL), .CDR_SWAP_MODE_EN (1'b0), .CFOK_PWRSVE_EN (1'b1), .CHAN_BOND_KEEP_ALIGN ("FALSE"), @@ -2583,8 +2654,8 @@ module util_adxcvr_xch #( .CTLE3_OCAP_EXT_EN (1'b0), .DDI_CTRL (2'b00), .DDI_REALIGN_WAIT (15), - .DEC_MCOMMA_DETECT ("TRUE"), - .DEC_PCOMMA_DETECT ("TRUE"), + .DEC_MCOMMA_DETECT (DEC_MCOMMA_DETECT), + .DEC_PCOMMA_DETECT (DEC_PCOMMA_DETECT), .DEC_VALID_COMMA_ONLY ("FALSE"), .DELAY_ELEC (1'b0), .DMONITOR_CFG0 (10'b0000000000), @@ -2630,7 +2701,7 @@ module util_adxcvr_xch #( .FTS_DESKEW_SEQ_ENABLE (4'b1111), .FTS_LANE_DESKEW_CFG (4'b1111), .FTS_LANE_DESKEW_EN ("FALSE"), - .GEARBOX_MODE (5'b00000), + .GEARBOX_MODE (GEARBOX_MODE), .ISCAN_CK_PH_SEL2 (1'b0), .LOCAL_MASTER (1'b1), .LPBK_BIAS_CTRL (4), @@ -2681,14 +2752,14 @@ module util_adxcvr_xch #( .RXBUF_ADDR_MODE ("FAST"), .RXBUF_EIDLE_HI_CNT (4'b1000), .RXBUF_EIDLE_LO_CNT (4'b0000), - .RXBUF_EN ("TRUE"), + .RXBUF_EN (RXBUF_EN), .RXBUF_RESET_ON_CB_CHANGE ("TRUE"), .RXBUF_RESET_ON_COMMAALIGN ("FALSE"), .RXBUF_RESET_ON_EIDLE ("FALSE"), .RXBUF_RESET_ON_RATE_CHANGE ("TRUE"), .RXBUF_THRESH_OVFLW (57), .RXBUF_THRESH_OVRD ("TRUE"), - .RXBUF_THRESH_UNDFLW (3), + .RXBUF_THRESH_UNDFLW (RXBUF_THRESH_UNDFLW), .RXCDRFREQRESET_TIME (5'b00001), .RXCDRPHRESET_TIME (5'b00001), .RXCDR_CFG0 (16'b0000000000000011), @@ -2726,7 +2797,7 @@ module util_adxcvr_xch #( .RXCKCAL2_S_LOOP_RST_CFG (16'b0000000000000000), .RXCKCAL2_X_LOOP_RST_CFG (16'b0000000000000000), .RXDFELPMRESET_TIME (7'b0001111), - .RXDFELPM_KL_CFG0 (15'b000000000000000 ), + .RXDFELPM_KL_CFG0 (15'b000000000000000), .RXDFELPM_KL_CFG1 (16'b1010000010000010), .RXDFELPM_KL_CFG2 (16'b0000000100000000), .RXDFE_CFG0 (16'b0000101000000000), @@ -2764,8 +2835,8 @@ module util_adxcvr_xch #( .RXDFE_HF_CFG1 (16'b1000000000000010), .RXDFE_KH_CFG0 (16'b1000000000000000), .RXDFE_KH_CFG1 (16'b1111111000000000), - .RXDFE_KH_CFG2 (16'b0000001000000000), - .RXDFE_KH_CFG3 (16'b0100000100000001), + .RXDFE_KH_CFG2 (RXDFE_KH_CFG2), + .RXDFE_KH_CFG3 (RXDFE_KH_CFG3), .RXDFE_OS_CFG0 (16'b0010000000000000), .RXDFE_OS_CFG1 (16'b1000000000000000), .RXDFE_UT_CFG0 (16'b0000000000000000), @@ -2776,8 +2847,8 @@ module util_adxcvr_xch #( .RXDLY_CFG (16'b0000000000010000), .RXDLY_LCFG (16'b0000000000110000), .RXELECIDLE_CFG ("SIGCFG_4"), - .RXGBOX_FIFO_INIT_RD_ADDR (4), - .RXGEARBOX_EN ("FALSE"), + .RXGBOX_FIFO_INIT_RD_ADDR (RXGBOX_FIFO_INIT_RD_ADDR), + .RXGEARBOX_EN (GEARBOX_EN), .RXISCANRESET_TIME (5'b00001), .RXLPM_CFG (16'b0000000000000000), .RXLPM_GC_CFG (16'b1111100000000000), @@ -2796,7 +2867,7 @@ module util_adxcvr_xch #( .RXPHSLIP_CFG (16'b1001100100110011), .RXPH_MONITOR_SEL (5'b00000), .RXPI_CFG0 (RXPI_CFG0), - .RXPI_CFG1 (16'b0000000001010100), + .RXPI_CFG1 (RXPI_CFG1), .RXPMACLK_SEL ("DATA"), .RXPMARESET_TIME (5'b00011), .RXPRBS_ERR_LOOPBACK (1'b0), @@ -2820,7 +2891,7 @@ module util_adxcvr_xch #( .RX_CM_TRIM (10), .RX_CTLE_PWR_SAVING (1'b0), .RX_CTLE_RES_CTRL (4'b0000), - .RX_DATA_WIDTH (40), + .RX_DATA_WIDTH (RX_DATA_WIDTH), .RX_DDI_SEL (6'b000000), .RX_DEFER_RESET_BUF_EN ("TRUE"), .RX_DEGEN_CTRL (3'b100), @@ -2839,11 +2910,11 @@ module util_adxcvr_xch #( .RX_EN_SUM_RCAL_B (0), .RX_EYESCAN_VS_CODE (7'b0000000), .RX_EYESCAN_VS_NEG_DIR (1'b0), - .RX_EYESCAN_VS_RANGE (2'b00), + .RX_EYESCAN_VS_RANGE (RX_EYESCAN_VS_RANGE), .RX_EYESCAN_VS_UT_SIGN (1'b0), .RX_FABINT_USRCLK_FLOP (1'b0), .RX_I2V_FILTER_EN (1'b1), - .RX_INT_DATAWIDTH (1), + .RX_INT_DATAWIDTH (RX_INT_DATAWIDTH), .RX_PMA_POWER_SAVE (1'b0), .RX_PMA_RSV0 (16'b0000000000101111), .RX_PROGDIV_CFG (0.0), @@ -2888,23 +2959,23 @@ module util_adxcvr_xch #( .TRANS_TIME_RATE (8'b00001110), .TST_RSV0 (8'b00000000), .TST_RSV1 (8'b00000000), - .TXBUF_EN ("TRUE"), + .TXBUF_EN (TXBUF_EN), .TXBUF_RESET_ON_RATE_CHANGE ("TRUE"), .TXDLY_CFG (16'b1000000000010000), .TXDLY_LCFG (16'b0000000000110000), .TXDRV_FREQBAND (TXDRV_FREQBAND), - .TXFE_CFG0 (16'b0000001111000010), + .TXFE_CFG0 (TXFE_CFG0), .TXFE_CFG1 (TXFE_CFG1), .TXFE_CFG2 (TXFE_CFG2), .TXFE_CFG3 (TXFE_CFG3), .TXFIFO_ADDR_CFG ("LOW"), .TXGBOX_FIFO_INIT_RD_ADDR (4), - .TXGEARBOX_EN ("FALSE"), + .TXGEARBOX_EN (GEARBOX_EN), .TXOUT_DIV (TX_OUT_DIV), .TXPCSRESET_TIME (5'b00011), .TXPHDLY_CFG0 (16'b0110000001110000), - .TXPHDLY_CFG1 (16'b0000000000001111), - .TXPH_CFG (16'b0000001100100011), + .TXPHDLY_CFG1 (TXPHDLY_CFG1), + .TXPH_CFG (TXPH_CFG), .TXPH_CFG2 (16'b0000000000000000), .TXPH_MONITOR_SEL (5'b00000), .TXPI_CFG0 (TXPI_CFG0), @@ -2917,14 +2988,14 @@ module util_adxcvr_xch #( .TXPMARESET_TIME (5'b00011), .TXREFCLKDIV2_SEL (1'b0), .TXSWBST_BST (1), - .TXSWBST_EN (0), + .TXSWBST_EN (TXSWBST_EN), .TXSWBST_MAG (4), .TXSYNC_MULTILANE (1'b1), .TXSYNC_OVRD (1'b0), .TXSYNC_SKIP_DA (1'b0), .TX_CLK25_DIV (TX_CLK25_DIV), .TX_CLKMUX_EN (1'b1), - .TX_DATA_WIDTH (40), + .TX_DATA_WIDTH (TX_DATA_WIDTH), .TX_DCC_LOOP_RST_CFG (16'b0000000000000100), .TX_DEEMPH0 (6'b000000), .TX_DEEMPH1 (6'b000000), @@ -2937,7 +3008,7 @@ module util_adxcvr_xch #( .TX_FABINT_USRCLK_FLOP (1'b0), .TX_FIFO_BYP_EN (1'b0), .TX_IDLE_DATA_ZERO (1'b0), - .TX_INT_DATAWIDTH (1), + .TX_INT_DATAWIDTH (TX_INT_DATAWIDTH), .TX_LOOPBACK_DRIVE_HIZ ("FALSE"), .TX_MAINCURSOR_SEL (1'b0), .TX_MARGIN_FULL_0 (7'b1011000), @@ -2960,7 +3031,7 @@ module util_adxcvr_xch #( .TX_PROGCLK_SEL ("PREPI"), .TX_PROGDIV_CFG (0.0), .TX_PROGDIV_RATE (16'b0000000000000001), - .TX_RXDETECT_CFG (14'b00000000110010 ), + .TX_RXDETECT_CFG (TX_RXDETECT_CFG), .TX_RXDETECT_REF (5), .TX_SAMPLE_PERIOD (3'b111), .TX_SW_MEAS (2'b00), @@ -3050,7 +3121,7 @@ module util_adxcvr_xch #( .QPLL1FREQLOCK (1'b0), .QPLL1REFCLK (qpll1_ref_clk), .RESETOVRD (1'b0), - .RX8B10BEN (1'b1), + .RX8B10BEN (RX8B10BEN), .RXAFECFOKEN (1'b1), .RXBUFRESET (1'b0), .RXCDRFREQRESET (1'b0), @@ -3116,7 +3187,7 @@ module util_adxcvr_xch #( .RXDLYSRESET (1'b0), .RXELECIDLEMODE (2'b11), .RXEQTRAINING (1'b0), - .RXGEARBOXSLIP (1'b0), + .RXGEARBOXSLIP (rx_bitslip_s), .RXLATCLK (1'b0), .RXLPMEN (up_rx_lpm_dfe_n), .RXLPMGCHOLD (1'b0), @@ -3163,14 +3234,14 @@ module util_adxcvr_xch #( .SIGVALIDCLK (1'b0), .TSTIN (20'b00000000000000000000), .TX8B10BBYPASS (1'b0), - .TX8B10BEN (1'b1), + .TX8B10BEN (TX8B10BEN), .TXCOMINIT (1'b0), .TXCOMSAS (1'b0), .TXCOMWAKE (1'b0), .TXCTRL0 (16'b0000000000000000), .TXCTRL1 (16'b0000000000000000), .TXCTRL2 ({4'd0, tx_charisk}), - .TXDATA ({96'd0, tx_data}), + .TXDATA (tx_data_s), .TXDATAEXTENDRSVD (8'b00000000), .TXDCCFORCESTART (1'b0), .TXDCCRESET (1'b0), @@ -3184,7 +3255,7 @@ module util_adxcvr_xch #( .TXDLYSRESET (1'b0), .TXDLYUPDOWN (1'b0), .TXELECIDLE (1'b0), - .TXHEADER (5'b00000), + .TXHEADER ({4'b0,tx_header}), .TXINHIBIT (1'b0), .TXLATCLK (1'b0), .TXLFPSTRESET (1'b0), @@ -3280,13 +3351,13 @@ module util_adxcvr_xch #( .RXCTRL1 ({rx_disperr_open_s, rx_disperr}), .RXCTRL2 (), .RXCTRL3 ({rx_notintable_open_s, rx_notintable}), - .RXDATA ({rx_data_open_s, rx_data}), + .RXDATA (rx_data_s), .RXDATAEXTENDRSVD (), .RXDATAVALID (), .RXDLYSRESETDONE (), .RXELECIDLE (), - .RXHEADER (), - .RXHEADERVALID (), + .RXHEADER (rx_header_s), + .RXHEADERVALID (rx_headervalid_s), .RXLFPSTRESETDET (), .RXLFPSU2LPEXITDET (), .RXLFPSU3WAKEDET (),