axi_dmac: src_fifo_inf: Simplify data path
Improves timing a bit Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>main
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f9ca4fb8be
commit
cb630e36a9
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@ -90,6 +90,14 @@ begin
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end
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end
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always @(posedge clk)
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begin
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if (en) begin
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buffer <= din;
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buffer_sync <= sync;
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end
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end
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always @(posedge clk)
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begin
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if (resetn == 1'b0) begin
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@ -98,8 +106,6 @@ begin
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end else begin
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if (enable) begin
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if (en) begin
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buffer <= din;
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buffer_sync <= sync;
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valid <= 1'b1;
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end else if (ready) begin
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valid <= 1'b0;
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