diff --git a/projects/ad4630_fmc/zed/README.md b/projects/ad4630_fmc/zed/README.md
index 417c1f213..ee482e503 100644
--- a/projects/ad4630_fmc/zed/README.md
+++ b/projects/ad4630_fmc/zed/README.md
@@ -1,14 +1,13 @@
 
-# EVAL-AD463x_FMCZ HDL reference design
+# EVAL-AD463X_FMCZ HDL reference design
 
 ## Building the design
 
 The design supports almost all the digital interface modes of AD4630-24, a new
 bit stream should be generated each time when the targeted configuration changes.
-**NOTE:** Interleaved mode (SPI hase one MISO lines) is supported only in SPI clock mode.
 
 Default configuration: generic SPI mode for clocking, 2 lanes per channel, SDR 
-data capture and second capture zone is used to pull out data from the converter. 
+data capture and capture zone 2. 
 
 ### Building attributes
 
@@ -19,9 +18,9 @@ data capture and second capture zone is used to pull out data from the converter
 |  CAPTURE_ZONE   |  1 - negedge of BUSY / 2 - next posedge of CNV    |
 |  DDR_EN         |  0 - MISO runs on SDR / 1 - MISO runs on DDR      |
 
-**Example:** make NUM_OF_SDI=2 CAPTURE_ZONE=2
+**Example:** make CLK_MODE=1 NUM_OF_SDI=2 CAPTURE_ZONE=2 DDR_EN=0
 
-## Documantation
+## Documentation
 
-https://wiki.analog.com/resources/eval/user-guides/ad436x/hdl
+https://wiki.analog.com/resources/eval/user-guides/ad463x/hdl