docs: Add ad7134_fmc doc (#1246)
* docs: Add ad7134_fmc doc. Update by guidelines Signed-off-by: laurent-19 <laurentiu.popa@analog.com> --------- Signed-off-by: laurent-19 <laurentiu.popa@analog.com>main
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@ -22,6 +22,7 @@ HDL Reference Designs
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AD469X-FMC <projects/ad469x_fmc/index>
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AD469X-FMC <projects/ad469x_fmc/index>
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AD5766-SDZ <projects/ad5766_sdz/index>
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AD5766-SDZ <projects/ad5766_sdz/index>
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AD7134-FMC <projects/ad7134_fmc/index>
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AD719X-ASDZ <projects/ad719x_asdz/index>
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AD719X-ASDZ <projects/ad719x_asdz/index>
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AD738X-FMC <projects/ad738x_fmc/index>
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AD738X-FMC <projects/ad738x_fmc/index>
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AD7616-SDZ <projects/ad7616_sdz/index>
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AD7616-SDZ <projects/ad7616_sdz/index>
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.. _ad7134_fmc:
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AD7134-FMC HDL project
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===============================================================================
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Overview
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-------------------------------------------------------------------------------
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The :adi:`AD7134` is a quad channel, low noise, simultaneous sampling,
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precision analog-to-digital converter (ADC), based on the continuous time
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sigma-delta (CTSD) modulation scheme. The CTSD architecture inherently rejects
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signals around the ADC aliasing frequency band, giving the device its inherent
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antialiasing capability, and removes the need for a complex external
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antialiasing filter.
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The device has four independent converter channels in parallel, each with a
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CTSD modulator and a digital decimation and filtering path. The bandwidth of
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each ADC channel ranges from dc to 391.5 kHz, making the device an ideal
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candidate for universal precision data acquisition solutions supporting a
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breadth of sensor types, from temperature and pressure to vibration and shock.
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It supports a wide range of ODR frequencies, from 0.01 kSPS to 1496 kSPS
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with less than 0.01 SPS adjustment resolution, allowing the user to granularly
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vary sampling speed to achieve coherent sampling. The adc offers three main
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digital filter profile options: a wideband low ripple filter (2.5 kSPS to 374
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kSPS), a fast responding sinc3 filter (0.01 kSPS to 1496 kSPS), and a balanced
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sinc6 filter with an ODR range 2.5 kSPS to 1.496 MSPS.
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The :adi:`AD7134` supports two device configuration schemes: serial peripheral
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interface (SPI) and hardware pin configuration (pin control mode). The SPI
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control mode offers access to all the features and configuration options
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available on the chip. Pin control mode offers the benefit of simplifying the
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device configuration, enabling the device to operate autonomously after power
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-up operating in a standalone mode. In addition to the optional SPI, it has a
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flexible and independent data interface for transmitting the ADC output data.
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The EVAL-AD7134FMCZ evaluation kit features the AD7134 24-bit, 4-channel,
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simultaneous sampling adc. Two on-board AD7134 ADCs are included to
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demonstrate multidevice simultaneous sampling. The HDL reference design
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provides all the interfaces necessary to interact with the device using a
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Xilinx FPGA development board.
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Supported boards
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-------------------------------------------------------------------------------
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- :adi:`EVAL-AD7134FMCZ <EVAL-AD7134FMCZ>`
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Supported devices
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-------------------------------------------------------------------------------
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- :adi:`AD7134`
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Supported carriers
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-------------------------------------------------------------------------------
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- :xilinx:`ZedBoard <products/boards-and-kits/1-8dyf-11.html>` on FMC slot *
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.. admonition:: Legend
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:class: note
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``*`` FMC extender needed for connecting the EVAL board
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Block design
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-------------------------------------------------------------------------------
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The reference design uses the SPI Engine Framework to interface with the two
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AD7134 ADCs. It only supports the slave mode for both devices with both DCLK
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and ODR generated by the FPGA. Each device sends data on 4 of the 8 DIN bits.
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Block diagram
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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The data path and clock domains are depicted in the below diagrams:
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.. image:: ad713x_hdl.svg
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:width: 800
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:align: center
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:alt: AD7134-FMC/ZED block diagram
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Jumper setup
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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================== ========= ===================================
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Jumper/Solder link Position Description
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================== ========= ===================================
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JP14 Mounted DEC0/DCLKIO (Device 1) [DCLK Input]
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JP15 Mounted DEC0/DCLKIO (Device 2) [DCLK Input]
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JP16 Mounted MODE (Device 1) [Slave Mode]
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JP17 Mounted MODE (Device 2) [Slave Mode]
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================== ========= ===================================
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CPU/Memory interconnects addresses
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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The addresses are dependent on the architecture of the FPGA, having an offset
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added to the base address from HDL(see more at :ref:`architecture`).
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======================== ===========
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Instance Address
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======================== ===========
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dual_ad7134_axi_regmap 0x44A0_0000
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axi_ad7134_dma 0x44A3_0000
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axi_sdp_clkgen 0x44A4_0000
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odr_generator 0x44B0_0000
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axi_ad7134_clkgen 0x44B1_0000
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======================== ===========
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SPI connections
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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.. list-table::
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:widths: 25 25 25 25
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:header-rows: 1
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* - SPI type
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- SPI manager instance
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- SPI subordinate
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- CS
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* - PS
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- SPI 0
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- AD7134
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- 0
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* - PS
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- SPI 0
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- AD7134
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- 1
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GPIOs
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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The Software GPIO number is calculated as follows:
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- Zynq-7000: if PS7 is used, then offset is 54
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.. list-table::
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:widths: 25 25 25 25
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:header-rows: 2
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* - GPIO signal
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- Direction
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- HDL GPIO EMIO
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- Software GPIO
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* -
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- (from FPGA view)
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-
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- Zynq-7000
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* - ad713x_dclkmode
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- INOUT
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- 49
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- 103
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* - ad713x_pinbspi
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- INOUT
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- 48
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- 102
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* - ad713x_dclkio[1:0]
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- INOUT
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- 47:46
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- 101:100
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* - ad713x_gpio[7:0]
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- INOUT
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- 45:38
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- 99:92
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* - ad713x_mode[1:0]
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- INOUT
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- 37:36
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- 91:90
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* - ad713x_pdn[1:0]
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- INOUT
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- 35:34
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- 89:88
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* - ad713x_resetn[1:0]
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- INOUT
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- 33:32
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- 87:86
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Interrupts
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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Below are the Programmable Logic interrupts used in this project.
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=============== === ========== ===========
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Instance name HDL Linux Zynq Actual Zynq
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=============== === ========== ===========
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axi_ad7134_dma 13 57 89
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dual_ad7134 12 56 88
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=============== === ========== ===========
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Building the HDL project
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-------------------------------------------------------------------------------
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The design is built upon ADI's generic HDL reference design framework.
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ADI does not distribute the bit/elf files of these projects so they
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must be built from the sources available :git-hdl:`here </>`. To get
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the source you must
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`clone <https://git-scm.com/book/en/v2/Git-Basics-Getting-a-Git-Repository>`__
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the HDL repository, and then build the project as follows:.
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**Linux/Cygwin/WSL**
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.. code-block::
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:linenos:
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user@analog:~$ cd hdl/projects/ad7134_fmc/zed
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user@analog:~/hdl/projects/ad7134_fmc/zed$ make
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A more comprehensive build guide can be found in the :ref:`build_hdl`
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user guide.
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Resources
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-------------------------------------------------------------------------------
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Hardware related
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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- Product datasheet: :adi:`AD7134`
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- `UG-1599: EVAL-AD7134FMCZ Board User Guide <https://www.analog.com/media/en/technical-documentation/user-guides/eval-ad7134fmcz-ug-1599.pdf>`__
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HDL related
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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- :git-hdl:`AD7134-FMC HDL project source code <projects/ad7134_fmc>`
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.. list-table::
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:widths: 30 35 35
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:header-rows: 1
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* - IP name
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- Source code link
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- Documentation link
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* - AXI_CLKGEN
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- :git-hdl:`library/axi_clkgen`
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- :dokuwiki:`[Wiki] <resources/fpga/docs/axi_clkgen>`
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* - AXI_DMAC
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- :git-hdl:`library/axi_dmac`
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- :ref:`here <axi_dmac>`
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* - AXI_HDMI_TX
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- :git-hdl:`library/axi_hdmi_tx`
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- :dokuwiki:`[Wiki] <resources/fpga/docs/axi_hdmi_tx>`
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* - AXI_I2S_ADI
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- :git-hdl:`library/axi_i2s_adi`
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- ---
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* - AXI_PWM_GEN
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- :git-hdl:`library/axi_pwm_gen`
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- :dokuwiki:`[Wiki] <resources/fpga/docs/axi_pwm_gen>`
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* - AXI_SDDIF_TX
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- :git-hdl:`library/axi_spdif_tx`
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- ---
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* - AXI_SYSID
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- :git-hdl:`library/axi_sysid`
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- :dokuwiki:`[Wiki] <resources/fpga/docs/axi_sysid>`
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* - AXI_SPI_ENGINE
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- :git-hdl:`library/spi_engine/axi_spi_engine`
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- :ref:`here <spi_engine axi>`
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* - SPI_ENGINE_EXECUTION
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- :git-hdl:`library/spi_engine/spi_engine_execution`
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- :ref:`here <spi_engine execution>`
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* - SPI_ENGINE_INTERCONNECT
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- :git-hdl:`library/spi_engine/spi_engine_interconnect`
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- :ref:`here <spi_engine interconnect>`
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* - SPI_ENGINE_OFFLOAD
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- :git-hdl:`library/spi_engine/spi_engine_offload`
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- :ref:`here <spi_engine offload>`
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* - AXI_SYSID_ROM
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- :git-hdl:`library/sysid_rom`
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- :dokuwiki:`[Wiki] <resources/fpga/docs/axi_sysid>`
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* - UTIL_I2C_MIXER
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- :git-hdl:`library/util_i2c_mixer`
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- :ref:`SPI Engine Framework documentation <spi_engine>`
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Software related
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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- :git-no-os:`AD7134-FMC No-OS project source code <projects/ad713x_fmcz>`
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- :git-no-os:`AD4134/AD7134 No-OS Driver source code <drivers/adc/ad713x>`
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- :dokuwiki:`AD4134/AD7134 No-OS Driver documentation <resources/tools-software/uc-drivers/ad713x>`
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- :dokuwiki:`How to build No-OS <resources/no-os/build>`
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.. include:: ../common/more_information.rst
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.. include:: ../common/support.rst
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