From cead3aaf866ba4c03f611856181868d53c5bc80b Mon Sep 17 00:00:00 2001 From: Adrian Costina Date: Mon, 22 Sep 2014 11:09:53 -0400 Subject: [PATCH 01/42] ultrasound: disconnected ADN4670 chips from SPI lines. Connected everything to ground so that the the clock selected is 0 and all outputs are enabled --- projects/usdrx1/common/usdrx1_bd.tcl | 70 ++++++++++++++-------------- projects/usdrx1/common/usdrx1_spi.v | 14 +----- projects/usdrx1/zc706/system_top.v | 31 ++++++------ 3 files changed, 51 insertions(+), 64 deletions(-) diff --git a/projects/usdrx1/common/usdrx1_bd.tcl b/projects/usdrx1/common/usdrx1_bd.tcl index edc9d01f6..ad8654d77 100644 --- a/projects/usdrx1/common/usdrx1_bd.tcl +++ b/projects/usdrx1/common/usdrx1_bd.tcl @@ -1,8 +1,8 @@ # usdrx1 -set spi_csn_i [create_bd_port -dir I -from 10 -to 0 spi_csn_i] -set spi_csn_o [create_bd_port -dir O -from 10 -to 0 spi_csn_o] +set spi_csn_i [create_bd_port -dir I -from 4 -to 0 spi_csn_i] +set spi_csn_o [create_bd_port -dir O -from 4 -to 0 spi_csn_o] set spi_clk_i [create_bd_port -dir I spi_clk_i] set spi_clk_o [create_bd_port -dir O spi_clk_o] set spi_sdo_i [create_bd_port -dir I spi_sdo_i] @@ -15,8 +15,6 @@ set rx_sysref [create_bd_port -dir O rx_sysref] set rx_data_p [create_bd_port -dir I -from 7 -to 0 rx_data_p] set rx_data_n [create_bd_port -dir I -from 7 -to 0 rx_data_n] -#set mlo_clk [create_bd_port -dir O mlo_clk] - set gt_rx_data [create_bd_port -dir O -from 255 -to 0 gt_rx_data] set gt_rx_data_0 [create_bd_port -dir I -from 63 -to 0 gt_rx_data_0] set gt_rx_data_1 [create_bd_port -dir I -from 63 -to 0 gt_rx_data_1] @@ -94,8 +92,8 @@ set_property -dict [list CONFIG.NUM_MI {1}] $axi_usdrx1_dma_interconnect set axi_usdrx1_spi [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_quad_spi:3.1 axi_usdrx1_spi] set_property -dict [list CONFIG.C_USE_STARTUP {0}] $axi_usdrx1_spi -set_property -dict [list CONFIG.C_NUM_SS_BITS {11}] $axi_usdrx1_spi -set_property -dict [list CONFIG.C_SCK_RATIO {16}] $axi_usdrx1_spi +set_property -dict [list CONFIG.C_NUM_SS_BITS {5}] $axi_usdrx1_spi +set_property -dict [list CONFIG.C_SCK_RATIO {8}] $axi_usdrx1_spi # additions to default configuration @@ -124,25 +122,25 @@ connect_bd_net -net axi_spi_1_sdo_i [get_bd_ports spi_sdo_i] [get_bd_pins axi_u connect_bd_net -net axi_spi_1_sdo_o [get_bd_ports spi_sdo_o] [get_bd_pins axi_usdrx1_spi/io0_o] connect_bd_net -net axi_spi_1_sdi_i [get_bd_ports spi_sdi_i] [get_bd_pins axi_usdrx1_spi/io1_i] -connect_bd_net -net sys_100m_clk [get_bd_pins axi_usdrx1_spi/ext_spi_clk] -connect_bd_net -net axi_spi_1_irq [get_bd_pins axi_usdrx1_spi/ip2intc_irpt] [get_bd_pins sys_concat_intc/In3] +connect_bd_net -net sys_100m_clk [get_bd_pins axi_usdrx1_spi/ext_spi_clk] +connect_bd_net -net axi_spi_1_irq [get_bd_pins axi_usdrx1_spi/ip2intc_irpt] [get_bd_pins sys_concat_intc/In3] # connections (gt) -connect_bd_net -net axi_usdrx1_gt_ref_clk_c [get_bd_pins axi_usdrx1_gt/ref_clk_c] [get_bd_ports rx_ref_clk] -connect_bd_net -net axi_usdrx1_gt_rx_data_p [get_bd_pins axi_usdrx1_gt/rx_data_p] [get_bd_ports rx_data_p] -connect_bd_net -net axi_usdrx1_gt_rx_data_n [get_bd_pins axi_usdrx1_gt/rx_data_n] [get_bd_ports rx_data_n] -connect_bd_net -net axi_usdrx1_gt_rx_sync [get_bd_pins axi_usdrx1_gt/rx_sync] [get_bd_ports rx_sync] -connect_bd_net -net axi_usdrx1_gt_rx_sysref [get_bd_pins axi_usdrx1_gt/rx_sysref] [get_bd_ports rx_sysref] +connect_bd_net -net axi_usdrx1_gt_ref_clk_c [get_bd_pins axi_usdrx1_gt/ref_clk_c] [get_bd_ports rx_ref_clk] +connect_bd_net -net axi_usdrx1_gt_rx_data_p [get_bd_pins axi_usdrx1_gt/rx_data_p] [get_bd_ports rx_data_p] +connect_bd_net -net axi_usdrx1_gt_rx_data_n [get_bd_pins axi_usdrx1_gt/rx_data_n] [get_bd_ports rx_data_n] +connect_bd_net -net axi_usdrx1_gt_rx_sync [get_bd_pins axi_usdrx1_gt/rx_sync] [get_bd_ports rx_sync] +connect_bd_net -net axi_usdrx1_gt_rx_sysref [get_bd_pins axi_usdrx1_gt/rx_sysref] [get_bd_ports rx_sysref] # connections (adc) connect_bd_net -net axi_usdrx1_gt_rx_clk [get_bd_pins axi_usdrx1_gt/rx_clk_g] connect_bd_net -net axi_usdrx1_gt_rx_clk [get_bd_pins axi_usdrx1_gt/rx_clk] -connect_bd_net -net axi_usdrx1_gt_rx_clk [get_bd_pins axi_ad9671_core_0/rx_clk] -connect_bd_net -net axi_usdrx1_gt_rx_clk [get_bd_pins axi_ad9671_core_1/rx_clk] -connect_bd_net -net axi_usdrx1_gt_rx_clk [get_bd_pins axi_ad9671_core_2/rx_clk] -connect_bd_net -net axi_usdrx1_gt_rx_clk [get_bd_pins axi_ad9671_core_3/rx_clk] +connect_bd_net -net axi_usdrx1_gt_rx_clk [get_bd_pins axi_ad9671_core_0/rx_clk] +connect_bd_net -net axi_usdrx1_gt_rx_clk [get_bd_pins axi_ad9671_core_1/rx_clk] +connect_bd_net -net axi_usdrx1_gt_rx_clk [get_bd_pins axi_ad9671_core_2/rx_clk] +connect_bd_net -net axi_usdrx1_gt_rx_clk [get_bd_pins axi_ad9671_core_3/rx_clk] connect_bd_net -net axi_usdrx1_gt_rx_clk [get_bd_pins axi_usdrx1_jesd/rx_core_clk] connect_bd_net -net axi_usdrx1_gt_rx_rst [get_bd_pins axi_usdrx1_gt/rx_rst] [get_bd_pins axi_usdrx1_jesd/rx_reset] @@ -181,7 +179,7 @@ connect_bd_net -net axi_ad9671_core_adc_dovf_3 [get_bd_pins axi_ad9671_core connect_bd_net -net axi_ad9671_dma_wr_en [get_bd_pins axi_usdrx1_dma/fifo_wr_en] [get_bd_ports adc_wr_en] connect_bd_net -net axi_ad9671_dma_adc_data [get_bd_pins axi_usdrx1_dma/fifo_wr_din] [get_bd_ports adc_data] connect_bd_net -net axi_ad9671_dma_adc_dovf [get_bd_pins axi_usdrx1_dma/fifo_wr_overflow] [get_bd_ports adc_dovf] -connect_bd_net -net axi_usdrx1_dma_irq [get_bd_pins axi_usdrx1_dma/irq] [get_bd_pins sys_concat_intc/In2] +connect_bd_net -net axi_usdrx1_dma_irq [get_bd_pins axi_usdrx1_dma/irq] [get_bd_pins sys_concat_intc/In2] # interconnect (cpu) @@ -201,14 +199,14 @@ connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M11_ACLK] $sy connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M12_ACLK] $sys_100m_clk_source connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M13_ACLK] $sys_100m_clk_source connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M14_ACLK] $sys_100m_clk_source -connect_bd_net -net sys_100m_clk [get_bd_pins axi_usdrx1_gt/s_axi_aclk] -connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9671_core_0/s_axi_aclk] -connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9671_core_1/s_axi_aclk] -connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9671_core_2/s_axi_aclk] -connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9671_core_3/s_axi_aclk] -connect_bd_net -net sys_100m_clk [get_bd_pins axi_usdrx1_jesd/s_axi_aclk] -connect_bd_net -net sys_100m_clk [get_bd_pins axi_usdrx1_dma/s_axi_aclk] -connect_bd_net -net sys_100m_clk [get_bd_pins axi_usdrx1_spi/s_axi_aclk] +connect_bd_net -net sys_100m_clk [get_bd_pins axi_usdrx1_gt/s_axi_aclk] +connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9671_core_0/s_axi_aclk] +connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9671_core_1/s_axi_aclk] +connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9671_core_2/s_axi_aclk] +connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9671_core_3/s_axi_aclk] +connect_bd_net -net sys_100m_clk [get_bd_pins axi_usdrx1_jesd/s_axi_aclk] +connect_bd_net -net sys_100m_clk [get_bd_pins axi_usdrx1_dma/s_axi_aclk] +connect_bd_net -net sys_100m_clk [get_bd_pins axi_usdrx1_spi/s_axi_aclk] connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M07_ARESETN] $sys_100m_resetn_source connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M08_ARESETN] $sys_100m_resetn_source connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M09_ARESETN] $sys_100m_resetn_source @@ -217,14 +215,14 @@ connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M11_ARESET connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M12_ARESETN] $sys_100m_resetn_source connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M13_ARESETN] $sys_100m_resetn_source connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M14_ARESETN] $sys_100m_resetn_source -connect_bd_net -net sys_100m_resetn [get_bd_pins axi_usdrx1_gt/s_axi_aresetn] -connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9671_core_0/s_axi_aresetn] -connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9671_core_1/s_axi_aresetn] -connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9671_core_2/s_axi_aresetn] -connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9671_core_3/s_axi_aresetn] -connect_bd_net -net sys_100m_resetn [get_bd_pins axi_usdrx1_jesd/s_axi_aresetn] -connect_bd_net -net sys_100m_resetn [get_bd_pins axi_usdrx1_dma/s_axi_aresetn] -connect_bd_net -net sys_100m_resetn [get_bd_pins axi_usdrx1_spi/s_axi_aresetn] +connect_bd_net -net sys_100m_resetn [get_bd_pins axi_usdrx1_gt/s_axi_aresetn] +connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9671_core_0/s_axi_aresetn] +connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9671_core_1/s_axi_aresetn] +connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9671_core_2/s_axi_aresetn] +connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9671_core_3/s_axi_aresetn] +connect_bd_net -net sys_100m_resetn [get_bd_pins axi_usdrx1_jesd/s_axi_aresetn] +connect_bd_net -net sys_100m_resetn [get_bd_pins axi_usdrx1_dma/s_axi_aresetn] +connect_bd_net -net sys_100m_resetn [get_bd_pins axi_usdrx1_spi/s_axi_aresetn] # interconnect (gt es) @@ -250,7 +248,7 @@ connect_bd_net -net sys_fmc_dma_clk $sys_fmc_dma_clk_source connect_bd_net -net sys_fmc_dma_resetn $sys_fmc_dma_resetn_source connect_bd_intf_net -intf_net axi_usdrx1_dma_interconnect_m00_axi [get_bd_intf_pins axi_usdrx1_dma_interconnect/M00_AXI] [get_bd_intf_pins sys_ps7/S_AXI_HP2] -connect_bd_intf_net -intf_net axi_usdrx1_dma_interconnect_s00_axi [get_bd_intf_pins axi_usdrx1_dma_interconnect/S00_AXI] [get_bd_intf_pins axi_usdrx1_dma/m_dest_axi] +connect_bd_intf_net -intf_net axi_usdrx1_dma_interconnect_s00_axi [get_bd_intf_pins axi_usdrx1_dma_interconnect/S00_AXI] [get_bd_intf_pins axi_usdrx1_dma/m_dest_axi] connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_usdrx1_dma_interconnect/ACLK] $sys_fmc_dma_clk_source connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_usdrx1_dma_interconnect/S00_ACLK] $sys_fmc_dma_clk_source connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_usdrx1_dma_interconnect/M00_ACLK] $sys_fmc_dma_clk_source @@ -259,7 +257,7 @@ connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_usdrx1_dma/m_dest_axi_aclk] connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_usdrx1_dma_interconnect/ARESETN] $sys_fmc_dma_resetn_source connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_usdrx1_dma_interconnect/S00_ARESETN] $sys_fmc_dma_resetn_source connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_usdrx1_dma_interconnect/M00_ARESETN] $sys_fmc_dma_resetn_source -connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_usdrx1_dma/m_dest_axi_aresetn] +connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_usdrx1_dma/m_dest_axi_aresetn] # ila diff --git a/projects/usdrx1/common/usdrx1_spi.v b/projects/usdrx1/common/usdrx1_spi.v index beed9891a..d4d3525f7 100644 --- a/projects/usdrx1/common/usdrx1_spi.v +++ b/projects/usdrx1/common/usdrx1_spi.v @@ -39,20 +39,17 @@ module usdrx1_spi ( - spi_fout_csn, spi_afe_csn, spi_clk_csn, spi_clk, spi_mosi, spi_miso, - spi_fout_sdio, spi_afe_sdio, spi_clk_sdio); // 4 wire - input [ 5:0] spi_fout_csn; input [ 3:0] spi_afe_csn; input spi_clk_csn; input spi_clk; @@ -61,7 +58,6 @@ module usdrx1_spi ( // 3 wire - inout spi_fout_sdio; inout spi_afe_sdio; inout spi_clk_sdio; @@ -73,16 +69,14 @@ module usdrx1_spi ( // internal signals - wire [ 2:0] spi_csn_3_s; + wire [ 1:0] spi_csn_3_s; wire spi_csn_s; wire spi_enable_s; - wire spi_fout_miso_s; wire spi_afe_miso_s; wire spi_clk_miso_s; // check on rising edge and change on falling edge - assign spi_csn_3_s[2] = & spi_fout_csn; assign spi_csn_3_s[1] = & spi_afe_csn; assign spi_csn_3_s[0] = spi_clk_csn; assign spi_csn_s = & spi_csn_3_s; @@ -111,15 +105,11 @@ module usdrx1_spi ( end end - assign spi_miso = ((spi_fout_miso_s & ~spi_csn_3_s[2]) | - (spi_afe_miso_s & ~spi_csn_3_s[1]) | + assign spi_miso = ((spi_afe_miso_s & ~spi_csn_3_s[1]) | (spi_clk_miso_s & ~spi_csn_3_s[0])); // io buffers - assign spi_fout_miso_s = spi_fout_sdio; - assign spi_fout_sdio = (spi_enable_s == 1'b1) ? 1'bz : spi_mosi; - assign spi_afe_miso_s = spi_afe_sdio; assign spi_afe_sdio = (spi_enable_s == 1'b1) ? 1'bz : spi_mosi; diff --git a/projects/usdrx1/zc706/system_top.v b/projects/usdrx1/zc706/system_top.v index 410d3a0cd..758798222 100644 --- a/projects/usdrx1/zc706/system_top.v +++ b/projects/usdrx1/zc706/system_top.v @@ -1,9 +1,9 @@ // *************************************************************************** // *************************************************************************** // Copyright 2011(c) Analog Devices, Inc. -// +// // All rights reserved. -// +// // Redistribution and use in source and binary forms, with or without modification, // are permitted provided that the following conditions are met: // - Redistributions of source code must retain the above copyright @@ -21,16 +21,16 @@ // patent holders to use this software. // - Use of the software either in source or binary form, must be run // on or directly connected to an Analog Devices Inc. component. -// +// // THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, // INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A // PARTICULAR PURPOSE ARE DISCLAIMED. // // IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, // EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY -// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR // BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, -// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF // THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // *************************************************************************** // *************************************************************************** @@ -171,7 +171,7 @@ module system_top ( output spi_fout_enb_sysref; output spi_fout_enb_trig; output spi_fout_clk; - inout spi_fout_sdio; + output spi_fout_sdio; output [ 3:0] spi_afe_csn; output spi_afe_clk; inout spi_afe_sdio; @@ -199,7 +199,7 @@ module system_top ( // internal signals - wire [10:0] spi_csn; + wire [ 4:0] spi_csn; wire spi_clk; wire spi_mosi; wire spi_miso; @@ -236,26 +236,25 @@ module system_top ( // spi assignments - assign spi_fout_enb_clk = ~spi_csn[10:10]; - assign spi_fout_enb_mlo = ~spi_csn[ 9: 9]; - assign spi_fout_enb_rst = ~spi_csn[ 8: 8]; - assign spi_fout_enb_sync = ~spi_csn[ 7: 7]; - assign spi_fout_enb_sysref = ~spi_csn[ 6: 6]; - assign spi_fout_enb_trig = ~spi_csn[ 5: 5]; + assign spi_fout_enb_clk = 1'b0; + assign spi_fout_enb_mlo = 1'b0; + assign spi_fout_enb_rst = 1'b0; + assign spi_fout_enb_sync = 1'b0; + assign spi_fout_enb_sysref = 1'b0; + assign spi_fout_enb_trig = 1'b0; + assign spi_fout_sdio = 1'b0; assign spi_afe_csn = spi_csn[ 4: 1]; assign spi_clk_csn = spi_csn[ 0: 0]; - assign spi_fout_clk = spi_clk; + assign spi_fout_clk = 1'b0; assign spi_afe_clk = spi_clk; assign spi_clk_clk = spi_clk; usdrx1_spi i_spi ( - .spi_fout_csn (spi_csn[10:5]), .spi_afe_csn (spi_csn[4:1]), .spi_clk_csn (spi_csn[0]), .spi_clk (spi_clk), .spi_mosi (spi_mosi), .spi_miso (spi_miso), - .spi_fout_sdio (spi_fout_sdio), .spi_afe_sdio (spi_afe_sdio), .spi_clk_sdio (spi_clk_sdio)); From ca9f7bf1f62cf0bf0d262a2f0f79a422bcacf117 Mon Sep 17 00:00:00 2001 From: Rejeesh Kutty Date: Fri, 19 Sep 2014 09:47:25 -0400 Subject: [PATCH 02/42] axi_ad9234: axi_ad9680 copy --- library/axi_ad9234/axi_ad9234.v | 323 +++++++++++++++++++++++ library/axi_ad9234/axi_ad9234_channel.v | 183 +++++++++++++ library/axi_ad9234/axi_ad9234_constr.xdc | 6 + library/axi_ad9234/axi_ad9234_if.v | 132 +++++++++ library/axi_ad9234/axi_ad9234_ip.tcl | 29 ++ library/axi_ad9234/axi_ad9234_pnmon.v | 244 +++++++++++++++++ 6 files changed, 917 insertions(+) create mode 100644 library/axi_ad9234/axi_ad9234.v create mode 100644 library/axi_ad9234/axi_ad9234_channel.v create mode 100644 library/axi_ad9234/axi_ad9234_constr.xdc create mode 100644 library/axi_ad9234/axi_ad9234_if.v create mode 100644 library/axi_ad9234/axi_ad9234_ip.tcl create mode 100644 library/axi_ad9234/axi_ad9234_pnmon.v diff --git a/library/axi_ad9234/axi_ad9234.v b/library/axi_ad9234/axi_ad9234.v new file mode 100644 index 000000000..efcf4c366 --- /dev/null +++ b/library/axi_ad9234/axi_ad9234.v @@ -0,0 +1,323 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2011(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module axi_ad9680 ( + + // jesd interface + // rx_clk is (line-rate/40) + + rx_clk, + rx_data, + + // dma interface + + adc_clk, + adc_enable_0, + adc_valid_0, + adc_data_0, + adc_enable_1, + adc_valid_1, + adc_data_1, + adc_dovf, + adc_dunf, + + // axi interface + + s_axi_aclk, + s_axi_aresetn, + s_axi_awvalid, + s_axi_awaddr, + s_axi_awready, + s_axi_wvalid, + s_axi_wdata, + s_axi_wstrb, + s_axi_wready, + s_axi_bvalid, + s_axi_bresp, + s_axi_bready, + s_axi_arvalid, + s_axi_araddr, + s_axi_arready, + s_axi_rvalid, + s_axi_rresp, + s_axi_rdata, + s_axi_rready); + + parameter PCORE_ID = 0; + parameter PCORE_DEVICE_TYPE = 0; + parameter PCORE_IODELAY_GROUP = "adc_if_delay_group"; + parameter C_S_AXI_MIN_SIZE = 32'hffff; + + // jesd interface + // rx_clk is (line-rate/40) + + input rx_clk; + input [127:0] rx_data; + + // dma interface + + output adc_clk; + output adc_enable_0; + output adc_valid_0; + output [63:0] adc_data_0; + output adc_enable_1; + output adc_valid_1; + output [63:0] adc_data_1; + input adc_dovf; + input adc_dunf; + + // axi interface + + input s_axi_aclk; + input s_axi_aresetn; + input s_axi_awvalid; + input [31:0] s_axi_awaddr; + output s_axi_awready; + input s_axi_wvalid; + input [31:0] s_axi_wdata; + input [ 3:0] s_axi_wstrb; + output s_axi_wready; + output s_axi_bvalid; + output [ 1:0] s_axi_bresp; + input s_axi_bready; + input s_axi_arvalid; + input [31:0] s_axi_araddr; + output s_axi_arready; + output s_axi_rvalid; + output [ 1:0] s_axi_rresp; + output [31:0] s_axi_rdata; + input s_axi_rready; + + // internal registers + + reg up_status_pn_err = 'd0; + reg up_status_pn_oos = 'd0; + reg up_status_or = 'd0; + reg [31:0] up_rdata = 'd0; + reg up_ack = 'd0; + + // internal clocks & resets + + wire adc_rst; + wire up_rstn; + wire up_clk; + + // internal signals + + wire [55:0] adc_data_a_s; + wire [55:0] adc_data_b_s; + wire adc_or_a_s; + wire adc_or_b_s; + wire adc_status_s; + wire [ 1:0] up_adc_pn_err_s; + wire [ 1:0] up_adc_pn_oos_s; + wire [ 1:0] up_adc_or_s; + wire [31:0] up_rdata_s[0:2]; + wire up_ack_s[0:2]; + wire up_sel_s; + wire up_wr_s; + wire [13:0] up_addr_s; + wire [31:0] up_wdata_s; + + // signal name changes + + assign up_clk = s_axi_aclk; + assign up_rstn = s_axi_aresetn; + + // defaults + + assign adc_valid_0 = 1'b1; + assign adc_valid_1 = 1'b1; + + // processor read interface + + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 0) begin + up_status_pn_err <= 'd0; + up_status_pn_oos <= 'd0; + up_status_or <= 'd0; + up_rdata <= 'd0; + up_ack <= 'd0; + end else begin + up_status_pn_err <= | up_adc_pn_err_s; + up_status_pn_oos <= | up_adc_pn_oos_s; + up_status_or <= | up_adc_or_s; + up_rdata <= up_rdata_s[0] | up_rdata_s[1] | up_rdata_s[2]; + up_ack <= up_ack_s[0] | up_ack_s[1] | up_ack_s[2]; + end + end + + // main (device interface) + + axi_ad9680_if i_if ( + .rx_clk (rx_clk), + .rx_data (rx_data), + .adc_clk (adc_clk), + .adc_rst (adc_rst), + .adc_data_a (adc_data_a_s), + .adc_data_b (adc_data_b_s), + .adc_or_a (adc_or_a_s), + .adc_or_b (adc_or_b_s), + .adc_status (adc_status_s)); + + // channel + + axi_ad9680_channel #(.IQSEL(0), .CHID(0)) i_channel_0 ( + .adc_clk (adc_clk), + .adc_rst (adc_rst), + .adc_data (adc_data_a_s), + .adc_or (adc_or_a_s), + .adc_dfmt_data (adc_data_0), + .adc_enable (adc_enable_0), + .up_adc_pn_err (up_adc_pn_err_s[0]), + .up_adc_pn_oos (up_adc_pn_oos_s[0]), + .up_adc_or (up_adc_or_s[0]), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_sel (up_sel_s), + .up_wr (up_wr_s), + .up_addr (up_addr_s), + .up_wdata (up_wdata_s), + .up_rdata (up_rdata_s[0]), + .up_ack (up_ack_s[0])); + + // channel + + axi_ad9680_channel #(.IQSEL(1), .CHID(1)) i_channel_1 ( + .adc_clk (adc_clk), + .adc_rst (adc_rst), + .adc_data (adc_data_b_s), + .adc_or (adc_or_b_s), + .adc_dfmt_data (adc_data_1), + .adc_enable (adc_enable_1), + .up_adc_pn_err (up_adc_pn_err_s[1]), + .up_adc_pn_oos (up_adc_pn_oos_s[1]), + .up_adc_or (up_adc_or_s[1]), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_sel (up_sel_s), + .up_wr (up_wr_s), + .up_addr (up_addr_s), + .up_wdata (up_wdata_s), + .up_rdata (up_rdata_s[1]), + .up_ack (up_ack_s[1])); + + // common processor control + + up_adc_common #(.PCORE_ID(PCORE_ID)) i_up_adc_common ( + .mmcm_rst (), + .adc_clk (adc_clk), + .adc_rst (adc_rst), + .adc_r1_mode (), + .adc_ddr_edgesel (), + .adc_pin_mode (), + .adc_status (adc_status_s), + .adc_status_ovf (adc_dovf), + .adc_status_unf (adc_dunf), + .adc_clk_ratio (32'd40), + .up_status_pn_err (up_status_pn_err), + .up_status_pn_oos (up_status_pn_oos), + .up_status_or (up_status_or), + .delay_clk (1'b0), + .delay_rst (), + .delay_sel (), + .delay_rwn (), + .delay_addr (), + .delay_wdata (), + .delay_rdata (5'd0), + .delay_ack_t (1'b0), + .delay_locked (1'b1), + .drp_clk (1'd0), + .drp_rst (), + .drp_sel (), + .drp_wr (), + .drp_addr (), + .drp_wdata (), + .drp_rdata (16'd0), + .drp_ready (1'd0), + .drp_locked (1'd1), + .up_usr_chanmax (), + .adc_usr_chanmax (8'd1), + .up_adc_gpio_in (32'd0), + .up_adc_gpio_out (), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_sel (up_sel_s), + .up_wr (up_wr_s), + .up_addr (up_addr_s), + .up_wdata (up_wdata_s), + .up_rdata (up_rdata_s[2]), + .up_ack (up_ack_s[2])); + + // up bus interface + + up_axi i_up_axi ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_axi_awvalid (s_axi_awvalid), + .up_axi_awaddr (s_axi_awaddr), + .up_axi_awready (s_axi_awready), + .up_axi_wvalid (s_axi_wvalid), + .up_axi_wdata (s_axi_wdata), + .up_axi_wstrb (s_axi_wstrb), + .up_axi_wready (s_axi_wready), + .up_axi_bvalid (s_axi_bvalid), + .up_axi_bresp (s_axi_bresp), + .up_axi_bready (s_axi_bready), + .up_axi_arvalid (s_axi_arvalid), + .up_axi_araddr (s_axi_araddr), + .up_axi_arready (s_axi_arready), + .up_axi_rvalid (s_axi_rvalid), + .up_axi_rresp (s_axi_rresp), + .up_axi_rdata (s_axi_rdata), + .up_axi_rready (s_axi_rready), + .up_sel (up_sel_s), + .up_wr (up_wr_s), + .up_addr (up_addr_s), + .up_wdata (up_wdata_s), + .up_rdata (up_rdata), + .up_ack (up_ack)); + +endmodule + +// *************************************************************************** +// *************************************************************************** + diff --git a/library/axi_ad9234/axi_ad9234_channel.v b/library/axi_ad9234/axi_ad9234_channel.v new file mode 100644 index 000000000..b80395265 --- /dev/null +++ b/library/axi_ad9234/axi_ad9234_channel.v @@ -0,0 +1,183 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2011(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** +// *************************************************************************** +// *************************************************************************** +// ADC channel- + +`timescale 1ns/100ps + +module axi_ad9680_channel ( + + // adc interface + + adc_clk, + adc_rst, + adc_data, + adc_or, + + // channel interface + + adc_dfmt_data, + adc_enable, + up_adc_pn_err, + up_adc_pn_oos, + up_adc_or, + + // processor interface + + up_rstn, + up_clk, + up_sel, + up_wr, + up_addr, + up_wdata, + up_rdata, + up_ack); + + // parameters + + parameter IQSEL = 0; + parameter CHID = 0; + + // adc interface + + input adc_clk; + input adc_rst; + input [55:0] adc_data; + input adc_or; + + // channel interface + + output [63:0] adc_dfmt_data; + output adc_enable; + output up_adc_pn_err; + output up_adc_pn_oos; + output up_adc_or; + + // processor interface + + input up_rstn; + input up_clk; + input up_sel; + input up_wr; + input [13:0] up_addr; + input [31:0] up_wdata; + output [31:0] up_rdata; + output up_ack; + + // internal signals + + wire adc_pn_oos_s; + wire adc_pn_err_s; + wire adc_dfmt_enable_s; + wire adc_dfmt_type_s; + wire adc_dfmt_se_s; + wire [ 3:0] adc_pnseq_sel_s; + + // instantiations + + axi_ad9680_pnmon i_pnmon ( + .adc_clk (adc_clk), + .adc_data (adc_data), + .adc_pn_oos (adc_pn_oos_s), + .adc_pn_err (adc_pn_err_s), + .adc_pnseq_sel (adc_pnseq_sel_s)); + + genvar n; + generate + for (n = 0; n < 4; n = n + 1) begin: g_ad_datafmt_1 + ad_datafmt #(.DATA_WIDTH(14)) i_ad_datafmt ( + .clk (adc_clk), + .valid (1'b1), + .data (adc_data[n*14+13:n*14]), + .valid_out (), + .data_out (adc_dfmt_data[n*16+15:n*16]), + .dfmt_enable (adc_dfmt_enable_s), + .dfmt_type (adc_dfmt_type_s), + .dfmt_se (adc_dfmt_se_s)); + end + endgenerate + + up_adc_channel #(.PCORE_ADC_CHID(CHID)) i_up_adc_channel ( + .adc_clk (adc_clk), + .adc_rst (adc_rst), + .adc_enable (adc_enable), + .adc_iqcor_enb (), + .adc_dcfilt_enb (), + .adc_dfmt_se (adc_dfmt_se_s), + .adc_dfmt_type (adc_dfmt_type_s), + .adc_dfmt_enable (adc_dfmt_enable_s), + .adc_dcfilt_offset (), + .adc_dcfilt_coeff (), + .adc_iqcor_coeff_1 (), + .adc_iqcor_coeff_2 (), + .adc_pnseq_sel (adc_pnseq_sel_s), + .adc_data_sel (), + .adc_pn_err (adc_pn_err_s), + .adc_pn_oos (adc_pn_oos_s), + .adc_or (adc_or), + .up_adc_pn_err (up_adc_pn_err), + .up_adc_pn_oos (up_adc_pn_oos), + .up_adc_or (up_adc_or), + .up_usr_datatype_be (), + .up_usr_datatype_signed (), + .up_usr_datatype_shift (), + .up_usr_datatype_total_bits (), + .up_usr_datatype_bits (), + .up_usr_decimation_m (), + .up_usr_decimation_n (), + .adc_usr_datatype_be (1'b0), + .adc_usr_datatype_signed (1'b1), + .adc_usr_datatype_shift (8'd0), + .adc_usr_datatype_total_bits (8'd16), + .adc_usr_datatype_bits (8'd16), + .adc_usr_decimation_m (16'd1), + .adc_usr_decimation_n (16'd1), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_sel (up_sel), + .up_wr (up_wr), + .up_addr (up_addr), + .up_wdata (up_wdata), + .up_rdata (up_rdata), + .up_ack (up_ack)); + +endmodule + +// *************************************************************************** +// *************************************************************************** + diff --git a/library/axi_ad9234/axi_ad9234_constr.xdc b/library/axi_ad9234/axi_ad9234_constr.xdc new file mode 100644 index 000000000..f22d7bdfa --- /dev/null +++ b/library/axi_ad9234/axi_ad9234_constr.xdc @@ -0,0 +1,6 @@ + +set_clock_groups -asynchronous -group [get_clocks -of_objects [get_ports adc_clk]] +set_clock_groups -asynchronous -group [get_clocks -of_objects [get_ports s_axi_aclk]] + + + diff --git a/library/axi_ad9234/axi_ad9234_if.v b/library/axi_ad9234/axi_ad9234_if.v new file mode 100644 index 000000000..c658b6b84 --- /dev/null +++ b/library/axi_ad9234/axi_ad9234_if.v @@ -0,0 +1,132 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2011(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** +// *************************************************************************** +// *************************************************************************** +// This is the LVDS/DDR interface + +`timescale 1ns/100ps + +module axi_ad9680_if ( + + // jesd interface + // rx_clk is (line-rate/40) + + rx_clk, + rx_data, + + // adc data output + + adc_clk, + adc_rst, + adc_data_a, + adc_data_b, + adc_or_a, + adc_or_b, + adc_status); + + // jesd interface + // rx_clk is (line-rate/40) + + input rx_clk; + input [127:0] rx_data; + + // adc data output + + output adc_clk; + input adc_rst; + output [55:0] adc_data_a; + output [55:0] adc_data_b; + output adc_or_a; + output adc_or_b; + output adc_status; + + // internal registers + + reg adc_status = 'd0; + + // internal signals + + wire [15:0] adc_data_a_s3_s; + wire [15:0] adc_data_a_s2_s; + wire [15:0] adc_data_a_s1_s; + wire [15:0] adc_data_a_s0_s; + wire [15:0] adc_data_b_s3_s; + wire [15:0] adc_data_b_s2_s; + wire [15:0] adc_data_b_s1_s; + wire [15:0] adc_data_b_s0_s; + + // adc clock is the reference clock + + assign adc_clk = rx_clk; + assign adc_or_a = 1'b0; + assign adc_or_b = 1'b0; + + // adc channels + + assign adc_data_a = { adc_data_a_s3_s[13:0], adc_data_a_s2_s[13:0], + adc_data_a_s1_s[13:0], adc_data_a_s0_s[13:0]}; + + assign adc_data_b = { adc_data_b_s3_s[13:0], adc_data_b_s2_s[13:0], + adc_data_b_s1_s[13:0], adc_data_b_s0_s[13:0]}; + + // data multiplex + + assign adc_data_a_s3_s = {rx_data[ 57: 56], rx_data[ 31: 24], rx_data[ 63: 58]}; + assign adc_data_a_s2_s = {rx_data[ 49: 48], rx_data[ 23: 16], rx_data[ 55: 50]}; + assign adc_data_a_s1_s = {rx_data[ 41: 40], rx_data[ 15: 8], rx_data[ 47: 42]}; + assign adc_data_a_s0_s = {rx_data[ 33: 32], rx_data[ 7: 0], rx_data[ 39: 34]}; + + assign adc_data_b_s3_s = {rx_data[121:120], rx_data[ 95: 88], rx_data[127:122]}; + assign adc_data_b_s2_s = {rx_data[113:112], rx_data[ 87: 80], rx_data[119:114]}; + assign adc_data_b_s1_s = {rx_data[105:104], rx_data[ 79: 72], rx_data[111:106]}; + assign adc_data_b_s0_s = {rx_data[ 97: 96], rx_data[ 71: 64], rx_data[103: 98]}; + + // status + + always @(posedge rx_clk) begin + if (adc_rst == 1'b1) begin + adc_status <= 1'b0; + end else begin + adc_status <= 1'b1; + end + end + +endmodule + +// *************************************************************************** +// *************************************************************************** + diff --git a/library/axi_ad9234/axi_ad9234_ip.tcl b/library/axi_ad9234/axi_ad9234_ip.tcl new file mode 100644 index 000000000..9426b317e --- /dev/null +++ b/library/axi_ad9234/axi_ad9234_ip.tcl @@ -0,0 +1,29 @@ +# ip + +source ../scripts/adi_env.tcl +source $ad_hdl_dir/library/scripts/adi_ip.tcl + +adi_ip_create axi_ad9680 +adi_ip_files axi_ad9680 [list \ + "$ad_hdl_dir/library/common/ad_rst.v" \ + "$ad_hdl_dir/library/common/ad_pnmon.v" \ + "$ad_hdl_dir/library/common/ad_datafmt.v" \ + "$ad_hdl_dir/library/common/up_axi.v" \ + "$ad_hdl_dir/library/common/up_xfer_cntrl.v" \ + "$ad_hdl_dir/library/common/up_xfer_status.v" \ + "$ad_hdl_dir/library/common/up_clock_mon.v" \ + "$ad_hdl_dir/library/common/up_drp_cntrl.v" \ + "$ad_hdl_dir/library/common/up_delay_cntrl.v" \ + "$ad_hdl_dir/library/common/up_adc_common.v" \ + "$ad_hdl_dir/library/common/up_adc_channel.v" \ + "axi_ad9680_pnmon.v" \ + "axi_ad9680_channel.v" \ + "axi_ad9680_if.v" \ + "axi_ad9680.v" ] + +adi_ip_properties axi_ad9680 +adi_ip_constraints axi_ad9680 [list \ + "axi_ad9680_constr.xdc" ] + +ipx::save_core [ipx::current_core] + diff --git a/library/axi_ad9234/axi_ad9234_pnmon.v b/library/axi_ad9234/axi_ad9234_pnmon.v new file mode 100644 index 000000000..4e64ca0fb --- /dev/null +++ b/library/axi_ad9234/axi_ad9234_pnmon.v @@ -0,0 +1,244 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2011(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** +// *************************************************************************** +// *************************************************************************** +// PN monitors + +`timescale 1ns/100ps + +module axi_ad9680_pnmon ( + + // adc interface + + adc_clk, + adc_data, + + // pn out of sync and error + + adc_pn_oos, + adc_pn_err, + + // processor interface PN9 (0x0), PN23 (0x1) + + adc_pnseq_sel); + + // adc interface + + input adc_clk; + input [55:0] adc_data; + + // pn out of sync and error + + output adc_pn_oos; + output adc_pn_err; + + // processor interface PN9 (0x0), PN23 (0x1) + + input [ 3:0] adc_pnseq_sel; + + // internal registers + + reg [55:0] adc_pn_data_in = 'd0; + reg [55:0] adc_pn_data_pn = 'd0; + + // internal signals + + wire [55:0] adc_pn_data_pn_s; + + // PN23 function + + function [55:0] pn23; + input [55:0] din; + reg [55:0] dout; + begin + dout[55] = din[22] ^ din[17]; + dout[54] = din[21] ^ din[16]; + dout[53] = din[20] ^ din[15]; + dout[52] = din[19] ^ din[14]; + dout[51] = din[18] ^ din[13]; + dout[50] = din[17] ^ din[12]; + dout[49] = din[16] ^ din[11]; + dout[48] = din[15] ^ din[10]; + dout[47] = din[14] ^ din[ 9]; + dout[46] = din[13] ^ din[ 8]; + dout[45] = din[12] ^ din[ 7]; + dout[44] = din[11] ^ din[ 6]; + dout[43] = din[10] ^ din[ 5]; + dout[42] = din[ 9] ^ din[ 4]; + dout[41] = din[ 8] ^ din[ 3]; + dout[40] = din[ 7] ^ din[ 2]; + dout[39] = din[ 6] ^ din[ 1]; + dout[38] = din[ 5] ^ din[ 0]; + dout[37] = din[ 4] ^ din[22] ^ din[17]; + dout[36] = din[ 3] ^ din[21] ^ din[16]; + dout[35] = din[ 2] ^ din[20] ^ din[15]; + dout[34] = din[ 1] ^ din[19] ^ din[14]; + dout[33] = din[ 0] ^ din[18] ^ din[13]; + dout[32] = din[22] ^ din[12]; + dout[31] = din[21] ^ din[11]; + dout[30] = din[20] ^ din[10]; + dout[29] = din[19] ^ din[ 9]; + dout[28] = din[18] ^ din[ 8]; + dout[27] = din[17] ^ din[ 7]; + dout[26] = din[16] ^ din[ 6]; + dout[25] = din[15] ^ din[ 5]; + dout[24] = din[14] ^ din[ 4]; + dout[23] = din[13] ^ din[ 3]; + dout[22] = din[12] ^ din[ 2]; + dout[21] = din[11] ^ din[ 1]; + dout[20] = din[10] ^ din[ 0]; + dout[19] = din[ 9] ^ din[22] ^ din[17]; + dout[18] = din[ 8] ^ din[21] ^ din[16]; + dout[17] = din[ 7] ^ din[20] ^ din[15]; + dout[16] = din[ 6] ^ din[19] ^ din[14]; + dout[15] = din[ 5] ^ din[18] ^ din[13]; + dout[14] = din[ 4] ^ din[17] ^ din[12]; + dout[13] = din[ 3] ^ din[16] ^ din[11]; + dout[12] = din[ 2] ^ din[15] ^ din[10]; + dout[11] = din[ 1] ^ din[14] ^ din[ 9]; + dout[10] = din[ 0] ^ din[13] ^ din[ 8]; + dout[ 9] = din[22] ^ din[12] ^ din[17] ^ din[ 7]; + dout[ 8] = din[21] ^ din[11] ^ din[16] ^ din[ 6]; + dout[ 7] = din[20] ^ din[10] ^ din[15] ^ din[ 5]; + dout[ 6] = din[19] ^ din[ 9] ^ din[14] ^ din[ 4]; + dout[ 5] = din[18] ^ din[ 8] ^ din[13] ^ din[ 3]; + dout[ 4] = din[17] ^ din[ 7] ^ din[12] ^ din[ 2]; + dout[ 3] = din[16] ^ din[ 6] ^ din[11] ^ din[ 1]; + dout[ 2] = din[15] ^ din[ 5] ^ din[10] ^ din[ 0]; + dout[ 1] = din[14] ^ din[ 4] ^ din[ 9] ^ din[22] ^ din[17]; + dout[ 0] = din[13] ^ din[ 3] ^ din[ 8] ^ din[21] ^ din[16]; + pn23 = dout; + end + endfunction + + // PN9 function + + function [55:0] pn9; + input [55:0] din; + reg [55:0] dout; + begin + dout[55] = din[ 8] ^ din[ 4]; + dout[54] = din[ 7] ^ din[ 3]; + dout[53] = din[ 6] ^ din[ 2]; + dout[52] = din[ 5] ^ din[ 1]; + dout[51] = din[ 4] ^ din[ 0]; + dout[50] = din[ 3] ^ din[ 8] ^ din[ 4]; + dout[49] = din[ 2] ^ din[ 7] ^ din[ 3]; + dout[48] = din[ 1] ^ din[ 6] ^ din[ 2]; + dout[47] = din[ 0] ^ din[ 5] ^ din[ 1]; + dout[46] = din[ 8] ^ din[ 0]; + dout[45] = din[ 7] ^ din[ 8] ^ din[ 4]; + dout[44] = din[ 6] ^ din[ 7] ^ din[ 3]; + dout[43] = din[ 5] ^ din[ 6] ^ din[ 2]; + dout[42] = din[ 4] ^ din[ 5] ^ din[ 1]; + dout[41] = din[ 3] ^ din[ 4] ^ din[ 0]; + dout[40] = din[ 2] ^ din[ 3] ^ din[ 8] ^ din[ 4]; + dout[39] = din[ 1] ^ din[ 2] ^ din[ 7] ^ din[ 3]; + dout[38] = din[ 0] ^ din[ 1] ^ din[ 6] ^ din[ 2]; + dout[37] = din[ 8] ^ din[ 0] ^ din[ 4] ^ din[ 5] ^ din[ 1]; + dout[36] = din[ 7] ^ din[ 8] ^ din[ 3] ^ din[ 0]; + dout[35] = din[ 6] ^ din[ 7] ^ din[ 2] ^ din[ 8] ^ din[ 4]; + dout[34] = din[ 5] ^ din[ 6] ^ din[ 1] ^ din[ 7] ^ din[ 3]; + dout[33] = din[ 4] ^ din[ 5] ^ din[ 0] ^ din[ 6] ^ din[ 2]; + dout[32] = din[ 3] ^ din[ 8] ^ din[ 5] ^ din[ 1]; + dout[31] = din[ 2] ^ din[ 4] ^ din[ 7] ^ din[ 0]; + dout[30] = din[ 1] ^ din[ 3] ^ din[ 6] ^ din[ 8] ^ din[ 4]; + dout[29] = din[ 0] ^ din[ 2] ^ din[ 5] ^ din[ 7] ^ din[ 3]; + dout[28] = din[ 8] ^ din[ 1] ^ din[ 6] ^ din[ 2]; + dout[27] = din[ 7] ^ din[ 0] ^ din[ 5] ^ din[ 1]; + dout[26] = din[ 6] ^ din[ 8] ^ din[ 0]; + dout[25] = din[ 5] ^ din[ 7] ^ din[ 8] ^ din[ 4]; + dout[24] = din[ 4] ^ din[ 6] ^ din[ 7] ^ din[ 3]; + dout[23] = din[ 3] ^ din[ 5] ^ din[ 6] ^ din[ 2]; + dout[22] = din[ 2] ^ din[ 4] ^ din[ 5] ^ din[ 1]; + dout[21] = din[ 1] ^ din[ 3] ^ din[ 4] ^ din[ 0]; + dout[20] = din[ 0] ^ din[ 2] ^ din[ 3] ^ din[ 8] ^ din[ 4]; + dout[19] = din[ 8] ^ din[ 1] ^ din[ 2] ^ din[ 4] ^ din[ 7] ^ din[ 3]; + dout[18] = din[ 7] ^ din[ 0] ^ din[ 1] ^ din[ 3] ^ din[ 6] ^ din[ 2]; + dout[17] = din[ 6] ^ din[ 8] ^ din[ 0] ^ din[ 2] ^ din[ 4] ^ din[ 5] ^ din[ 1]; + dout[16] = din[ 5] ^ din[ 7] ^ din[ 8] ^ din[ 1] ^ din[ 3] ^ din[ 0]; + dout[15] = din[ 6] ^ din[ 7] ^ din[ 0] ^ din[ 2] ^ din[ 8]; + dout[14] = din[ 5] ^ din[ 6] ^ din[ 8] ^ din[ 1] ^ din[ 4] ^ din[ 7]; + dout[13] = din[ 4] ^ din[ 5] ^ din[ 7] ^ din[ 0] ^ din[ 3] ^ din[ 6]; + dout[12] = din[ 3] ^ din[ 6] ^ din[ 8] ^ din[ 2] ^ din[ 5]; + dout[11] = din[ 2] ^ din[ 4] ^ din[ 5] ^ din[ 7] ^ din[ 1]; + dout[10] = din[ 1] ^ din[ 4] ^ din[ 3] ^ din[ 6] ^ din[ 0]; + dout[ 9] = din[ 0] ^ din[ 3] ^ din[ 2] ^ din[ 5] ^ din[ 8] ^ din[ 4]; + dout[ 8] = din[ 8] ^ din[ 2] ^ din[ 1] ^ din[ 7] ^ din[ 3]; + dout[ 7] = din[ 7] ^ din[ 1] ^ din[ 0] ^ din[ 6] ^ din[ 2]; + dout[ 6] = din[ 6] ^ din[ 0] ^ din[ 8] ^ din[ 4] ^ din[ 5] ^ din[ 1]; + dout[ 5] = din[ 5] ^ din[ 8] ^ din[ 7] ^ din[ 3] ^ din[ 0]; + dout[ 4] = din[ 7] ^ din[ 6] ^ din[ 2] ^ din[ 8]; + dout[ 3] = din[ 6] ^ din[ 5] ^ din[ 1] ^ din[ 7]; + dout[ 2] = din[ 4] ^ din[ 5] ^ din[ 0] ^ din[ 6]; + dout[ 1] = din[ 3] ^ din[ 8] ^ din[ 5]; + dout[ 0] = din[ 2] ^ din[ 4] ^ din[ 7]; + pn9 = dout; + end + endfunction + + // pn sequence select + + assign adc_pn_data_pn_s = (adc_pn_oos == 1'b1) ? adc_pn_data_in : adc_pn_data_pn; + + always @(posedge adc_clk) begin + adc_pn_data_in <= { ~adc_data[13], adc_data[12: 0], + ~adc_data[27], adc_data[26:14], + ~adc_data[41], adc_data[40:28], + ~adc_data[55], adc_data[54:42]}; + if (adc_pnseq_sel == 4'd0) begin + adc_pn_data_pn <= pn9(adc_pn_data_pn_s); + end else begin + adc_pn_data_pn <= pn23(adc_pn_data_pn_s); + end + end + + // pn oos & pn err + + ad_pnmon #(.DATA_WIDTH(56)) i_pnmon ( + .adc_clk (adc_clk), + .adc_valid_in (1'b1), + .adc_data_in (adc_pn_data_in), + .adc_data_pn (adc_pn_data_pn), + .adc_pn_oos (adc_pn_oos), + .adc_pn_err (adc_pn_err)); + +endmodule + +// *************************************************************************** +// *************************************************************************** + From 0cb75671100892f520732284e199ea89777528fe Mon Sep 17 00:00:00 2001 From: Rejeesh Kutty Date: Fri, 19 Sep 2014 09:53:47 -0400 Subject: [PATCH 03/42] fmcadc3: daq2 copy --- projects/fmcadc3/common/fmcadc3_bd.tcl | 508 ++++++++++++++++++++ projects/fmcadc3/common/fmcadc3_spi.v | 109 +++++ projects/fmcadc3/zc706/system_bd.tcl | 58 +++ projects/fmcadc3/zc706/system_constr.xdc | 74 +++ projects/fmcadc3/zc706/system_project.tcl | 17 + projects/fmcadc3/zc706/system_top.v | 537 ++++++++++++++++++++++ 6 files changed, 1303 insertions(+) create mode 100644 projects/fmcadc3/common/fmcadc3_bd.tcl create mode 100644 projects/fmcadc3/common/fmcadc3_spi.v create mode 100644 projects/fmcadc3/zc706/system_bd.tcl create mode 100644 projects/fmcadc3/zc706/system_constr.xdc create mode 100644 projects/fmcadc3/zc706/system_project.tcl create mode 100644 projects/fmcadc3/zc706/system_top.v diff --git a/projects/fmcadc3/common/fmcadc3_bd.tcl b/projects/fmcadc3/common/fmcadc3_bd.tcl new file mode 100644 index 000000000..d7f93512c --- /dev/null +++ b/projects/fmcadc3/common/fmcadc3_bd.tcl @@ -0,0 +1,508 @@ + + # daq2 + + set spi_csn_i [create_bd_port -dir I -from 2 -to 0 spi_csn_i] + set spi_csn_o [create_bd_port -dir O -from 2 -to 0 spi_csn_o] + set spi_clk_i [create_bd_port -dir I spi_clk_i] + set spi_clk_o [create_bd_port -dir O spi_clk_o] + set spi_sdo_i [create_bd_port -dir I spi_sdo_i] + set spi_sdo_o [create_bd_port -dir O spi_sdo_o] + set spi_sdi_i [create_bd_port -dir I spi_sdi_i] + + set rx_ref_clk [create_bd_port -dir I rx_ref_clk] + set rx_sync [create_bd_port -dir O rx_sync] + set rx_sysref [create_bd_port -dir I rx_sysref] + set rx_data_p [create_bd_port -dir I -from 3 -to 0 rx_data_p] + set rx_data_n [create_bd_port -dir I -from 3 -to 0 rx_data_n] + + set tx_ref_clk [create_bd_port -dir I tx_ref_clk] + set tx_sync [create_bd_port -dir I tx_sync] + set tx_sysref [create_bd_port -dir I tx_sysref] + set tx_data_p [create_bd_port -dir O -from 3 -to 0 tx_data_p] + set tx_data_n [create_bd_port -dir O -from 3 -to 0 tx_data_n] + +if {$sys_zynq == 0} { + + set gpio_ctl_i [create_bd_port -dir I -from 5 -to 0 gpio_ctl_i] + set gpio_ctl_o [create_bd_port -dir O -from 5 -to 0 gpio_ctl_o] + set gpio_ctl_t [create_bd_port -dir O -from 5 -to 0 gpio_ctl_t] + set gpio_status_i [create_bd_port -dir I -from 4 -to 0 gpio_status_i] + set gpio_status_o [create_bd_port -dir O -from 4 -to 0 gpio_status_o] + set gpio_status_t [create_bd_port -dir O -from 4 -to 0 gpio_status_t] +} + + set dac_clk [create_bd_port -dir O dac_clk] + set dac_valid_0 [create_bd_port -dir O dac_valid_0] + set dac_enable_0 [create_bd_port -dir O dac_enable_0] + set dac_ddata_0 [create_bd_port -dir I -from 63 -to 0 dac_ddata_0] + set dac_valid_1 [create_bd_port -dir O dac_valid_1] + set dac_enable_1 [create_bd_port -dir O dac_enable_1] + set dac_ddata_1 [create_bd_port -dir I -from 63 -to 0 dac_ddata_1] + set dac_valid_2 [create_bd_port -dir O dac_valid_2] + set dac_enable_2 [create_bd_port -dir O dac_enable_2] + set dac_ddata_2 [create_bd_port -dir I -from 63 -to 0 dac_ddata_2] + set dac_valid_3 [create_bd_port -dir O dac_valid_3] + set dac_enable_3 [create_bd_port -dir O dac_enable_3] + set dac_ddata_3 [create_bd_port -dir I -from 63 -to 0 dac_ddata_3] + set dac_drd [create_bd_port -dir I dac_drd] + set dac_ddata [create_bd_port -dir O -from 127 -to 0 dac_ddata] + + set adc_clk [create_bd_port -dir O adc_clk] + set adc_enable_0 [create_bd_port -dir O adc_enable_0] + set adc_valid_0 [create_bd_port -dir O adc_valid_0] + set adc_data_0 [create_bd_port -dir O -from 63 -to 0 adc_data_0] + set adc_enable_1 [create_bd_port -dir O adc_enable_1] + set adc_valid_1 [create_bd_port -dir O adc_valid_1] + set adc_data_1 [create_bd_port -dir O -from 63 -to 0 adc_data_1] + set adc_dwr [create_bd_port -dir I adc_dwr] + set adc_dsync [create_bd_port -dir I adc_dsync] + set adc_ddata [create_bd_port -dir I -from 127 -to 0 adc_ddata] + + # dac peripherals + + set axi_ad9144_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9144:1.0 axi_ad9144_core] + set_property -dict [list CONFIG.PCORE_QUAD_DUAL_N {0}] $axi_ad9144_core + + set axi_ad9144_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:5.1 axi_ad9144_jesd] + set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {1}] $axi_ad9144_jesd + set_property -dict [list CONFIG.C_LANES {4}] $axi_ad9144_jesd + + set axi_ad9144_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad9144_dma] + set_property -dict [list CONFIG.C_DMA_TYPE_SRC {0}] $axi_ad9144_dma + set_property -dict [list CONFIG.C_DMA_TYPE_DEST {2}] $axi_ad9144_dma + set_property -dict [list CONFIG.PCORE_ID {1}] $axi_ad9144_dma + set_property -dict [list CONFIG.C_AXI_SLICE_SRC {0}] $axi_ad9144_dma + set_property -dict [list CONFIG.C_AXI_SLICE_DEST {0}] $axi_ad9144_dma + set_property -dict [list CONFIG.C_CLKS_ASYNC_REQ_SRC {1}] $axi_ad9144_dma + set_property -dict [list CONFIG.C_DMA_LENGTH_WIDTH {24}] $axi_ad9144_dma + set_property -dict [list CONFIG.C_2D_TRANSFER {0}] $axi_ad9144_dma + set_property -dict [list CONFIG.C_CYCLIC {1}] $axi_ad9144_dma + set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_SRC {128}] $axi_ad9144_dma + set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_DEST {128}] $axi_ad9144_dma + +if {$sys_zynq == 1} { + + set axi_ad9144_dma_interconnect [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_ad9144_dma_interconnect] + set_property -dict [list CONFIG.NUM_MI {1}] $axi_ad9144_dma_interconnect +} + + # adc peripherals + + set axi_ad9680_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9680:1.0 axi_ad9680_core] + + set axi_ad9680_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:5.1 axi_ad9680_jesd] + set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {0}] $axi_ad9680_jesd + set_property -dict [list CONFIG.C_LANES {4}] $axi_ad9680_jesd + + set axi_ad9680_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad9680_dma] + set_property -dict [list CONFIG.C_DMA_TYPE_SRC {2}] $axi_ad9680_dma + set_property -dict [list CONFIG.C_DMA_TYPE_DEST {0}] $axi_ad9680_dma + set_property -dict [list CONFIG.PCORE_ID {0}] $axi_ad9680_dma + set_property -dict [list CONFIG.C_AXI_SLICE_SRC {0}] $axi_ad9680_dma + set_property -dict [list CONFIG.C_AXI_SLICE_DEST {0}] $axi_ad9680_dma + set_property -dict [list CONFIG.C_CLKS_ASYNC_DEST_REQ {1}] $axi_ad9680_dma + set_property -dict [list CONFIG.C_SYNC_TRANSFER_START {1}] $axi_ad9680_dma + set_property -dict [list CONFIG.C_DMA_LENGTH_WIDTH {24}] $axi_ad9680_dma + set_property -dict [list CONFIG.C_2D_TRANSFER {0}] $axi_ad9680_dma + set_property -dict [list CONFIG.C_CYCLIC {0}] $axi_ad9680_dma + set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_SRC {128}] $axi_ad9680_dma + set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_DEST {128}] $axi_ad9680_dma + +if {$sys_zynq == 1} { + + set axi_ad9680_dma_interconnect [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_ad9680_dma_interconnect] + set_property -dict [list CONFIG.NUM_MI {1}] $axi_ad9680_dma_interconnect +} + + # dac/adc common gt/gpio + + set axi_daq2_gt [create_bd_cell -type ip -vlnv analog.com:user:axi_jesd_gt:1.0 axi_daq2_gt] + set_property -dict [list CONFIG.PCORE_NUM_OF_LANES {4}] $axi_daq2_gt + +if {$sys_zynq == 1} { + + set axi_daq2_gt_interconnect [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_daq2_gt_interconnect] + set_property -dict [list CONFIG.NUM_MI {1}] $axi_daq2_gt_interconnect +} + + # gpio and spi + +if {$sys_zynq == 0} { + + set axi_daq2_spi [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_quad_spi:3.1 axi_daq2_spi] + set_property -dict [list CONFIG.C_USE_STARTUP {0}] $axi_daq2_spi + set_property -dict [list CONFIG.C_NUM_SS_BITS {3}] $axi_daq2_spi + set_property -dict [list CONFIG.C_SCK_RATIO {8}] $axi_daq2_spi + + set axi_daq2_gpio [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_daq2_gpio] + set_property -dict [list CONFIG.C_IS_DUAL {1}] $axi_daq2_gpio + set_property -dict [list CONFIG.C_GPIO_WIDTH {5}] $axi_daq2_gpio + set_property -dict [list CONFIG.C_GPIO2_WIDTH {6}] $axi_daq2_gpio + set_property -dict [list CONFIG.C_INTERRUPT_PRESENT {1}] $axi_daq2_gpio +} + + # additions to default configuration + +if {$sys_zynq == 0} { + + set_property -dict [list CONFIG.NUM_MI {16}] $axi_cpu_interconnect + +} else { + + set_property -dict [list CONFIG.NUM_MI {14}] $axi_cpu_interconnect +} + +if {$sys_zynq == 0} { + + set_property -dict [list CONFIG.NUM_SI {11}] $axi_mem_interconnect + set_property -dict [list CONFIG.NUM_PORTS {7}] $sys_concat_intc +} + +if {$sys_zynq == 1} { + + set_property -dict [list CONFIG.PCW_USE_S_AXI_HP1 {1}] $sys_ps7 + set_property -dict [list CONFIG.PCW_USE_S_AXI_HP2 {1}] $sys_ps7 + set_property -dict [list CONFIG.PCW_USE_S_AXI_HP3 {1}] $sys_ps7 + set_property -dict [list CONFIG.PCW_EN_CLK2_PORT {1}] $sys_ps7 + set_property -dict [list CONFIG.PCW_EN_RST2_PORT {1}] $sys_ps7 + set_property -dict [list CONFIG.PCW_FPGA2_PERIPHERAL_FREQMHZ {200.0}] $sys_ps7 + set_property -dict [list CONFIG.PCW_GPIO_EMIO_GPIO_IO {43}] $sys_ps7 + set_property -dict [list CONFIG.PCW_SPI0_PERIPHERAL_ENABLE {1}] $sys_ps7 + set_property -dict [list CONFIG.PCW_SPI0_SPI0_IO {EMIO}] $sys_ps7 + + set_property LEFT 42 [get_bd_ports GPIO_I] + set_property LEFT 42 [get_bd_ports GPIO_O] + set_property LEFT 42 [get_bd_ports GPIO_T] +} + + # connections (spi and gpio) + +if {$sys_zynq == 0} { + + connect_bd_net -net spi_csn_i [get_bd_ports spi_csn_i] [get_bd_pins axi_daq2_spi/ss_i] + connect_bd_net -net spi_csn_o [get_bd_ports spi_csn_o] [get_bd_pins axi_daq2_spi/ss_o] + connect_bd_net -net spi_clk_i [get_bd_ports spi_clk_i] [get_bd_pins axi_daq2_spi/sck_i] + connect_bd_net -net spi_clk_o [get_bd_ports spi_clk_o] [get_bd_pins axi_daq2_spi/sck_o] + connect_bd_net -net spi_sdo_i [get_bd_ports spi_sdo_i] [get_bd_pins axi_daq2_spi/io0_i] + connect_bd_net -net spi_sdo_o [get_bd_ports spi_sdo_o] [get_bd_pins axi_daq2_spi/io0_o] + connect_bd_net -net spi_sdi_i [get_bd_ports spi_sdi_i] [get_bd_pins axi_daq2_spi/io1_i] + +} else { + set sys_spi_csn_concat [create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:1.0 sys_spi_csn_concat] + set_property -dict [list CONFIG.NUM_PORTS {3}] $sys_spi_csn_concat + + set sys_const_vcc [create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.0 sys_const_vcc] + set_property -dict [list CONFIG.CONST_WIDTH {1} CONFIG.CONST_VAL {1}] $sys_const_vcc + + connect_bd_net -net spi_csn0 [get_bd_pins sys_spi_csn_concat/In2] [get_bd_pins sys_ps7/SPI0_SS_O] + connect_bd_net -net spi_csn1 [get_bd_pins sys_spi_csn_concat/In1] [get_bd_pins sys_ps7/SPI0_SS1_O] + connect_bd_net -net spi_csn2 [get_bd_pins sys_spi_csn_concat/In0] [get_bd_pins sys_ps7/SPI0_SS2_O] + connect_bd_net -net spi_csn_o [get_bd_ports spi_csn_o] [get_bd_pins sys_spi_csn_concat/dout] + connect_bd_net -net spi_csn_i [get_bd_pins sys_const_vcc/const] [get_bd_pins sys_ps7/SPI0_SS_I] + connect_bd_net -net spi_clk_i [get_bd_ports spi_clk_i] [get_bd_pins sys_ps7/SPI0_SCLK_I] + connect_bd_net -net spi_clk_o [get_bd_ports spi_clk_o] [get_bd_pins sys_ps7/SPI0_SCLK_O] + connect_bd_net -net spi_sdo_i [get_bd_ports spi_sdo_i] [get_bd_pins sys_ps7/SPI0_MOSI_I] + connect_bd_net -net spi_sdo_o [get_bd_ports spi_sdo_o] [get_bd_pins sys_ps7/SPI0_MOSI_O] + connect_bd_net -net spi_sdi_i [get_bd_ports spi_sdi_i] [get_bd_pins sys_ps7/SPI0_MISO_I] +} + +if {$sys_zynq == 0} { + + connect_bd_net -net gpio_status_i [get_bd_ports gpio_status_i] [get_bd_pins axi_daq2_gpio/gpio_io_i] + connect_bd_net -net gpio_status_o [get_bd_ports gpio_status_o] [get_bd_pins axi_daq2_gpio/gpio_io_o] + connect_bd_net -net gpio_status_t [get_bd_ports gpio_status_t] [get_bd_pins axi_daq2_gpio/gpio_io_t] + connect_bd_net -net gpio_ctl_i [get_bd_ports gpio_ctl_i] [get_bd_pins axi_daq2_gpio/gpio2_io_i] + connect_bd_net -net gpio_ctl_o [get_bd_ports gpio_ctl_o] [get_bd_pins axi_daq2_gpio/gpio2_io_o] + connect_bd_net -net gpio_ctl_t [get_bd_ports gpio_ctl_t] [get_bd_pins axi_daq2_gpio/gpio2_io_t] +} + +if {$sys_zynq == 0} { + + delete_bd_objs [get_bd_nets sys_concat_intc_din_2] [get_bd_ports unc_int2] + delete_bd_objs [get_bd_nets sys_concat_intc_din_3] [get_bd_ports unc_int3] +} + + # connections (gt) + + connect_bd_net -net axi_daq2_gt_ref_clk_q [get_bd_pins axi_daq2_gt/ref_clk_q] [get_bd_ports rx_ref_clk] + connect_bd_net -net axi_daq2_gt_ref_clk_c [get_bd_pins axi_daq2_gt/ref_clk_c] [get_bd_ports tx_ref_clk] + connect_bd_net -net axi_daq2_gt_rx_data_p [get_bd_pins axi_daq2_gt/rx_data_p] [get_bd_ports rx_data_p] + connect_bd_net -net axi_daq2_gt_rx_data_n [get_bd_pins axi_daq2_gt/rx_data_n] [get_bd_ports rx_data_n] + connect_bd_net -net axi_daq2_gt_rx_sync [get_bd_pins axi_daq2_gt/rx_sync] [get_bd_ports rx_sync] + connect_bd_net -net axi_daq2_gt_rx_ext_sysref [get_bd_pins axi_daq2_gt/rx_ext_sysref] [get_bd_ports rx_sysref] + connect_bd_net -net axi_daq2_gt_tx_data_p [get_bd_pins axi_daq2_gt/tx_data_p] [get_bd_ports tx_data_p] + connect_bd_net -net axi_daq2_gt_tx_data_n [get_bd_pins axi_daq2_gt/tx_data_n] [get_bd_ports tx_data_n] + connect_bd_net -net axi_daq2_gt_tx_sync [get_bd_pins axi_daq2_gt/tx_sync] [get_bd_ports tx_sync] + connect_bd_net -net axi_daq2_gt_tx_ext_sysref [get_bd_pins axi_daq2_gt/tx_ext_sysref] [get_bd_ports tx_sysref] + + # connections (dac) + + connect_bd_net -net axi_daq2_gt_tx_clk [get_bd_pins axi_daq2_gt/tx_clk_g] + connect_bd_net -net axi_daq2_gt_tx_clk [get_bd_pins axi_daq2_gt/tx_clk] + connect_bd_net -net axi_daq2_gt_tx_clk [get_bd_pins axi_ad9144_core/tx_clk] + connect_bd_net -net axi_daq2_gt_tx_clk [get_bd_pins axi_ad9144_jesd/tx_core_clk] + + connect_bd_net -net axi_daq2_gt_tx_rst [get_bd_pins axi_daq2_gt/tx_rst] [get_bd_pins axi_ad9144_jesd/tx_reset] + connect_bd_net -net axi_daq2_gt_tx_sysref [get_bd_pins axi_daq2_gt/tx_sysref] [get_bd_pins axi_ad9144_jesd/tx_sysref] + connect_bd_net -net axi_daq2_gt_tx_gt_charisk [get_bd_pins axi_daq2_gt/tx_gt_charisk] [get_bd_pins axi_ad9144_jesd/gt_txcharisk_out] + connect_bd_net -net axi_daq2_gt_tx_gt_data [get_bd_pins axi_daq2_gt/tx_gt_data] [get_bd_pins axi_ad9144_jesd/gt_txdata_out] + connect_bd_net -net axi_daq2_gt_tx_rst_done [get_bd_pins axi_daq2_gt/tx_rst_done] [get_bd_pins axi_ad9144_jesd/tx_reset_done] + connect_bd_net -net axi_daq2_gt_tx_ip_sync [get_bd_pins axi_daq2_gt/tx_ip_sync] [get_bd_pins axi_ad9144_jesd/tx_sync] + connect_bd_net -net axi_daq2_gt_tx_ip_sof [get_bd_pins axi_daq2_gt/tx_ip_sof] [get_bd_pins axi_ad9144_jesd/tx_start_of_frame] + connect_bd_net -net axi_daq2_gt_tx_ip_data [get_bd_pins axi_daq2_gt/tx_ip_data] [get_bd_pins axi_ad9144_jesd/tx_tdata] + connect_bd_net -net axi_daq2_gt_tx_data [get_bd_pins axi_daq2_gt/tx_data] [get_bd_pins axi_ad9144_core/tx_data] + connect_bd_net -net axi_ad9144_dac_clk [get_bd_pins axi_ad9144_core/dac_clk] [get_bd_pins axi_ad9144_dma/fifo_rd_clk] + connect_bd_net -net axi_ad9144_dac_valid_0 [get_bd_pins axi_ad9144_core/dac_valid_0] [get_bd_ports dac_valid_0] + connect_bd_net -net axi_ad9144_dac_enable_0 [get_bd_pins axi_ad9144_core/dac_enable_0] [get_bd_ports dac_enable_0] + connect_bd_net -net axi_ad9144_dac_ddata_0 [get_bd_pins axi_ad9144_core/dac_ddata_0] [get_bd_ports dac_ddata_0] + connect_bd_net -net axi_ad9144_dac_valid_1 [get_bd_pins axi_ad9144_core/dac_valid_1] [get_bd_ports dac_valid_1] + connect_bd_net -net axi_ad9144_dac_enable_1 [get_bd_pins axi_ad9144_core/dac_enable_1] [get_bd_ports dac_enable_1] + connect_bd_net -net axi_ad9144_dac_ddata_1 [get_bd_pins axi_ad9144_core/dac_ddata_1] [get_bd_ports dac_ddata_1] + connect_bd_net -net axi_ad9144_dac_valid_2 [get_bd_pins axi_ad9144_core/dac_valid_2] [get_bd_ports dac_valid_2] + connect_bd_net -net axi_ad9144_dac_enable_2 [get_bd_pins axi_ad9144_core/dac_enable_2] [get_bd_ports dac_enable_2] + connect_bd_net -net axi_ad9144_dac_ddata_2 [get_bd_pins axi_ad9144_core/dac_ddata_2] [get_bd_ports dac_ddata_2] + connect_bd_net -net axi_ad9144_dac_valid_3 [get_bd_pins axi_ad9144_core/dac_valid_3] [get_bd_ports dac_valid_3] + connect_bd_net -net axi_ad9144_dac_enable_3 [get_bd_pins axi_ad9144_core/dac_enable_3] [get_bd_ports dac_enable_3] + connect_bd_net -net axi_ad9144_dac_ddata_3 [get_bd_pins axi_ad9144_core/dac_ddata_3] [get_bd_ports dac_ddata_3] + connect_bd_net -net axi_ad9144_dac_drd [get_bd_ports dac_drd] [get_bd_pins axi_ad9144_dma/fifo_rd_en] + connect_bd_net -net axi_ad9144_dac_ddata [get_bd_ports dac_ddata] [get_bd_pins axi_ad9144_dma/fifo_rd_dout] + connect_bd_net -net axi_ad9144_dac_dunf [get_bd_pins axi_ad9144_core/dac_dunf] [get_bd_pins axi_ad9144_dma/fifo_rd_underflow] + connect_bd_net -net axi_ad9144_dma_irq [get_bd_pins axi_ad9144_dma/irq] [get_bd_pins sys_concat_intc/In3] + + # connections (adc) + + connect_bd_net -net axi_daq2_gt_rx_clk [get_bd_pins axi_daq2_gt/rx_clk_g] + connect_bd_net -net axi_daq2_gt_rx_clk [get_bd_pins axi_daq2_gt/rx_clk] + connect_bd_net -net axi_daq2_gt_rx_clk [get_bd_pins axi_ad9680_core/rx_clk] + connect_bd_net -net axi_daq2_gt_rx_clk [get_bd_pins axi_ad9680_jesd/rx_core_clk] + + connect_bd_net -net axi_daq2_gt_rx_rst [get_bd_pins axi_daq2_gt/rx_rst] [get_bd_pins axi_ad9680_jesd/rx_reset] + connect_bd_net -net axi_daq2_gt_rx_sysref [get_bd_pins axi_daq2_gt/rx_sysref] [get_bd_pins axi_ad9680_jesd/rx_sysref] + connect_bd_net -net axi_daq2_gt_rx_gt_charisk [get_bd_pins axi_daq2_gt/rx_gt_charisk] [get_bd_pins axi_ad9680_jesd/gt_rxcharisk_in] + connect_bd_net -net axi_daq2_gt_rx_gt_disperr [get_bd_pins axi_daq2_gt/rx_gt_disperr] [get_bd_pins axi_ad9680_jesd/gt_rxdisperr_in] + connect_bd_net -net axi_daq2_gt_rx_gt_notintable [get_bd_pins axi_daq2_gt/rx_gt_notintable] [get_bd_pins axi_ad9680_jesd/gt_rxnotintable_in] + connect_bd_net -net axi_daq2_gt_rx_gt_data [get_bd_pins axi_daq2_gt/rx_gt_data] [get_bd_pins axi_ad9680_jesd/gt_rxdata_in] + connect_bd_net -net axi_daq2_gt_rx_rst_done [get_bd_pins axi_daq2_gt/rx_rst_done] [get_bd_pins axi_ad9680_jesd/rx_reset_done] + connect_bd_net -net axi_daq2_gt_rx_ip_comma_align [get_bd_pins axi_daq2_gt/rx_ip_comma_align] [get_bd_pins axi_ad9680_jesd/rxencommaalign_out] + connect_bd_net -net axi_daq2_gt_rx_ip_sync [get_bd_pins axi_daq2_gt/rx_ip_sync] [get_bd_pins axi_ad9680_jesd/rx_sync] + connect_bd_net -net axi_daq2_gt_rx_ip_sof [get_bd_pins axi_daq2_gt/rx_ip_sof] [get_bd_pins axi_ad9680_jesd/rx_start_of_frame] + connect_bd_net -net axi_daq2_gt_rx_ip_data [get_bd_pins axi_daq2_gt/rx_ip_data] [get_bd_pins axi_ad9680_jesd/rx_tdata] + connect_bd_net -net axi_daq2_gt_rx_data [get_bd_pins axi_daq2_gt/rx_data] [get_bd_pins axi_ad9680_core/rx_data] + connect_bd_net -net axi_ad9680_adc_clk [get_bd_pins axi_ad9680_core/adc_clk] [get_bd_pins axi_ad9680_dma/fifo_wr_clk] + connect_bd_net -net axi_ad9680_adc_enable_0 [get_bd_pins axi_ad9680_core/adc_enable_0] [get_bd_ports adc_enable_0] + connect_bd_net -net axi_ad9680_adc_valid_0 [get_bd_pins axi_ad9680_core/adc_valid_0] [get_bd_ports adc_valid_0] + connect_bd_net -net axi_ad9680_adc_data_0 [get_bd_pins axi_ad9680_core/adc_data_0] [get_bd_ports adc_data_0] + connect_bd_net -net axi_ad9680_adc_enable_1 [get_bd_pins axi_ad9680_core/adc_enable_1] [get_bd_ports adc_enable_1] + connect_bd_net -net axi_ad9680_adc_valid_1 [get_bd_pins axi_ad9680_core/adc_valid_1] [get_bd_ports adc_valid_1] + connect_bd_net -net axi_ad9680_adc_data_1 [get_bd_pins axi_ad9680_core/adc_data_1] [get_bd_ports adc_data_1] + connect_bd_net -net axi_ad9680_adc_dwr [get_bd_ports adc_dwr] [get_bd_pins axi_ad9680_dma/fifo_wr_en] + connect_bd_net -net axi_ad9680_adc_dsync [get_bd_ports adc_dsync] [get_bd_pins axi_ad9680_dma/fifo_wr_sync] + connect_bd_net -net axi_ad9680_adc_ddata [get_bd_ports adc_ddata] [get_bd_pins axi_ad9680_dma/fifo_wr_din] + connect_bd_net -net axi_ad9680_adc_dovf [get_bd_pins axi_ad9680_core/adc_dovf] [get_bd_pins axi_ad9680_dma/fifo_wr_overflow] + connect_bd_net -net axi_ad9680_dma_irq [get_bd_pins axi_ad9680_dma/irq] [get_bd_pins sys_concat_intc/In2] + + # dac/adc clocks + + connect_bd_net -net axi_ad9144_dac_clk [get_bd_ports dac_clk] + connect_bd_net -net axi_ad9680_adc_clk [get_bd_ports adc_clk] + + # interconnect (cpu) + + connect_bd_intf_net -intf_net axi_cpu_interconnect_m07_axi [get_bd_intf_pins axi_cpu_interconnect/M07_AXI] [get_bd_intf_pins axi_ad9144_dma/s_axi] + connect_bd_intf_net -intf_net axi_cpu_interconnect_m08_axi [get_bd_intf_pins axi_cpu_interconnect/M08_AXI] [get_bd_intf_pins axi_ad9144_core/s_axi] + connect_bd_intf_net -intf_net axi_cpu_interconnect_m09_axi [get_bd_intf_pins axi_cpu_interconnect/M09_AXI] [get_bd_intf_pins axi_ad9144_jesd/s_axi] + connect_bd_intf_net -intf_net axi_cpu_interconnect_m10_axi [get_bd_intf_pins axi_cpu_interconnect/M10_AXI] [get_bd_intf_pins axi_ad9680_dma/s_axi] + connect_bd_intf_net -intf_net axi_cpu_interconnect_m11_axi [get_bd_intf_pins axi_cpu_interconnect/M11_AXI] [get_bd_intf_pins axi_ad9680_core/s_axi] + connect_bd_intf_net -intf_net axi_cpu_interconnect_m12_axi [get_bd_intf_pins axi_cpu_interconnect/M12_AXI] [get_bd_intf_pins axi_ad9680_jesd/s_axi] + connect_bd_intf_net -intf_net axi_cpu_interconnect_m13_axi [get_bd_intf_pins axi_cpu_interconnect/M13_AXI] [get_bd_intf_pins axi_daq2_gt/s_axi] + connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M07_ACLK] $sys_100m_clk_source + connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M08_ACLK] $sys_100m_clk_source + connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M09_ACLK] $sys_100m_clk_source + connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M10_ACLK] $sys_100m_clk_source + connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M11_ACLK] $sys_100m_clk_source + connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M12_ACLK] $sys_100m_clk_source + connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M13_ACLK] $sys_100m_clk_source + connect_bd_net -net sys_100m_clk [get_bd_pins axi_daq2_gt/s_axi_aclk] + connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9144_core/s_axi_aclk] + connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9144_jesd/s_axi_aclk] + connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9144_dma/s_axi_aclk] + connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9680_core/s_axi_aclk] + connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9680_jesd/s_axi_aclk] + connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9680_dma/s_axi_aclk] + connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M07_ARESETN] $sys_100m_resetn_source + connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M08_ARESETN] $sys_100m_resetn_source + connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M09_ARESETN] $sys_100m_resetn_source + connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M10_ARESETN] $sys_100m_resetn_source + connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M11_ARESETN] $sys_100m_resetn_source + connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M12_ARESETN] $sys_100m_resetn_source + connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M13_ARESETN] $sys_100m_resetn_source + connect_bd_net -net sys_100m_resetn [get_bd_pins axi_daq2_gt/s_axi_aresetn] + connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9144_core/s_axi_aresetn] + connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9144_jesd/s_axi_aresetn] + connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9144_dma/s_axi_aresetn] + connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9680_core/s_axi_aresetn] + connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9680_jesd/s_axi_aresetn] + connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9680_dma/s_axi_aresetn] + +if {$sys_zynq == 0} { + + connect_bd_intf_net -intf_net axi_cpu_interconnect_m14_axi [get_bd_intf_pins axi_cpu_interconnect/M14_AXI] [get_bd_intf_pins axi_daq2_spi/axi_lite] + connect_bd_intf_net -intf_net axi_cpu_interconnect_m15_axi [get_bd_intf_pins axi_cpu_interconnect/M15_AXI] [get_bd_intf_pins axi_daq2_gpio/s_axi] + connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M14_ACLK] $sys_100m_clk_source + connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M15_ACLK] $sys_100m_clk_source + connect_bd_net -net sys_100m_clk [get_bd_pins axi_daq2_spi/s_axi_aclk] + connect_bd_net -net sys_100m_clk [get_bd_pins axi_daq2_spi/ext_spi_clk] + connect_bd_net -net sys_100m_clk [get_bd_pins axi_daq2_gpio/s_axi_aclk] + connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M14_ARESETN] $sys_100m_resetn_source + connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M15_ARESETN] $sys_100m_resetn_source + connect_bd_net -net sys_100m_resetn [get_bd_pins axi_daq2_spi/s_axi_aresetn] + connect_bd_net -net sys_100m_resetn [get_bd_pins axi_daq2_gpio/s_axi_aresetn] + + connect_bd_net -net axi_daq2_spi_irq [get_bd_pins axi_daq2_spi/ip2intc_irpt] [get_bd_pins sys_concat_intc/In5] + connect_bd_net -net axi_daq2_gpio_irq [get_bd_pins axi_daq2_gpio/ip2intc_irpt] [get_bd_pins sys_concat_intc/In6] +} + + # gt uses hp3, and 100MHz clock for both DRP and AXI4 + +if {$sys_zynq == 0} { + + connect_bd_intf_net -intf_net axi_mem_interconnect_s08_axi [get_bd_intf_pins axi_mem_interconnect/S08_AXI] [get_bd_intf_pins axi_daq2_gt/m_axi] + connect_bd_net -net sys_100m_clk [get_bd_pins axi_mem_interconnect/S08_ACLK] $sys_100m_clk_source + connect_bd_net -net sys_100m_clk [get_bd_pins axi_daq2_gt/m_axi_aclk] + connect_bd_net -net sys_100m_clk [get_bd_pins axi_daq2_gt/drp_clk] + connect_bd_net -net sys_100m_resetn [get_bd_pins axi_mem_interconnect/S08_ARESETN] $sys_100m_resetn_source + connect_bd_net -net sys_100m_resetn [get_bd_pins axi_daq2_gt/m_axi_aresetn] + +} else { + + connect_bd_intf_net -intf_net axi_daq2_gt_interconnect_m00_axi [get_bd_intf_pins axi_daq2_gt_interconnect/M00_AXI] [get_bd_intf_pins sys_ps7/S_AXI_HP3] + connect_bd_intf_net -intf_net axi_daq2_gt_interconnect_s00_axi [get_bd_intf_pins axi_daq2_gt_interconnect/S00_AXI] [get_bd_intf_pins axi_daq2_gt/m_axi] + connect_bd_net -net sys_100m_clk [get_bd_pins axi_daq2_gt_interconnect/ACLK] $sys_100m_clk_source + connect_bd_net -net sys_100m_clk [get_bd_pins axi_daq2_gt_interconnect/M00_ACLK] $sys_100m_clk_source + connect_bd_net -net sys_100m_clk [get_bd_pins axi_daq2_gt_interconnect/S00_ACLK] $sys_100m_clk_source + connect_bd_net -net sys_100m_clk [get_bd_pins sys_ps7/S_AXI_HP3_ACLK] + connect_bd_net -net sys_100m_clk [get_bd_pins axi_daq2_gt/m_axi_aclk] + connect_bd_net -net sys_100m_clk [get_bd_pins axi_daq2_gt/drp_clk] + connect_bd_net -net sys_100m_resetn [get_bd_pins axi_daq2_gt_interconnect/ARESETN] $sys_100m_resetn_source + connect_bd_net -net sys_100m_resetn [get_bd_pins axi_daq2_gt_interconnect/M00_ARESETN] $sys_100m_resetn_source + connect_bd_net -net sys_100m_resetn [get_bd_pins axi_daq2_gt_interconnect/S00_ARESETN] $sys_100m_resetn_source + connect_bd_net -net sys_100m_resetn [get_bd_pins axi_daq2_gt/m_axi_aresetn] +} + + # memory interconnects share the same clock (fclk2) + +if {$sys_zynq == 1} { + set sys_fmc_dma_sync_reset [create_bd_cell -type ip -vlnv analog.com:user:util_sync_reset:1.0 sys_fmc_dma_sync_reset] + + set sys_fmc_dma_clk_source [get_bd_pins sys_ps7/FCLK_CLK2] + set sys_fmc_dma_resetn_source [get_bd_pins sys_fmc_dma_sync_reset/sync_resetn] + + connect_bd_net -net sys_fmc_dma_clk [get_bd_pins sys_fmc_dma_sync_reset/clk] + connect_bd_net -net sys_fmc_dma_async_reset \ + [get_bd_pins sys_fmc_dma_sync_reset/async_resetn] \ + [get_bd_pins sys_ps7/FCLK_RESET2_N] + + connect_bd_net -net sys_fmc_dma_clk $sys_fmc_dma_clk_source + connect_bd_net -net sys_fmc_dma_resetn $sys_fmc_dma_resetn_source +} + + # interconnect (mem/dac) + +if {$sys_zynq == 0} { + + connect_bd_intf_net -intf_net axi_mem_interconnect_s09_axi [get_bd_intf_pins axi_mem_interconnect/S09_AXI] [get_bd_intf_pins axi_ad9144_dma/m_src_axi] + connect_bd_net -net sys_200m_clk [get_bd_pins axi_mem_interconnect/S09_ACLK] $sys_200m_clk_source + connect_bd_net -net sys_200m_clk [get_bd_pins axi_ad9144_dma/m_src_axi_aclk] + connect_bd_net -net sys_200m_resetn [get_bd_pins axi_mem_interconnect/S09_ARESETN] $sys_200m_resetn_source + connect_bd_net -net sys_200m_resetn [get_bd_pins axi_ad9144_dma/m_src_axi_aresetn] + + connect_bd_intf_net -intf_net axi_mem_interconnect_s10_axi [get_bd_intf_pins axi_mem_interconnect/S10_AXI] [get_bd_intf_pins axi_ad9680_dma/m_dest_axi] + connect_bd_net -net sys_200m_clk [get_bd_pins axi_mem_interconnect/S10_ACLK] $sys_200m_clk_source + connect_bd_net -net sys_200m_clk [get_bd_pins axi_ad9680_dma/m_dest_axi_aclk] + connect_bd_net -net sys_200m_resetn [get_bd_pins axi_mem_interconnect/S10_ARESETN] $sys_200m_resetn_source + connect_bd_net -net sys_200m_resetn [get_bd_pins axi_ad9680_dma/m_dest_axi_aresetn] + +} else { + + connect_bd_intf_net -intf_net axi_ad9144_dma_interconnect_m00_axi [get_bd_intf_pins axi_ad9144_dma_interconnect/M00_AXI] [get_bd_intf_pins sys_ps7/S_AXI_HP1] + connect_bd_intf_net -intf_net axi_ad9144_dma_interconnect_s00_axi [get_bd_intf_pins axi_ad9144_dma_interconnect/S00_AXI] [get_bd_intf_pins axi_ad9144_dma/m_src_axi] + connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_ad9144_dma_interconnect/ACLK] $sys_fmc_dma_clk_source + connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_ad9144_dma_interconnect/M00_ACLK] $sys_fmc_dma_clk_source + connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_ad9144_dma_interconnect/S00_ACLK] $sys_fmc_dma_clk_source + connect_bd_net -net sys_fmc_dma_clk [get_bd_pins sys_ps7/S_AXI_HP1_ACLK] + connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_ad9144_dma/m_src_axi_aclk] + connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_ad9144_dma_interconnect/ARESETN] $sys_fmc_dma_resetn_source + connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_ad9144_dma_interconnect/M00_ARESETN] $sys_fmc_dma_resetn_source + connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_ad9144_dma_interconnect/S00_ARESETN] $sys_fmc_dma_resetn_source + connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_ad9144_dma/m_src_axi_aresetn] + + connect_bd_intf_net -intf_net axi_ad9680_dma_interconnect_m00_axi [get_bd_intf_pins axi_ad9680_dma_interconnect/M00_AXI] [get_bd_intf_pins sys_ps7/S_AXI_HP2] + connect_bd_intf_net -intf_net axi_ad9680_dma_interconnect_s00_axi [get_bd_intf_pins axi_ad9680_dma_interconnect/S00_AXI] [get_bd_intf_pins axi_ad9680_dma/m_dest_axi] + connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_ad9680_dma_interconnect/ACLK] $sys_fmc_dma_clk_source + connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_ad9680_dma_interconnect/M00_ACLK] $sys_fmc_dma_clk_source + connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_ad9680_dma_interconnect/S00_ACLK] $sys_fmc_dma_clk_source + connect_bd_net -net sys_fmc_dma_clk [get_bd_pins sys_ps7/S_AXI_HP2_ACLK] + connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_ad9680_dma/m_dest_axi_aclk] + connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_ad9680_dma_interconnect/ARESETN] $sys_fmc_dma_resetn_source + connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_ad9680_dma_interconnect/M00_ARESETN] $sys_fmc_dma_resetn_source + connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_ad9680_dma_interconnect/S00_ARESETN] $sys_fmc_dma_resetn_source + connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_ad9680_dma/m_dest_axi_aresetn] +} + + # ila + + set ila_jesd_rx_mon [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:3.0 ila_jesd_rx_mon] + set_property -dict [list CONFIG.C_NUM_OF_PROBES {4}] $ila_jesd_rx_mon + set_property -dict [list CONFIG.C_PROBE0_WIDTH {334}] $ila_jesd_rx_mon + set_property -dict [list CONFIG.C_PROBE1_WIDTH {6}] $ila_jesd_rx_mon + set_property -dict [list CONFIG.C_PROBE2_WIDTH {128}] $ila_jesd_rx_mon + set_property -dict [list CONFIG.C_PROBE3_WIDTH {128}] $ila_jesd_rx_mon + + connect_bd_net -net axi_daq2_gt_rx_mon_data [get_bd_pins axi_daq2_gt/rx_mon_data] + connect_bd_net -net axi_daq2_gt_rx_mon_trigger [get_bd_pins axi_daq2_gt/rx_mon_trigger] + connect_bd_net -net axi_daq2_gt_rx_clk [get_bd_pins ila_jesd_rx_mon/CLK] + connect_bd_net -net axi_daq2_gt_rx_mon_data [get_bd_pins ila_jesd_rx_mon/PROBE0] + connect_bd_net -net axi_daq2_gt_rx_mon_trigger [get_bd_pins ila_jesd_rx_mon/PROBE1] + connect_bd_net -net axi_daq2_gt_rx_data [get_bd_pins ila_jesd_rx_mon/PROBE2] + connect_bd_net -net axi_ad9680_adc_ddata [get_bd_pins ila_jesd_rx_mon/PROBE3] + + set ila_jesd_tx_mon [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:3.0 ila_jesd_tx_mon] + set_property -dict [list CONFIG.C_NUM_OF_PROBES {2}] $ila_jesd_tx_mon + set_property -dict [list CONFIG.C_PROBE0_WIDTH {150}] $ila_jesd_tx_mon + set_property -dict [list CONFIG.C_PROBE1_WIDTH {6}] $ila_jesd_tx_mon + + connect_bd_net -net axi_daq2_gt_tx_mon_data [get_bd_pins axi_daq2_gt/tx_mon_data] + connect_bd_net -net axi_daq2_gt_tx_mon_trigger [get_bd_pins axi_daq2_gt/tx_mon_trigger] + connect_bd_net -net axi_daq2_gt_tx_clk [get_bd_pins ila_jesd_tx_mon/CLK] + connect_bd_net -net axi_daq2_gt_tx_mon_data [get_bd_pins ila_jesd_tx_mon/PROBE0] + connect_bd_net -net axi_daq2_gt_tx_mon_trigger [get_bd_pins ila_jesd_tx_mon/PROBE1] + + # address map + + create_bd_addr_seg -range 0x00010000 -offset 0x44A00000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad9144_core/s_axi/axi_lite] SEG_data_ad9144_core + create_bd_addr_seg -range 0x00010000 -offset 0x44A10000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad9680_core/s_axi/axi_lite] SEG_data_ad9680_core + create_bd_addr_seg -range 0x00010000 -offset 0x44A60000 $sys_addr_cntrl_space [get_bd_addr_segs axi_daq2_gt/s_axi/axi_lite] SEG_data_daq2_gt + create_bd_addr_seg -range 0x00001000 -offset 0x44A90000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad9144_jesd/s_axi/Reg] SEG_data_ad9144_jesd + create_bd_addr_seg -range 0x00001000 -offset 0x44A91000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad9680_jesd/s_axi/Reg] SEG_data_ad9680_jesd + create_bd_addr_seg -range 0x00010000 -offset 0x7c400000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad9680_dma/s_axi/axi_lite] SEG_data_ad9680_dma + create_bd_addr_seg -range 0x00010000 -offset 0x7c420000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad9144_dma/s_axi/axi_lite] SEG_data_ad9144_dma + +if {$sys_zynq == 0} { + + create_bd_addr_seg -range 0x00010000 -offset 0x40000000 $sys_addr_cntrl_space [get_bd_addr_segs axi_daq2_gpio/S_AXI/Reg] SEG_data_daq2_gpio + create_bd_addr_seg -range 0x00010000 -offset 0x44A70000 $sys_addr_cntrl_space [get_bd_addr_segs axi_daq2_spi/axi_lite/Reg] SEG_data_daq2_spi +} + +if {$sys_zynq == 0} { + + create_bd_addr_seg -range $sys_mem_size -offset 0x80000000 [get_bd_addr_spaces axi_ad9144_dma/m_src_axi] [get_bd_addr_segs axi_ddr_cntrl/memmap/memaddr] SEG_axi_ddr_cntrl + create_bd_addr_seg -range $sys_mem_size -offset 0x80000000 [get_bd_addr_spaces axi_ad9680_dma/m_dest_axi] [get_bd_addr_segs axi_ddr_cntrl/memmap/memaddr] SEG_axi_ddr_cntrl + create_bd_addr_seg -range $sys_mem_size -offset 0x80000000 [get_bd_addr_spaces axi_daq2_gt/m_axi] [get_bd_addr_segs axi_ddr_cntrl/memmap/memaddr] SEG_axi_ddr_cntrl + +} else { + + create_bd_addr_seg -range $sys_mem_size -offset 0x00000000 [get_bd_addr_spaces axi_ad9144_dma/m_src_axi] [get_bd_addr_segs sys_ps7/S_AXI_HP1/HP1_DDR_LOWOCM] SEG_sys_ps7_hp1_ddr_lowocm + create_bd_addr_seg -range $sys_mem_size -offset 0x00000000 [get_bd_addr_spaces axi_ad9680_dma/m_dest_axi] [get_bd_addr_segs sys_ps7/S_AXI_HP2/HP2_DDR_LOWOCM] SEG_sys_ps7_hp2_ddr_lowocm + create_bd_addr_seg -range $sys_mem_size -offset 0x00000000 [get_bd_addr_spaces axi_daq2_gt/m_axi] [get_bd_addr_segs sys_ps7/S_AXI_HP3/HP3_DDR_LOWOCM] SEG_sys_ps7_hp3_ddr_lowocm +} + diff --git a/projects/fmcadc3/common/fmcadc3_spi.v b/projects/fmcadc3/common/fmcadc3_spi.v new file mode 100644 index 000000000..eb3e7d91e --- /dev/null +++ b/projects/fmcadc3/common/fmcadc3_spi.v @@ -0,0 +1,109 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2011(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module daq2_spi ( + + spi_csn, + spi_clk, + spi_mosi, + spi_miso, + + spi_sdio); + + // 4 wire + + input [ 2:0] spi_csn; + input spi_clk; + input spi_mosi; + output spi_miso; + + // 3 wire + + inout spi_sdio; + + // internal registers + + reg [ 5:0] spi_count = 'd0; + reg spi_rd_wr_n = 'd0; + reg spi_enable = 'd0; + + // internal signals + + wire spi_csn_s; + wire spi_enable_s; + + // check on rising edge and change on falling edge + + assign spi_csn_s = & spi_csn; + assign spi_enable_s = spi_enable & ~spi_csn_s; + + always @(posedge spi_clk or posedge spi_csn_s) begin + if (spi_csn_s == 1'b1) begin + spi_count <= 6'd0; + spi_rd_wr_n <= 1'd0; + end else begin + spi_count <= spi_count + 1'b1; + if (spi_count == 6'd0) begin + spi_rd_wr_n <= spi_mosi; + end + end + end + + always @(negedge spi_clk or posedge spi_csn_s) begin + if (spi_csn_s == 1'b1) begin + spi_enable <= 1'b0; + end else begin + if (spi_count == 6'd16) begin + spi_enable <= spi_rd_wr_n; + end + end + end + + // io butter + + IOBUF i_iobuf_sdio ( + .T (spi_enable_s), + .I (spi_mosi), + .O (spi_miso), + .IO (spi_sdio)); + +endmodule + +// *************************************************************************** +// *************************************************************************** diff --git a/projects/fmcadc3/zc706/system_bd.tcl b/projects/fmcadc3/zc706/system_bd.tcl new file mode 100644 index 000000000..177e09f7f --- /dev/null +++ b/projects/fmcadc3/zc706/system_bd.tcl @@ -0,0 +1,58 @@ + +source $ad_hdl_dir/projects/common/zc706/zc706_system_bd.tcl +source $ad_hdl_dir/projects/common/zc706/zc706_system_plddr3.tcl +source ../common/daq2_bd.tcl + +set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_SRC {64}] $axi_ad9144_dma +set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_DEST {128}] $axi_ad9144_dma +set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_SRC {64}] $axi_ad9680_dma +set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_DEST {64}] $axi_ad9680_dma + +p_plddr3_fifo [current_bd_instance .] plddr3_fifo 128 + +set DDR3 [create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 DDR3] +set sys_clk [create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 sys_clk] + +connect_bd_intf_net -intf_net DDR3 [get_bd_intf_ports DDR3] [get_bd_intf_pins plddr3_fifo/DDR3] +connect_bd_intf_net -intf_net sys_clk [get_bd_intf_ports sys_clk] [get_bd_intf_pins plddr3_fifo/sys_clk] + +delete_bd_objs [get_bd_nets axi_ad9680_adc_clk] +delete_bd_objs [get_bd_nets axi_ad9680_adc_dwr] +delete_bd_objs [get_bd_nets axi_ad9680_adc_ddata] +delete_bd_objs [get_bd_nets axi_ad9680_adc_dsync] +delete_bd_objs [get_bd_nets axi_ad9680_adc_dovf] + +connect_bd_net -net [get_bd_nets axi_daq2_gt_rx_rst] [get_bd_pins plddr3_fifo/adc_rst] [get_bd_pins axi_daq2_gt/rx_rst] +connect_bd_net -net [get_bd_nets sys_fmc_dma_resetn] [get_bd_pins plddr3_fifo/dma_rstn] [get_bd_pins sys_fmc_dma_sync_reset/sync_resetn] +connect_bd_net -net axi_ad9680_dma_xfer_req [get_bd_pins axi_ad9680_dma/fifo_wr_xfer_req] [get_bd_pins plddr3_fifo/axi_xfer_req] + +connect_bd_net -net axi_ad9680_adc_clk [get_bd_pins axi_ad9680_core/adc_clk] [get_bd_pins plddr3_fifo/adc_clk] +connect_bd_net -net axi_ad9680_adc_dovf [get_bd_pins axi_ad9680_core/adc_dovf] [get_bd_pins plddr3_fifo/adc_wovf] +connect_bd_net -net axi_ad9680_adc_dwr [get_bd_ports adc_dwr] [get_bd_pins plddr3_fifo/adc_wr] +connect_bd_net -net axi_ad9680_adc_ddata [get_bd_ports adc_ddata] [get_bd_pins plddr3_fifo/adc_wdata] + +connect_bd_net -net axi_ad9680_dma_clk [get_bd_pins plddr3_fifo/dma_clk] [get_bd_pins axi_ad9680_dma/fifo_wr_clk] +connect_bd_net -net axi_ad9680_dma_dwr [get_bd_pins plddr3_fifo/dma_wr] [get_bd_pins axi_ad9680_dma/fifo_wr_en] +connect_bd_net -net axi_ad9680_dma_ddata [get_bd_pins plddr3_fifo/dma_wdata] [get_bd_pins axi_ad9680_dma/fifo_wr_din] +connect_bd_net -net axi_ad9680_dma_dovf [get_bd_pins plddr3_fifo/dma_wovf] [get_bd_pins axi_ad9680_dma/fifo_wr_overflow] +connect_bd_net -net axi_ad9680_adc_dsync [get_bd_ports adc_dsync] [get_bd_pins axi_ad9680_dma/fifo_wr_sync] + +connect_bd_net -net axi_ad9680_adc_clk [get_bd_ports adc_clk] +connect_bd_net -net axi_ad9680_adc_ddata [get_bd_pins ila_jesd_rx_mon/PROBE3] + +set ila_dma_mon [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:3.0 ila_dma_mon] +set_property -dict [list CONFIG.C_NUM_OF_PROBES {4}] $ila_dma_mon +set_property -dict [list CONFIG.C_PROBE0_WIDTH {1}] $ila_dma_mon +set_property -dict [list CONFIG.C_PROBE1_WIDTH {1}] $ila_dma_mon +set_property -dict [list CONFIG.C_PROBE2_WIDTH {64}] $ila_dma_mon +set_property -dict [list CONFIG.C_PROBE3_WIDTH {5}] $ila_dma_mon + +connect_bd_net -net axi_ad9680_dma_clk [get_bd_pins ila_dma_mon/clk] +connect_bd_net -net axi_ad9680_dma_dwr [get_bd_pins ila_dma_mon/probe0] +connect_bd_net -net axi_ad9680_dma_xfer_req [get_bd_pins ila_dma_mon/probe1] +connect_bd_net -net axi_ad9680_dma_ddata [get_bd_pins ila_dma_mon/probe2] +connect_bd_net -net axi_xfer_status [get_bd_pins ila_dma_mon/probe3] [get_bd_pins plddr3_fifo/axi_xfer_status] + + +create_bd_addr_seg -range 0x40000000 -offset 0x80000000 [get_bd_addr_spaces plddr3_fifo/axi_fifo2s/axi] [get_bd_addr_segs plddr3_fifo/axi_ddr_cntrl/memmap/memaddr] SEG_axi_ddr_cntrl_memaddr + diff --git a/projects/fmcadc3/zc706/system_constr.xdc b/projects/fmcadc3/zc706/system_constr.xdc new file mode 100644 index 000000000..ff599d9e8 --- /dev/null +++ b/projects/fmcadc3/zc706/system_constr.xdc @@ -0,0 +1,74 @@ + +# daq2 + +set_property -dict {PACKAGE_PIN AA8 } [get_ports rx_ref_clk_p] ; ## B20 FMC_HPC_GBTCLK1_M2C_P +set_property -dict {PACKAGE_PIN AA7 } [get_ports rx_ref_clk_n] ; ## B21 FMC_HPC_GBTCLK1_M2C_N +set_property -dict {PACKAGE_PIN AE8 } [get_ports rx_data_p[0]] ; ## A10 FMC_HPC_DP3_M2C_P +set_property -dict {PACKAGE_PIN AE7 } [get_ports rx_data_n[0]] ; ## A11 FMC_HPC_DP3_M2C_N +set_property -dict {PACKAGE_PIN AH10} [get_ports rx_data_p[1]] ; ## C06 FMC_HPC_DP0_M2C_P +set_property -dict {PACKAGE_PIN AH9 } [get_ports rx_data_n[1]] ; ## C07 FMC_HPC_DP0_M2C_N +set_property -dict {PACKAGE_PIN AG8 } [get_ports rx_data_p[2]] ; ## A06 FMC_HPC_DP2_M2C_P +set_property -dict {PACKAGE_PIN AG7 } [get_ports rx_data_n[2]] ; ## A07 FMC_HPC_DP2_M2C_N +set_property -dict {PACKAGE_PIN AJ8 } [get_ports rx_data_p[3]] ; ## A02 FMC_HPC_DP1_M2C_P +set_property -dict {PACKAGE_PIN AJ7 } [get_ports rx_data_n[3]] ; ## A03 FMC_HPC_DP1_M2C_N +set_property -dict {PACKAGE_PIN AG21 IOSTANDARD LVDS_25} [get_ports rx_sync_p] ; ## D08 FMC_HPC_LA01_CC_P +set_property -dict {PACKAGE_PIN AH21 IOSTANDARD LVDS_25} [get_ports rx_sync_n] ; ## D09 FMC_HPC_LA01_CC_N +set_property -dict {PACKAGE_PIN AH19 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_sysref_p] ; ## G09 FMC_HPC_LA03_P +set_property -dict {PACKAGE_PIN AJ19 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_sysref_n] ; ## G10 FMC_HPC_LA03_N + +set_property -dict {PACKAGE_PIN AD10} [get_ports tx_ref_clk_p] ; ## D04 FMC_HPC_GBTCLK0_M2C_P +set_property -dict {PACKAGE_PIN AD9 } [get_ports tx_ref_clk_n] ; ## D05 FMC_HPC_GBTCLK0_M2C_N +set_property -dict {PACKAGE_PIN AK2 } [get_ports tx_data_p[0]] ; ## A30 FMC_HPC_DP3_C2M_P +set_property -dict {PACKAGE_PIN AK1 } [get_ports tx_data_n[0]] ; ## A31 FMC_HPC_DP3_C2M_N +set_property -dict {PACKAGE_PIN AJ4 } [get_ports tx_data_p[1]] ; ## A26 FMC_HPC_DP2_C2M_P +set_property -dict {PACKAGE_PIN AJ3 } [get_ports tx_data_n[1]] ; ## A27 FMC_HPC_DP2_C2M_N +set_property -dict {PACKAGE_PIN AK6 } [get_ports tx_data_p[2]] ; ## A22 FMC_HPC_DP1_C2M_P +set_property -dict {PACKAGE_PIN AK5 } [get_ports tx_data_n[2]] ; ## A23 FMC_HPC_DP1_C2M_N +set_property -dict {PACKAGE_PIN AK10} [get_ports tx_data_p[3]] ; ## C02 FMC_HPC_DP0_C2M_P +set_property -dict {PACKAGE_PIN AK9 } [get_ports tx_data_n[3]] ; ## C03 FMC_HPC_DP0_C2M_N +set_property -dict {PACKAGE_PIN AK17 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports tx_sync_p] ; ## H07 FMC_HPC_LA02_P +set_property -dict {PACKAGE_PIN AK18 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports tx_sync_n] ; ## H08 FMC_HPC_LA02_N +set_property -dict {PACKAGE_PIN AJ20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports tx_sysref_p] ; ## H10 FMC_HPC_LA04_P +set_property -dict {PACKAGE_PIN AK20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports tx_sysref_n] ; ## H11 FMC_HPC_LA04_N + +set_property -dict {PACKAGE_PIN AH23 IOSTANDARD LVCMOS25} [get_ports spi_csn_clk] ; ## D11 FMC_HPC_LA05_P +set_property -dict {PACKAGE_PIN AG24 IOSTANDARD LVCMOS25} [get_ports spi_csn_dac] ; ## C14 FMC_HPC_LA10_P +set_property -dict {PACKAGE_PIN AE21 IOSTANDARD LVCMOS25} [get_ports spi_csn_adc] ; ## D15 FMC_HPC_LA09_N +set_property -dict {PACKAGE_PIN AH24 IOSTANDARD LVCMOS25} [get_ports spi_clk] ; ## D12 FMC_HPC_LA05_N +set_property -dict {PACKAGE_PIN AD21 IOSTANDARD LVCMOS25} [get_ports spi_sdio] ; ## D14 FMC_HPC_LA09_P + +set_property -dict {PACKAGE_PIN AH22 IOSTANDARD LVCMOS25} [get_ports clkd_reset] ; ## C11 FMC_HPC_LA06_N +set_property -dict {PACKAGE_PIN AF19 IOSTANDARD LVCMOS25} [get_ports clkd_sync] ; ## G12 FMC_HPC_LA08_P +set_property -dict {PACKAGE_PIN AG19 IOSTANDARD LVCMOS25} [get_ports clkd_pd] ; ## G13 FMC_HPC_LA08_N +set_property -dict {PACKAGE_PIN AG25 IOSTANDARD LVCMOS25} [get_ports dac_reset] ; ## C15 FMC_HPC_LA10_N +set_property -dict {PACKAGE_PIN AF24 IOSTANDARD LVCMOS25} [get_ports dac_txen] ; ## G16 FMC_HPC_LA12_N +set_property -dict {PACKAGE_PIN AG22 IOSTANDARD LVCMOS25} [get_ports adc_pd] ; ## C10 FMC_HPC_LA06_P + +set_property -dict {PACKAGE_PIN AA22 IOSTANDARD LVCMOS25} [get_ports clkd_status[0]] ; ## D17 FMC_HPC_LA13_P +set_property -dict {PACKAGE_PIN AA23 IOSTANDARD LVCMOS25} [get_ports clkd_status[1]] ; ## D18 FMC_HPC_LA13_N +set_property -dict {PACKAGE_PIN AF23 IOSTANDARD LVCMOS25} [get_ports dac_irq] ; ## G15 FMC_HPC_LA12_P +set_property -dict {PACKAGE_PIN AD23 IOSTANDARD LVCMOS25} [get_ports adc_fda] ; ## H16 FMC_HPC_LA11_P +set_property -dict {PACKAGE_PIN AE23 IOSTANDARD LVCMOS25} [get_ports adc_fdb] ; ## H17 FMC_HPC_LA11_N + +# clocks + +create_clock -name tx_ref_clk -period 2.00 [get_ports tx_ref_clk_p] +create_clock -name rx_ref_clk -period 2.00 [get_ports rx_ref_clk_p] +create_clock -name tx_div_clk -period 4.00 [get_nets i_system_wrapper/system_i/axi_daq2_gt_tx_clk] +create_clock -name rx_div_clk -period 4.00 [get_nets i_system_wrapper/system_i/axi_daq2_gt_rx_clk] +create_clock -name fmc_dma_clk -period 5.00 [get_pins i_system_wrapper/system_i/sys_ps7/FCLK_CLK2] +create_clock -name pl_ddr_clk -period 5.00 [get_pins i_system_wrapper/system_i/plddr3_fifo/axi_ddr_cntrl/ui_clk] +create_clock -name pl_dma_clk -period 15.62 [get_pins i_system_wrapper/system_i/plddr3_fifo/axi_ddr_cntrl/ui_addn_clk_0] + +set_clock_groups -asynchronous -group {tx_div_clk} +set_clock_groups -asynchronous -group {rx_div_clk} +set_clock_groups -asynchronous -group {fmc_dma_clk} +set_clock_groups -asynchronous -group {pl_ddr_clk} +set_clock_groups -asynchronous -group {pl_dma_clk} + +set_false_path -through [get_pins i_system_wrapper/system_i/axi_daq2_gt/inst/i_up_gt/i_drp_rst_reg/i_rst_reg/PRE] +set_false_path -through [get_pins i_system_wrapper/system_i/axi_daq2_gt/inst/i_up_gt/i_gt_pll_rst_reg/i_rst_reg/PRE] +set_false_path -through [get_pins i_system_wrapper/system_i/axi_daq2_gt/inst/i_up_gt/i_gt_rx_rst_reg/i_rst_reg/PRE] +set_false_path -through [get_pins i_system_wrapper/system_i/axi_daq2_gt/inst/i_up_gt/i_gt_tx_rst_reg/i_rst_reg/PRE] +set_false_path -through [get_pins i_system_wrapper/system_i/axi_daq2_gt/inst/i_up_gt/i_rx_rst_reg/i_rst_reg/PRE] +set_false_path -through [get_pins i_system_wrapper/system_i/axi_daq2_gt/inst/i_up_gt/i_tx_rst_reg/i_rst_reg/PRE] diff --git a/projects/fmcadc3/zc706/system_project.tcl b/projects/fmcadc3/zc706/system_project.tcl new file mode 100644 index 000000000..73e0af659 --- /dev/null +++ b/projects/fmcadc3/zc706/system_project.tcl @@ -0,0 +1,17 @@ + + + +source ../../scripts/adi_env.tcl +source $ad_hdl_dir/projects/scripts/adi_project.tcl + +adi_project_create daq2_zc706 +adi_project_files daq2_zc706 [list \ + "../common/daq2_spi.v" \ + "system_top.v" \ + "system_constr.xdc"\ + "$ad_hdl_dir/library/common/ad_iobuf.v" \ + "$ad_hdl_dir/projects/common/zc706/zc706_system_constr.xdc" ] + +adi_project_run daq2_zc706 + + diff --git a/projects/fmcadc3/zc706/system_top.v b/projects/fmcadc3/zc706/system_top.v new file mode 100644 index 000000000..17917e91c --- /dev/null +++ b/projects/fmcadc3/zc706/system_top.v @@ -0,0 +1,537 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2011(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module system_top ( + + sys_clk_p, + sys_clk_n, + + DDR3_addr, + DDR3_ba, + DDR3_cas_n, + DDR3_ck_n, + DDR3_ck_p, + DDR3_cke, + DDR3_cs_n, + DDR3_dm, + DDR3_dq, + DDR3_dqs_n, + DDR3_dqs_p, + DDR3_odt, + DDR3_ras_n, + DDR3_reset_n, + DDR3_we_n, + + DDR_addr, + DDR_ba, + DDR_cas_n, + DDR_ck_n, + DDR_ck_p, + DDR_cke, + DDR_cs_n, + DDR_dm, + DDR_dq, + DDR_dqs_n, + DDR_dqs_p, + DDR_odt, + DDR_ras_n, + DDR_reset_n, + DDR_we_n, + + FIXED_IO_ddr_vrn, + FIXED_IO_ddr_vrp, + FIXED_IO_mio, + FIXED_IO_ps_clk, + FIXED_IO_ps_porb, + FIXED_IO_ps_srstb, + + gpio_bd, + + hdmi_out_clk, + hdmi_vsync, + hdmi_hsync, + hdmi_data_e, + hdmi_data, + + spdif, + + iic_scl, + iic_sda, + + rx_ref_clk_p, + rx_ref_clk_n, + rx_sysref_p, + rx_sysref_n, + rx_sync_p, + rx_sync_n, + rx_data_p, + rx_data_n, + + tx_ref_clk_p, + tx_ref_clk_n, + tx_sysref_p, + tx_sysref_n, + tx_sync_p, + tx_sync_n, + tx_data_p, + tx_data_n, + + adc_fdb, + adc_fda, + dac_irq, + clkd_status, + + adc_pd, + dac_txen, + dac_reset, + clkd_pd, + clkd_sync, + clkd_reset, + + spi_csn_clk, + spi_csn_dac, + spi_csn_adc, + spi_clk, + spi_sdio); + + input sys_clk_p; + input sys_clk_n; + + output [13:0] DDR3_addr; + output [ 2:0] DDR3_ba; + output DDR3_cas_n; + output [ 0:0] DDR3_ck_n; + output [ 0:0] DDR3_ck_p; + output [ 0:0] DDR3_cke; + output [ 0:0] DDR3_cs_n; + output [ 7:0] DDR3_dm; + inout [63:0] DDR3_dq; + inout [ 7:0] DDR3_dqs_n; + inout [ 7:0] DDR3_dqs_p; + output [ 0:0] DDR3_odt; + output DDR3_ras_n; + output DDR3_reset_n; + output DDR3_we_n; + + inout [14:0] DDR_addr; + inout [ 2:0] DDR_ba; + inout DDR_cas_n; + inout DDR_ck_n; + inout DDR_ck_p; + inout DDR_cke; + inout DDR_cs_n; + inout [ 3:0] DDR_dm; + inout [31:0] DDR_dq; + inout [ 3:0] DDR_dqs_n; + inout [ 3:0] DDR_dqs_p; + inout DDR_odt; + inout DDR_ras_n; + inout DDR_reset_n; + inout DDR_we_n; + + inout FIXED_IO_ddr_vrn; + inout FIXED_IO_ddr_vrp; + inout [53:0] FIXED_IO_mio; + inout FIXED_IO_ps_clk; + inout FIXED_IO_ps_porb; + inout FIXED_IO_ps_srstb; + + inout [14:0] gpio_bd; + + output hdmi_out_clk; + output hdmi_vsync; + output hdmi_hsync; + output hdmi_data_e; + output [23:0] hdmi_data; + + output spdif; + + inout iic_scl; + inout iic_sda; + + input rx_ref_clk_p; + input rx_ref_clk_n; + input rx_sysref_p; + input rx_sysref_n; + output rx_sync_p; + output rx_sync_n; + input [ 3:0] rx_data_p; + input [ 3:0] rx_data_n; + + input tx_ref_clk_p; + input tx_ref_clk_n; + input tx_sysref_p; + input tx_sysref_n; + input tx_sync_p; + input tx_sync_n; + output [ 3:0] tx_data_p; + output [ 3:0] tx_data_n; + + inout adc_fdb; + inout adc_fda; + inout dac_irq; + inout [ 1:0] clkd_status; + + inout adc_pd; + inout dac_txen; + inout dac_reset; + inout clkd_pd; + inout clkd_sync; + inout clkd_reset; + + output spi_csn_clk; + output spi_csn_dac; + output spi_csn_adc; + output spi_clk; + inout spi_sdio; + + // internal registers + + reg dac_drd = 'd0; + reg [63:0] dac_ddata_0 = 'd0; + reg [63:0] dac_ddata_1 = 'd0; + reg [63:0] dac_ddata_2 = 'd0; + reg [63:0] dac_ddata_3 = 'd0; + reg adc_dsync = 'd0; + reg adc_dwr = 'd0; + reg [127:0] adc_ddata = 'd0; + + // internal signals + + wire [42:0] gpio_i; + wire [42:0] gpio_o; + wire [42:0] gpio_t; + wire rx_ref_clk; + wire rx_sysref; + wire rx_sync; + wire tx_ref_clk; + wire tx_sysref; + wire tx_sync; + wire [ 2:0] spi_csn; + wire spi_mosi; + wire spi_miso; + wire dac_clk; + wire [127:0] dac_ddata; + wire dac_enable_0; + wire dac_enable_1; + wire dac_enable_2; + wire dac_enable_3; + wire dac_valid_0; + wire dac_valid_1; + wire dac_valid_2; + wire dac_valid_3; + wire adc_clk; + wire [63:0] adc_data_0; + wire [63:0] adc_data_1; + wire adc_enable_0; + wire adc_enable_1; + wire adc_valid_0; + wire adc_valid_1; + + // adc-dac data + + always @(posedge dac_clk) begin + case ({dac_enable_1, dac_enable_0}) + 2'b11: begin + dac_drd <= dac_valid_0 & dac_valid_1; + dac_ddata_0[63:48] <= dac_ddata[111: 96]; + dac_ddata_0[47:32] <= dac_ddata[ 79: 64]; + dac_ddata_0[31:16] <= dac_ddata[ 47: 32]; + dac_ddata_0[15: 0] <= dac_ddata[ 15: 0]; + dac_ddata_1[63:48] <= dac_ddata[127:112]; + dac_ddata_1[47:32] <= dac_ddata[ 95: 80]; + dac_ddata_1[31:16] <= dac_ddata[ 63: 48]; + dac_ddata_1[15: 0] <= dac_ddata[ 31: 16]; + dac_ddata_2 <= 64'd0; + dac_ddata_3 <= 64'd0; + end + 2'b10: begin + dac_drd <= dac_valid_1 & ~dac_drd; + dac_ddata_0 <= 64'd0; + if (dac_drd == 1'b1) begin + dac_ddata_1[63:48] <= dac_ddata[127:112]; + dac_ddata_1[47:32] <= dac_ddata[111: 96]; + dac_ddata_1[31:16] <= dac_ddata[ 95: 80]; + dac_ddata_1[15: 0] <= dac_ddata[ 79: 64]; + end else begin + dac_ddata_1[63:48] <= dac_ddata[ 63: 48]; + dac_ddata_1[47:32] <= dac_ddata[ 47: 32]; + dac_ddata_1[31:16] <= dac_ddata[ 31: 16]; + dac_ddata_1[15: 0] <= dac_ddata[ 15: 0]; + end + dac_ddata_2 <= 64'd0; + dac_ddata_3 <= 64'd0; + end + 2'b01: begin + dac_drd <= dac_valid_0 & ~dac_drd; + if (dac_drd == 1'b1) begin + dac_ddata_0[63:48] <= dac_ddata[127:112]; + dac_ddata_0[47:32] <= dac_ddata[111: 96]; + dac_ddata_0[31:16] <= dac_ddata[ 95: 80]; + dac_ddata_0[15: 0] <= dac_ddata[ 79: 64]; + end else begin + dac_ddata_0[63:48] <= dac_ddata[ 63: 48]; + dac_ddata_0[47:32] <= dac_ddata[ 47: 32]; + dac_ddata_0[31:16] <= dac_ddata[ 31: 16]; + dac_ddata_0[15: 0] <= dac_ddata[ 15: 0]; + end + dac_ddata_1 <= 64'd0; + dac_ddata_2 <= 64'd0; + dac_ddata_3 <= 64'd0; + end + default: begin + dac_drd <= 1'b0; + dac_ddata_0 <= 64'd0; + dac_ddata_1 <= 64'd0; + dac_ddata_2 <= 64'd0; + dac_ddata_3 <= 64'd0; + end + endcase + end + + always @(posedge adc_clk) begin + case ({adc_enable_1, adc_enable_0}) + 2'b11: begin + adc_dsync <= 1'b1; + adc_dwr <= adc_valid_1 & adc_valid_0; + adc_ddata[127:112] <= adc_data_1[63:48]; + adc_ddata[111: 96] <= adc_data_0[63:48]; + adc_ddata[ 95: 80] <= adc_data_1[47:32]; + adc_ddata[ 79: 64] <= adc_data_0[47:32]; + adc_ddata[ 63: 48] <= adc_data_1[31:16]; + adc_ddata[ 47: 32] <= adc_data_0[31:16]; + adc_ddata[ 31: 16] <= adc_data_1[15: 0]; + adc_ddata[ 15: 0] <= adc_data_0[15: 0]; + end + 2'b10: begin + adc_dsync <= 1'b1; + adc_dwr <= adc_valid_1 & ~adc_dwr; + adc_ddata[127:112] <= adc_data_1[63:48]; + adc_ddata[111: 96] <= adc_data_1[47:32]; + adc_ddata[ 95: 80] <= adc_data_1[31:16]; + adc_ddata[ 79: 64] <= adc_data_1[15: 0]; + adc_ddata[ 63: 48] <= adc_ddata[127:112]; + adc_ddata[ 47: 32] <= adc_ddata[111: 96]; + adc_ddata[ 31: 16] <= adc_ddata[ 95: 80]; + adc_ddata[ 15: 0] <= adc_ddata[ 79: 64]; + end + 2'b01: begin + adc_dsync <= 1'b1; + adc_dwr <= adc_valid_0 & ~adc_dwr; + adc_ddata[127:112] <= adc_data_0[63:48]; + adc_ddata[111: 96] <= adc_data_0[47:32]; + adc_ddata[ 95: 80] <= adc_data_0[31:16]; + adc_ddata[ 79: 64] <= adc_data_0[15: 0]; + adc_ddata[ 63: 48] <= adc_ddata[127:112]; + adc_ddata[ 47: 32] <= adc_ddata[111: 96]; + adc_ddata[ 31: 16] <= adc_ddata[ 95: 80]; + adc_ddata[ 15: 0] <= adc_ddata[ 79: 64]; + end + default: begin + adc_dsync <= 1'b0; + adc_dwr <= 1'b0; + adc_ddata <= 128'd0; + end + endcase + end + + // spi + + assign spi_csn_adc = spi_csn[2]; + assign spi_csn_dac = spi_csn[1]; + assign spi_csn_clk = spi_csn[0]; + + // instantiations + + IBUFDS_GTE2 i_ibufds_rx_ref_clk ( + .CEB (1'd0), + .I (rx_ref_clk_p), + .IB (rx_ref_clk_n), + .O (rx_ref_clk), + .ODIV2 ()); + + IBUFDS i_ibufds_rx_sysref ( + .I (rx_sysref_p), + .IB (rx_sysref_n), + .O (rx_sysref)); + + OBUFDS i_obufds_rx_sync ( + .I (rx_sync), + .O (rx_sync_p), + .OB (rx_sync_n)); + + IBUFDS_GTE2 i_ibufds_tx_ref_clk ( + .CEB (1'd0), + .I (tx_ref_clk_p), + .IB (tx_ref_clk_n), + .O (tx_ref_clk), + .ODIV2 ()); + + IBUFDS i_ibufds_tx_sysref ( + .I (tx_sysref_p), + .IB (tx_sysref_n), + .O (tx_sysref)); + + IBUFDS i_ibufds_tx_sync ( + .I (tx_sync_p), + .IB (tx_sync_n), + .O (tx_sync)); + + daq2_spi i_spi ( + .spi_csn (spi_csn), + .spi_clk (spi_clk), + .spi_mosi (spi_mosi), + .spi_miso (spi_miso), + .spi_sdio (spi_sdio)); + + ad_iobuf #(.DATA_WIDTH(26)) i_iobuf ( + .dt ({gpio_t[42:32], gpio_t[14:0]}), + .di ({gpio_o[42:32], gpio_o[14:0]}), + .do ({gpio_i[42:32], gpio_i[14:0]}), + .dio ({ adc_pd, // 42 + dac_txen, // 41 + dac_reset, // 40 + clkd_pd, // 39 + clkd_sync, // 38 + clkd_reset, // 37 + adc_fdb, // 36 + adc_fda, // 35 + dac_irq, // 34 + clkd_status, // 32 + gpio_bd})); // 0 + + system_wrapper i_system_wrapper ( + .DDR3_addr (DDR3_addr), + .DDR3_ba (DDR3_ba), + .DDR3_cas_n (DDR3_cas_n), + .DDR3_ck_n (DDR3_ck_n), + .DDR3_ck_p (DDR3_ck_p), + .DDR3_cke (DDR3_cke), + .DDR3_cs_n (DDR3_cs_n), + .DDR3_dm (DDR3_dm), + .DDR3_dq (DDR3_dq), + .DDR3_dqs_n (DDR3_dqs_n), + .DDR3_dqs_p (DDR3_dqs_p), + .DDR3_odt (DDR3_odt), + .DDR3_ras_n (DDR3_ras_n), + .DDR3_reset_n (DDR3_reset_n), + .DDR3_we_n (DDR3_we_n), + .DDR_addr (DDR_addr), + .DDR_ba (DDR_ba), + .DDR_cas_n (DDR_cas_n), + .DDR_ck_n (DDR_ck_n), + .DDR_ck_p (DDR_ck_p), + .DDR_cke (DDR_cke), + .DDR_cs_n (DDR_cs_n), + .DDR_dm (DDR_dm), + .DDR_dq (DDR_dq), + .DDR_dqs_n (DDR_dqs_n), + .DDR_dqs_p (DDR_dqs_p), + .DDR_odt (DDR_odt), + .DDR_ras_n (DDR_ras_n), + .DDR_reset_n (DDR_reset_n), + .DDR_we_n (DDR_we_n), + .FIXED_IO_ddr_vrn (FIXED_IO_ddr_vrn), + .FIXED_IO_ddr_vrp (FIXED_IO_ddr_vrp), + .FIXED_IO_mio (FIXED_IO_mio), + .FIXED_IO_ps_clk (FIXED_IO_ps_clk), + .FIXED_IO_ps_porb (FIXED_IO_ps_porb), + .FIXED_IO_ps_srstb (FIXED_IO_ps_srstb), + .GPIO_I (gpio_i), + .GPIO_O (gpio_o), + .GPIO_T (gpio_t), + .adc_clk (adc_clk), + .adc_data_0 (adc_data_0), + .adc_data_1 (adc_data_1), + .adc_ddata (adc_ddata), + .adc_dsync (adc_dsync), + .adc_dwr (adc_dwr), + .adc_enable_0 (adc_enable_0), + .adc_enable_1 (adc_enable_1), + .adc_valid_0 (adc_valid_0), + .adc_valid_1 (adc_valid_1), + .dac_clk (dac_clk), + .dac_ddata (dac_ddata), + .dac_ddata_0 (dac_ddata_0), + .dac_ddata_1 (dac_ddata_1), + .dac_ddata_2 (dac_ddata_2), + .dac_ddata_3 (dac_ddata_3), + .dac_drd (dac_drd), + .dac_enable_0 (dac_enable_0), + .dac_enable_1 (dac_enable_1), + .dac_enable_2 (dac_enable_2), + .dac_enable_3 (dac_enable_3), + .dac_valid_0 (dac_valid_0), + .dac_valid_1 (dac_valid_1), + .dac_valid_2 (dac_valid_2), + .dac_valid_3 (dac_valid_3), + .hdmi_data (hdmi_data), + .hdmi_data_e (hdmi_data_e), + .hdmi_hsync (hdmi_hsync), + .hdmi_out_clk (hdmi_out_clk), + .hdmi_vsync (hdmi_vsync), + .iic_main_scl_io (iic_scl), + .iic_main_sda_io (iic_sda), + .rx_data_n (rx_data_n), + .rx_data_p (rx_data_p), + .rx_ref_clk (rx_ref_clk), + .rx_sync (rx_sync), + .rx_sysref (rx_sysref), + .spdif (spdif), + .spi_clk_i (spi_clk), + .spi_clk_o (spi_clk), + .spi_csn_i (spi_csn), + .spi_csn_o (spi_csn), + .spi_sdi_i (spi_miso), + .spi_sdo_i (spi_mosi), + .spi_sdo_o (spi_mosi), + .sys_clk_clk_n (sys_clk_n), + .sys_clk_clk_p (sys_clk_p), + .tx_data_n (tx_data_n), + .tx_data_p (tx_data_p), + .tx_ref_clk (tx_ref_clk), + .tx_sync (tx_sync), + .tx_sysref (tx_sysref)); + +endmodule + +// *************************************************************************** +// *************************************************************************** From 07f5795255874eb82544f21dfc5cc33979e6a516 Mon Sep 17 00:00:00 2001 From: Rejeesh Kutty Date: Mon, 22 Sep 2014 11:17:20 -0400 Subject: [PATCH 04/42] fmcadc3: initial updates --- library/axi_ad9234/axi_ad9234.v | 8 +- library/axi_ad9234/axi_ad9234_channel.v | 4 +- library/axi_ad9234/axi_ad9234_if.v | 2 +- library/axi_ad9234/axi_ad9234_ip.tcl | 18 +- library/axi_ad9234/axi_ad9234_pnmon.v | 2 +- projects/fmcadc3/common/fmcadc3_bd.tcl | 531 +++++++++------------- projects/fmcadc3/common/fmcadc3_spi.v | 10 +- projects/fmcadc3/zc706/system_bd.tcl | 59 ++- projects/fmcadc3/zc706/system_constr.xdc | 98 ++-- projects/fmcadc3/zc706/system_project.tcl | 8 +- projects/fmcadc3/zc706/system_top.v | 395 +++++++--------- 11 files changed, 484 insertions(+), 651 deletions(-) diff --git a/library/axi_ad9234/axi_ad9234.v b/library/axi_ad9234/axi_ad9234.v index efcf4c366..657573eff 100644 --- a/library/axi_ad9234/axi_ad9234.v +++ b/library/axi_ad9234/axi_ad9234.v @@ -39,7 +39,7 @@ `timescale 1ns/100ps -module axi_ad9680 ( +module axi_ad9234 ( // jesd interface // rx_clk is (line-rate/40) @@ -187,7 +187,7 @@ module axi_ad9680 ( // main (device interface) - axi_ad9680_if i_if ( + axi_ad9234_if i_if ( .rx_clk (rx_clk), .rx_data (rx_data), .adc_clk (adc_clk), @@ -200,7 +200,7 @@ module axi_ad9680 ( // channel - axi_ad9680_channel #(.IQSEL(0), .CHID(0)) i_channel_0 ( + axi_ad9234_channel #(.IQSEL(0), .CHID(0)) i_channel_0 ( .adc_clk (adc_clk), .adc_rst (adc_rst), .adc_data (adc_data_a_s), @@ -221,7 +221,7 @@ module axi_ad9680 ( // channel - axi_ad9680_channel #(.IQSEL(1), .CHID(1)) i_channel_1 ( + axi_ad9234_channel #(.IQSEL(1), .CHID(1)) i_channel_1 ( .adc_clk (adc_clk), .adc_rst (adc_rst), .adc_data (adc_data_b_s), diff --git a/library/axi_ad9234/axi_ad9234_channel.v b/library/axi_ad9234/axi_ad9234_channel.v index b80395265..89913a6e3 100644 --- a/library/axi_ad9234/axi_ad9234_channel.v +++ b/library/axi_ad9234/axi_ad9234_channel.v @@ -40,7 +40,7 @@ `timescale 1ns/100ps -module axi_ad9680_channel ( +module axi_ad9234_channel ( // adc interface @@ -110,7 +110,7 @@ module axi_ad9680_channel ( // instantiations - axi_ad9680_pnmon i_pnmon ( + axi_ad9234_pnmon i_pnmon ( .adc_clk (adc_clk), .adc_data (adc_data), .adc_pn_oos (adc_pn_oos_s), diff --git a/library/axi_ad9234/axi_ad9234_if.v b/library/axi_ad9234/axi_ad9234_if.v index c658b6b84..5f91208f0 100644 --- a/library/axi_ad9234/axi_ad9234_if.v +++ b/library/axi_ad9234/axi_ad9234_if.v @@ -40,7 +40,7 @@ `timescale 1ns/100ps -module axi_ad9680_if ( +module axi_ad9234_if ( // jesd interface // rx_clk is (line-rate/40) diff --git a/library/axi_ad9234/axi_ad9234_ip.tcl b/library/axi_ad9234/axi_ad9234_ip.tcl index 9426b317e..b1b75291f 100644 --- a/library/axi_ad9234/axi_ad9234_ip.tcl +++ b/library/axi_ad9234/axi_ad9234_ip.tcl @@ -3,8 +3,8 @@ source ../scripts/adi_env.tcl source $ad_hdl_dir/library/scripts/adi_ip.tcl -adi_ip_create axi_ad9680 -adi_ip_files axi_ad9680 [list \ +adi_ip_create axi_ad9234 +adi_ip_files axi_ad9234 [list \ "$ad_hdl_dir/library/common/ad_rst.v" \ "$ad_hdl_dir/library/common/ad_pnmon.v" \ "$ad_hdl_dir/library/common/ad_datafmt.v" \ @@ -16,14 +16,14 @@ adi_ip_files axi_ad9680 [list \ "$ad_hdl_dir/library/common/up_delay_cntrl.v" \ "$ad_hdl_dir/library/common/up_adc_common.v" \ "$ad_hdl_dir/library/common/up_adc_channel.v" \ - "axi_ad9680_pnmon.v" \ - "axi_ad9680_channel.v" \ - "axi_ad9680_if.v" \ - "axi_ad9680.v" ] + "axi_ad9234_pnmon.v" \ + "axi_ad9234_channel.v" \ + "axi_ad9234_if.v" \ + "axi_ad9234.v" ] -adi_ip_properties axi_ad9680 -adi_ip_constraints axi_ad9680 [list \ - "axi_ad9680_constr.xdc" ] +adi_ip_properties axi_ad9234 +adi_ip_constraints axi_ad9234 [list \ + "axi_ad9234_constr.xdc" ] ipx::save_core [ipx::current_core] diff --git a/library/axi_ad9234/axi_ad9234_pnmon.v b/library/axi_ad9234/axi_ad9234_pnmon.v index 4e64ca0fb..3e8f620c8 100644 --- a/library/axi_ad9234/axi_ad9234_pnmon.v +++ b/library/axi_ad9234/axi_ad9234_pnmon.v @@ -40,7 +40,7 @@ `timescale 1ns/100ps -module axi_ad9680_pnmon ( +module axi_ad9234_pnmon ( // adc interface diff --git a/projects/fmcadc3/common/fmcadc3_bd.tcl b/projects/fmcadc3/common/fmcadc3_bd.tcl index d7f93512c..aa5c9c71e 100644 --- a/projects/fmcadc3/common/fmcadc3_bd.tcl +++ b/projects/fmcadc3/common/fmcadc3_bd.tcl @@ -1,8 +1,19 @@ - # daq2 + # fmcadc3 + +if {$sys_zynq == 0} { set spi_csn_i [create_bd_port -dir I -from 2 -to 0 spi_csn_i] set spi_csn_o [create_bd_port -dir O -from 2 -to 0 spi_csn_o] + +} else { + + set spi_csn_0 [create_bd_port -dir O spi_csn_0] + set spi_csn_1 [create_bd_port -dir O spi_csn_1] + set spi_csn_2 [create_bd_port -dir O spi_csn_2] + set spi_csn_i [create_bd_port -dir I spi_csn_i] +} + set spi_clk_i [create_bd_port -dir I spi_clk_i] set spi_clk_o [create_bd_port -dir O spi_clk_o] set spi_sdo_i [create_bd_port -dir I spi_sdo_i] @@ -12,41 +23,22 @@ set rx_ref_clk [create_bd_port -dir I rx_ref_clk] set rx_sync [create_bd_port -dir O rx_sync] set rx_sysref [create_bd_port -dir I rx_sysref] - set rx_data_p [create_bd_port -dir I -from 3 -to 0 rx_data_p] - set rx_data_n [create_bd_port -dir I -from 3 -to 0 rx_data_n] - - set tx_ref_clk [create_bd_port -dir I tx_ref_clk] - set tx_sync [create_bd_port -dir I tx_sync] - set tx_sysref [create_bd_port -dir I tx_sysref] - set tx_data_p [create_bd_port -dir O -from 3 -to 0 tx_data_p] - set tx_data_n [create_bd_port -dir O -from 3 -to 0 tx_data_n] + set rx_data_p [create_bd_port -dir I -from 7 -to 0 rx_data_p] + set rx_data_n [create_bd_port -dir I -from 7 -to 0 rx_data_n] if {$sys_zynq == 0} { - set gpio_ctl_i [create_bd_port -dir I -from 5 -to 0 gpio_ctl_i] - set gpio_ctl_o [create_bd_port -dir O -from 5 -to 0 gpio_ctl_o] - set gpio_ctl_t [create_bd_port -dir O -from 5 -to 0 gpio_ctl_t] + set gpio_ctl_i [create_bd_port -dir I gpio_ctl_i] + set gpio_ctl_o [create_bd_port -dir O gpio_ctl_o] + set gpio_ctl_t [create_bd_port -dir O gpio_ctl_t] set gpio_status_i [create_bd_port -dir I -from 4 -to 0 gpio_status_i] set gpio_status_o [create_bd_port -dir O -from 4 -to 0 gpio_status_o] set gpio_status_t [create_bd_port -dir O -from 4 -to 0 gpio_status_t] } - set dac_clk [create_bd_port -dir O dac_clk] - set dac_valid_0 [create_bd_port -dir O dac_valid_0] - set dac_enable_0 [create_bd_port -dir O dac_enable_0] - set dac_ddata_0 [create_bd_port -dir I -from 63 -to 0 dac_ddata_0] - set dac_valid_1 [create_bd_port -dir O dac_valid_1] - set dac_enable_1 [create_bd_port -dir O dac_enable_1] - set dac_ddata_1 [create_bd_port -dir I -from 63 -to 0 dac_ddata_1] - set dac_valid_2 [create_bd_port -dir O dac_valid_2] - set dac_enable_2 [create_bd_port -dir O dac_enable_2] - set dac_ddata_2 [create_bd_port -dir I -from 63 -to 0 dac_ddata_2] - set dac_valid_3 [create_bd_port -dir O dac_valid_3] - set dac_enable_3 [create_bd_port -dir O dac_enable_3] - set dac_ddata_3 [create_bd_port -dir I -from 63 -to 0 dac_ddata_3] - set dac_drd [create_bd_port -dir I dac_drd] - set dac_ddata [create_bd_port -dir O -from 127 -to 0 dac_ddata] - + set gt_data [create_bd_port -dir O -from 255 -to 0 gt_data] + set gt_data_0 [create_bd_port -dir I -from 127 -to 0 gt_data_0] + set gt_data_1 [create_bd_port -dir I -from 127 -to 0 gt_data_1] set adc_clk [create_bd_port -dir O adc_clk] set adc_enable_0 [create_bd_port -dir O adc_enable_0] set adc_valid_0 [create_bd_port -dir O adc_valid_0] @@ -54,102 +46,81 @@ if {$sys_zynq == 0} { set adc_enable_1 [create_bd_port -dir O adc_enable_1] set adc_valid_1 [create_bd_port -dir O adc_valid_1] set adc_data_1 [create_bd_port -dir O -from 63 -to 0 adc_data_1] + set adc_enable_2 [create_bd_port -dir O adc_enable_2] + set adc_valid_2 [create_bd_port -dir O adc_valid_2] + set adc_data_2 [create_bd_port -dir O -from 63 -to 0 adc_data_2] + set adc_enable_3 [create_bd_port -dir O adc_enable_3] + set adc_valid_3 [create_bd_port -dir O adc_valid_3] + set adc_data_3 [create_bd_port -dir O -from 63 -to 0 adc_data_3] set adc_dwr [create_bd_port -dir I adc_dwr] set adc_dsync [create_bd_port -dir I adc_dsync] - set adc_ddata [create_bd_port -dir I -from 127 -to 0 adc_ddata] - - # dac peripherals - - set axi_ad9144_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9144:1.0 axi_ad9144_core] - set_property -dict [list CONFIG.PCORE_QUAD_DUAL_N {0}] $axi_ad9144_core - - set axi_ad9144_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:5.1 axi_ad9144_jesd] - set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {1}] $axi_ad9144_jesd - set_property -dict [list CONFIG.C_LANES {4}] $axi_ad9144_jesd - - set axi_ad9144_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad9144_dma] - set_property -dict [list CONFIG.C_DMA_TYPE_SRC {0}] $axi_ad9144_dma - set_property -dict [list CONFIG.C_DMA_TYPE_DEST {2}] $axi_ad9144_dma - set_property -dict [list CONFIG.PCORE_ID {1}] $axi_ad9144_dma - set_property -dict [list CONFIG.C_AXI_SLICE_SRC {0}] $axi_ad9144_dma - set_property -dict [list CONFIG.C_AXI_SLICE_DEST {0}] $axi_ad9144_dma - set_property -dict [list CONFIG.C_CLKS_ASYNC_REQ_SRC {1}] $axi_ad9144_dma - set_property -dict [list CONFIG.C_DMA_LENGTH_WIDTH {24}] $axi_ad9144_dma - set_property -dict [list CONFIG.C_2D_TRANSFER {0}] $axi_ad9144_dma - set_property -dict [list CONFIG.C_CYCLIC {1}] $axi_ad9144_dma - set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_SRC {128}] $axi_ad9144_dma - set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_DEST {128}] $axi_ad9144_dma - -if {$sys_zynq == 1} { - - set axi_ad9144_dma_interconnect [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_ad9144_dma_interconnect] - set_property -dict [list CONFIG.NUM_MI {1}] $axi_ad9144_dma_interconnect -} + set adc_ddata [create_bd_port -dir I -from 255 -to 0 adc_ddata] # adc peripherals - set axi_ad9680_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9680:1.0 axi_ad9680_core] + set axi_ad9234_core_0 [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9234:1.0 axi_ad9234_core_0] + set axi_ad9234_core_1 [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9234:1.0 axi_ad9234_core_1] - set axi_ad9680_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:5.1 axi_ad9680_jesd] - set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {0}] $axi_ad9680_jesd - set_property -dict [list CONFIG.C_LANES {4}] $axi_ad9680_jesd + set axi_ad9234_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:5.2 axi_ad9234_jesd] + set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {0}] $axi_ad9234_jesd + set_property -dict [list CONFIG.C_LANES {8}] $axi_ad9234_jesd - set axi_ad9680_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad9680_dma] - set_property -dict [list CONFIG.C_DMA_TYPE_SRC {2}] $axi_ad9680_dma - set_property -dict [list CONFIG.C_DMA_TYPE_DEST {0}] $axi_ad9680_dma - set_property -dict [list CONFIG.PCORE_ID {0}] $axi_ad9680_dma - set_property -dict [list CONFIG.C_AXI_SLICE_SRC {0}] $axi_ad9680_dma - set_property -dict [list CONFIG.C_AXI_SLICE_DEST {0}] $axi_ad9680_dma - set_property -dict [list CONFIG.C_CLKS_ASYNC_DEST_REQ {1}] $axi_ad9680_dma - set_property -dict [list CONFIG.C_SYNC_TRANSFER_START {1}] $axi_ad9680_dma - set_property -dict [list CONFIG.C_DMA_LENGTH_WIDTH {24}] $axi_ad9680_dma - set_property -dict [list CONFIG.C_2D_TRANSFER {0}] $axi_ad9680_dma - set_property -dict [list CONFIG.C_CYCLIC {0}] $axi_ad9680_dma - set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_SRC {128}] $axi_ad9680_dma - set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_DEST {128}] $axi_ad9680_dma + set axi_ad9234_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad9234_dma] + set_property -dict [list CONFIG.C_DMA_TYPE_SRC {2}] $axi_ad9234_dma + set_property -dict [list CONFIG.C_DMA_TYPE_DEST {0}] $axi_ad9234_dma + set_property -dict [list CONFIG.PCORE_ID {0}] $axi_ad9234_dma + set_property -dict [list CONFIG.C_AXI_SLICE_SRC {0}] $axi_ad9234_dma + set_property -dict [list CONFIG.C_AXI_SLICE_DEST {0}] $axi_ad9234_dma + set_property -dict [list CONFIG.C_CLKS_ASYNC_DEST_REQ {1}] $axi_ad9234_dma + set_property -dict [list CONFIG.C_SYNC_TRANSFER_START {1}] $axi_ad9234_dma + set_property -dict [list CONFIG.C_DMA_LENGTH_WIDTH {24}] $axi_ad9234_dma + set_property -dict [list CONFIG.C_2D_TRANSFER {0}] $axi_ad9234_dma + set_property -dict [list CONFIG.C_CYCLIC {0}] $axi_ad9234_dma + set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_SRC {256}] $axi_ad9234_dma + set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_DEST {256}] $axi_ad9234_dma if {$sys_zynq == 1} { - set axi_ad9680_dma_interconnect [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_ad9680_dma_interconnect] - set_property -dict [list CONFIG.NUM_MI {1}] $axi_ad9680_dma_interconnect + set axi_ad9234_dma_interconnect [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_ad9234_dma_interconnect] + set_property -dict [list CONFIG.NUM_MI {1}] $axi_ad9234_dma_interconnect } # dac/adc common gt/gpio - set axi_daq2_gt [create_bd_cell -type ip -vlnv analog.com:user:axi_jesd_gt:1.0 axi_daq2_gt] - set_property -dict [list CONFIG.PCORE_NUM_OF_LANES {4}] $axi_daq2_gt + set axi_fmcadc3_gt [create_bd_cell -type ip -vlnv analog.com:user:axi_jesd_gt:1.0 axi_fmcadc3_gt] + set_property -dict [list CONFIG.PCORE_NUM_OF_LANES {8}] $axi_fmcadc3_gt if {$sys_zynq == 1} { - set axi_daq2_gt_interconnect [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_daq2_gt_interconnect] - set_property -dict [list CONFIG.NUM_MI {1}] $axi_daq2_gt_interconnect + set axi_fmcadc3_gt_interconnect [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_fmcadc3_gt_interconnect] + set_property -dict [list CONFIG.NUM_MI {1}] $axi_fmcadc3_gt_interconnect } # gpio and spi if {$sys_zynq == 0} { - set axi_daq2_spi [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_quad_spi:3.1 axi_daq2_spi] - set_property -dict [list CONFIG.C_USE_STARTUP {0}] $axi_daq2_spi - set_property -dict [list CONFIG.C_NUM_SS_BITS {3}] $axi_daq2_spi - set_property -dict [list CONFIG.C_SCK_RATIO {8}] $axi_daq2_spi + set axi_fmcadc3_spi [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_quad_spi:3.1 axi_fmcadc3_spi] + set_property -dict [list CONFIG.C_USE_STARTUP {0}] $axi_fmcadc3_spi + set_property -dict [list CONFIG.C_NUM_SS_BITS {3}] $axi_fmcadc3_spi + set_property -dict [list CONFIG.C_SCK_RATIO {8}] $axi_fmcadc3_spi - set axi_daq2_gpio [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_daq2_gpio] - set_property -dict [list CONFIG.C_IS_DUAL {1}] $axi_daq2_gpio - set_property -dict [list CONFIG.C_GPIO_WIDTH {5}] $axi_daq2_gpio - set_property -dict [list CONFIG.C_GPIO2_WIDTH {6}] $axi_daq2_gpio - set_property -dict [list CONFIG.C_INTERRUPT_PRESENT {1}] $axi_daq2_gpio + set axi_fmcadc3_gpio [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_fmcadc3_gpio] + set_property -dict [list CONFIG.C_IS_DUAL {1}] $axi_fmcadc3_gpio + set_property -dict [list CONFIG.C_GPIO_WIDTH {5}] $axi_fmcadc3_gpio + set_property -dict [list CONFIG.C_GPIO2_WIDTH {1}] $axi_fmcadc3_gpio + set_property -dict [list CONFIG.C_INTERRUPT_PRESENT {1}] $axi_fmcadc3_gpio } # additions to default configuration if {$sys_zynq == 0} { - set_property -dict [list CONFIG.NUM_MI {16}] $axi_cpu_interconnect + set_property -dict [list CONFIG.NUM_MI {14}] $axi_cpu_interconnect } else { - set_property -dict [list CONFIG.NUM_MI {14}] $axi_cpu_interconnect + set_property -dict [list CONFIG.NUM_MI {12}] $axi_cpu_interconnect } if {$sys_zynq == 0} { @@ -160,60 +131,53 @@ if {$sys_zynq == 0} { if {$sys_zynq == 1} { - set_property -dict [list CONFIG.PCW_USE_S_AXI_HP1 {1}] $sys_ps7 set_property -dict [list CONFIG.PCW_USE_S_AXI_HP2 {1}] $sys_ps7 set_property -dict [list CONFIG.PCW_USE_S_AXI_HP3 {1}] $sys_ps7 set_property -dict [list CONFIG.PCW_EN_CLK2_PORT {1}] $sys_ps7 set_property -dict [list CONFIG.PCW_EN_RST2_PORT {1}] $sys_ps7 set_property -dict [list CONFIG.PCW_FPGA2_PERIPHERAL_FREQMHZ {200.0}] $sys_ps7 - set_property -dict [list CONFIG.PCW_GPIO_EMIO_GPIO_IO {43}] $sys_ps7 + set_property -dict [list CONFIG.PCW_GPIO_EMIO_GPIO_IO {38}] $sys_ps7 set_property -dict [list CONFIG.PCW_SPI0_PERIPHERAL_ENABLE {1}] $sys_ps7 set_property -dict [list CONFIG.PCW_SPI0_SPI0_IO {EMIO}] $sys_ps7 - set_property LEFT 42 [get_bd_ports GPIO_I] - set_property LEFT 42 [get_bd_ports GPIO_O] - set_property LEFT 42 [get_bd_ports GPIO_T] + set_property LEFT 37 [get_bd_ports GPIO_I] + set_property LEFT 37 [get_bd_ports GPIO_O] + set_property LEFT 37 [get_bd_ports GPIO_T] } # connections (spi and gpio) if {$sys_zynq == 0} { - connect_bd_net -net spi_csn_i [get_bd_ports spi_csn_i] [get_bd_pins axi_daq2_spi/ss_i] - connect_bd_net -net spi_csn_o [get_bd_ports spi_csn_o] [get_bd_pins axi_daq2_spi/ss_o] - connect_bd_net -net spi_clk_i [get_bd_ports spi_clk_i] [get_bd_pins axi_daq2_spi/sck_i] - connect_bd_net -net spi_clk_o [get_bd_ports spi_clk_o] [get_bd_pins axi_daq2_spi/sck_o] - connect_bd_net -net spi_sdo_i [get_bd_ports spi_sdo_i] [get_bd_pins axi_daq2_spi/io0_i] - connect_bd_net -net spi_sdo_o [get_bd_ports spi_sdo_o] [get_bd_pins axi_daq2_spi/io0_o] - connect_bd_net -net spi_sdi_i [get_bd_ports spi_sdi_i] [get_bd_pins axi_daq2_spi/io1_i] + connect_bd_net -net spi_csn_i [get_bd_ports spi_csn_i] [get_bd_pins axi_fmcadc3_spi/ss_i] + connect_bd_net -net spi_csn_o [get_bd_ports spi_csn_o] [get_bd_pins axi_fmcadc3_spi/ss_o] + connect_bd_net -net spi_clk_i [get_bd_ports spi_clk_i] [get_bd_pins axi_fmcadc3_spi/sck_i] + connect_bd_net -net spi_clk_o [get_bd_ports spi_clk_o] [get_bd_pins axi_fmcadc3_spi/sck_o] + connect_bd_net -net spi_sdo_i [get_bd_ports spi_sdo_i] [get_bd_pins axi_fmcadc3_spi/io0_i] + connect_bd_net -net spi_sdo_o [get_bd_ports spi_sdo_o] [get_bd_pins axi_fmcadc3_spi/io0_o] + connect_bd_net -net spi_sdi_i [get_bd_ports spi_sdi_i] [get_bd_pins axi_fmcadc3_spi/io1_i] } else { - set sys_spi_csn_concat [create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:1.0 sys_spi_csn_concat] - set_property -dict [list CONFIG.NUM_PORTS {3}] $sys_spi_csn_concat - set sys_const_vcc [create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.0 sys_const_vcc] - set_property -dict [list CONFIG.CONST_WIDTH {1} CONFIG.CONST_VAL {1}] $sys_const_vcc - - connect_bd_net -net spi_csn0 [get_bd_pins sys_spi_csn_concat/In2] [get_bd_pins sys_ps7/SPI0_SS_O] - connect_bd_net -net spi_csn1 [get_bd_pins sys_spi_csn_concat/In1] [get_bd_pins sys_ps7/SPI0_SS1_O] - connect_bd_net -net spi_csn2 [get_bd_pins sys_spi_csn_concat/In0] [get_bd_pins sys_ps7/SPI0_SS2_O] - connect_bd_net -net spi_csn_o [get_bd_ports spi_csn_o] [get_bd_pins sys_spi_csn_concat/dout] - connect_bd_net -net spi_csn_i [get_bd_pins sys_const_vcc/const] [get_bd_pins sys_ps7/SPI0_SS_I] - connect_bd_net -net spi_clk_i [get_bd_ports spi_clk_i] [get_bd_pins sys_ps7/SPI0_SCLK_I] - connect_bd_net -net spi_clk_o [get_bd_ports spi_clk_o] [get_bd_pins sys_ps7/SPI0_SCLK_O] - connect_bd_net -net spi_sdo_i [get_bd_ports spi_sdo_i] [get_bd_pins sys_ps7/SPI0_MOSI_I] - connect_bd_net -net spi_sdo_o [get_bd_ports spi_sdo_o] [get_bd_pins sys_ps7/SPI0_MOSI_O] - connect_bd_net -net spi_sdi_i [get_bd_ports spi_sdi_i] [get_bd_pins sys_ps7/SPI0_MISO_I] + connect_bd_net -net spi_csn_0 [get_bd_ports spi_csn_0] [get_bd_pins sys_ps7/SPI0_SS_O] + connect_bd_net -net spi_csn_1 [get_bd_ports spi_csn_1] [get_bd_pins sys_ps7/SPI0_SS1_O] + connect_bd_net -net spi_csn_2 [get_bd_ports spi_csn_2] [get_bd_pins sys_ps7/SPI0_SS2_O] + connect_bd_net -net spi_csn_i [get_bd_ports spi_csn_i] [get_bd_pins sys_ps7/SPI0_SS_I] + connect_bd_net -net spi_clk_i [get_bd_ports spi_clk_i] [get_bd_pins sys_ps7/SPI0_SCLK_I] + connect_bd_net -net spi_clk_o [get_bd_ports spi_clk_o] [get_bd_pins sys_ps7/SPI0_SCLK_O] + connect_bd_net -net spi_sdo_i [get_bd_ports spi_sdo_i] [get_bd_pins sys_ps7/SPI0_MOSI_I] + connect_bd_net -net spi_sdo_o [get_bd_ports spi_sdo_o] [get_bd_pins sys_ps7/SPI0_MOSI_O] + connect_bd_net -net spi_sdi_i [get_bd_ports spi_sdi_i] [get_bd_pins sys_ps7/SPI0_MISO_I] } if {$sys_zynq == 0} { - connect_bd_net -net gpio_status_i [get_bd_ports gpio_status_i] [get_bd_pins axi_daq2_gpio/gpio_io_i] - connect_bd_net -net gpio_status_o [get_bd_ports gpio_status_o] [get_bd_pins axi_daq2_gpio/gpio_io_o] - connect_bd_net -net gpio_status_t [get_bd_ports gpio_status_t] [get_bd_pins axi_daq2_gpio/gpio_io_t] - connect_bd_net -net gpio_ctl_i [get_bd_ports gpio_ctl_i] [get_bd_pins axi_daq2_gpio/gpio2_io_i] - connect_bd_net -net gpio_ctl_o [get_bd_ports gpio_ctl_o] [get_bd_pins axi_daq2_gpio/gpio2_io_o] - connect_bd_net -net gpio_ctl_t [get_bd_ports gpio_ctl_t] [get_bd_pins axi_daq2_gpio/gpio2_io_t] + connect_bd_net -net gpio_status_i [get_bd_ports gpio_status_i] [get_bd_pins axi_fmcadc3_gpio/gpio_io_i] + connect_bd_net -net gpio_status_o [get_bd_ports gpio_status_o] [get_bd_pins axi_fmcadc3_gpio/gpio_io_o] + connect_bd_net -net gpio_status_t [get_bd_ports gpio_status_t] [get_bd_pins axi_fmcadc3_gpio/gpio_io_t] + connect_bd_net -net gpio_ctl_i [get_bd_ports gpio_ctl_i] [get_bd_pins axi_fmcadc3_gpio/gpio2_io_i] + connect_bd_net -net gpio_ctl_o [get_bd_ports gpio_ctl_o] [get_bd_pins axi_fmcadc3_gpio/gpio2_io_o] + connect_bd_net -net gpio_ctl_t [get_bd_ports gpio_ctl_t] [get_bd_pins axi_fmcadc3_gpio/gpio2_io_t] } if {$sys_zynq == 0} { @@ -224,169 +188,128 @@ if {$sys_zynq == 0} { # connections (gt) - connect_bd_net -net axi_daq2_gt_ref_clk_q [get_bd_pins axi_daq2_gt/ref_clk_q] [get_bd_ports rx_ref_clk] - connect_bd_net -net axi_daq2_gt_ref_clk_c [get_bd_pins axi_daq2_gt/ref_clk_c] [get_bd_ports tx_ref_clk] - connect_bd_net -net axi_daq2_gt_rx_data_p [get_bd_pins axi_daq2_gt/rx_data_p] [get_bd_ports rx_data_p] - connect_bd_net -net axi_daq2_gt_rx_data_n [get_bd_pins axi_daq2_gt/rx_data_n] [get_bd_ports rx_data_n] - connect_bd_net -net axi_daq2_gt_rx_sync [get_bd_pins axi_daq2_gt/rx_sync] [get_bd_ports rx_sync] - connect_bd_net -net axi_daq2_gt_rx_ext_sysref [get_bd_pins axi_daq2_gt/rx_ext_sysref] [get_bd_ports rx_sysref] - connect_bd_net -net axi_daq2_gt_tx_data_p [get_bd_pins axi_daq2_gt/tx_data_p] [get_bd_ports tx_data_p] - connect_bd_net -net axi_daq2_gt_tx_data_n [get_bd_pins axi_daq2_gt/tx_data_n] [get_bd_ports tx_data_n] - connect_bd_net -net axi_daq2_gt_tx_sync [get_bd_pins axi_daq2_gt/tx_sync] [get_bd_ports tx_sync] - connect_bd_net -net axi_daq2_gt_tx_ext_sysref [get_bd_pins axi_daq2_gt/tx_ext_sysref] [get_bd_ports tx_sysref] - - # connections (dac) - - connect_bd_net -net axi_daq2_gt_tx_clk [get_bd_pins axi_daq2_gt/tx_clk_g] - connect_bd_net -net axi_daq2_gt_tx_clk [get_bd_pins axi_daq2_gt/tx_clk] - connect_bd_net -net axi_daq2_gt_tx_clk [get_bd_pins axi_ad9144_core/tx_clk] - connect_bd_net -net axi_daq2_gt_tx_clk [get_bd_pins axi_ad9144_jesd/tx_core_clk] - - connect_bd_net -net axi_daq2_gt_tx_rst [get_bd_pins axi_daq2_gt/tx_rst] [get_bd_pins axi_ad9144_jesd/tx_reset] - connect_bd_net -net axi_daq2_gt_tx_sysref [get_bd_pins axi_daq2_gt/tx_sysref] [get_bd_pins axi_ad9144_jesd/tx_sysref] - connect_bd_net -net axi_daq2_gt_tx_gt_charisk [get_bd_pins axi_daq2_gt/tx_gt_charisk] [get_bd_pins axi_ad9144_jesd/gt_txcharisk_out] - connect_bd_net -net axi_daq2_gt_tx_gt_data [get_bd_pins axi_daq2_gt/tx_gt_data] [get_bd_pins axi_ad9144_jesd/gt_txdata_out] - connect_bd_net -net axi_daq2_gt_tx_rst_done [get_bd_pins axi_daq2_gt/tx_rst_done] [get_bd_pins axi_ad9144_jesd/tx_reset_done] - connect_bd_net -net axi_daq2_gt_tx_ip_sync [get_bd_pins axi_daq2_gt/tx_ip_sync] [get_bd_pins axi_ad9144_jesd/tx_sync] - connect_bd_net -net axi_daq2_gt_tx_ip_sof [get_bd_pins axi_daq2_gt/tx_ip_sof] [get_bd_pins axi_ad9144_jesd/tx_start_of_frame] - connect_bd_net -net axi_daq2_gt_tx_ip_data [get_bd_pins axi_daq2_gt/tx_ip_data] [get_bd_pins axi_ad9144_jesd/tx_tdata] - connect_bd_net -net axi_daq2_gt_tx_data [get_bd_pins axi_daq2_gt/tx_data] [get_bd_pins axi_ad9144_core/tx_data] - connect_bd_net -net axi_ad9144_dac_clk [get_bd_pins axi_ad9144_core/dac_clk] [get_bd_pins axi_ad9144_dma/fifo_rd_clk] - connect_bd_net -net axi_ad9144_dac_valid_0 [get_bd_pins axi_ad9144_core/dac_valid_0] [get_bd_ports dac_valid_0] - connect_bd_net -net axi_ad9144_dac_enable_0 [get_bd_pins axi_ad9144_core/dac_enable_0] [get_bd_ports dac_enable_0] - connect_bd_net -net axi_ad9144_dac_ddata_0 [get_bd_pins axi_ad9144_core/dac_ddata_0] [get_bd_ports dac_ddata_0] - connect_bd_net -net axi_ad9144_dac_valid_1 [get_bd_pins axi_ad9144_core/dac_valid_1] [get_bd_ports dac_valid_1] - connect_bd_net -net axi_ad9144_dac_enable_1 [get_bd_pins axi_ad9144_core/dac_enable_1] [get_bd_ports dac_enable_1] - connect_bd_net -net axi_ad9144_dac_ddata_1 [get_bd_pins axi_ad9144_core/dac_ddata_1] [get_bd_ports dac_ddata_1] - connect_bd_net -net axi_ad9144_dac_valid_2 [get_bd_pins axi_ad9144_core/dac_valid_2] [get_bd_ports dac_valid_2] - connect_bd_net -net axi_ad9144_dac_enable_2 [get_bd_pins axi_ad9144_core/dac_enable_2] [get_bd_ports dac_enable_2] - connect_bd_net -net axi_ad9144_dac_ddata_2 [get_bd_pins axi_ad9144_core/dac_ddata_2] [get_bd_ports dac_ddata_2] - connect_bd_net -net axi_ad9144_dac_valid_3 [get_bd_pins axi_ad9144_core/dac_valid_3] [get_bd_ports dac_valid_3] - connect_bd_net -net axi_ad9144_dac_enable_3 [get_bd_pins axi_ad9144_core/dac_enable_3] [get_bd_ports dac_enable_3] - connect_bd_net -net axi_ad9144_dac_ddata_3 [get_bd_pins axi_ad9144_core/dac_ddata_3] [get_bd_ports dac_ddata_3] - connect_bd_net -net axi_ad9144_dac_drd [get_bd_ports dac_drd] [get_bd_pins axi_ad9144_dma/fifo_rd_en] - connect_bd_net -net axi_ad9144_dac_ddata [get_bd_ports dac_ddata] [get_bd_pins axi_ad9144_dma/fifo_rd_dout] - connect_bd_net -net axi_ad9144_dac_dunf [get_bd_pins axi_ad9144_core/dac_dunf] [get_bd_pins axi_ad9144_dma/fifo_rd_underflow] - connect_bd_net -net axi_ad9144_dma_irq [get_bd_pins axi_ad9144_dma/irq] [get_bd_pins sys_concat_intc/In3] + connect_bd_net -net axi_fmcadc3_gt_ref_clk_q [get_bd_pins axi_fmcadc3_gt/ref_clk_q] [get_bd_ports rx_ref_clk] + connect_bd_net -net axi_fmcadc3_gt_rx_data_p [get_bd_pins axi_fmcadc3_gt/rx_data_p] [get_bd_ports rx_data_p] + connect_bd_net -net axi_fmcadc3_gt_rx_data_n [get_bd_pins axi_fmcadc3_gt/rx_data_n] [get_bd_ports rx_data_n] + connect_bd_net -net axi_fmcadc3_gt_rx_sync [get_bd_pins axi_fmcadc3_gt/rx_sync] [get_bd_ports rx_sync] + connect_bd_net -net axi_fmcadc3_gt_rx_ext_sysref [get_bd_pins axi_fmcadc3_gt/rx_ext_sysref] [get_bd_ports rx_sysref] # connections (adc) - connect_bd_net -net axi_daq2_gt_rx_clk [get_bd_pins axi_daq2_gt/rx_clk_g] - connect_bd_net -net axi_daq2_gt_rx_clk [get_bd_pins axi_daq2_gt/rx_clk] - connect_bd_net -net axi_daq2_gt_rx_clk [get_bd_pins axi_ad9680_core/rx_clk] - connect_bd_net -net axi_daq2_gt_rx_clk [get_bd_pins axi_ad9680_jesd/rx_core_clk] + connect_bd_net -net axi_fmcadc3_gt_rx_clk [get_bd_pins axi_fmcadc3_gt/rx_clk_g] + connect_bd_net -net axi_fmcadc3_gt_rx_clk [get_bd_pins axi_fmcadc3_gt/rx_clk] + connect_bd_net -net axi_fmcadc3_gt_rx_clk [get_bd_pins axi_ad9234_core_0/rx_clk] + connect_bd_net -net axi_fmcadc3_gt_rx_clk [get_bd_pins axi_ad9234_core_1/rx_clk] + connect_bd_net -net axi_fmcadc3_gt_rx_clk [get_bd_pins axi_ad9234_jesd/rx_core_clk] - connect_bd_net -net axi_daq2_gt_rx_rst [get_bd_pins axi_daq2_gt/rx_rst] [get_bd_pins axi_ad9680_jesd/rx_reset] - connect_bd_net -net axi_daq2_gt_rx_sysref [get_bd_pins axi_daq2_gt/rx_sysref] [get_bd_pins axi_ad9680_jesd/rx_sysref] - connect_bd_net -net axi_daq2_gt_rx_gt_charisk [get_bd_pins axi_daq2_gt/rx_gt_charisk] [get_bd_pins axi_ad9680_jesd/gt_rxcharisk_in] - connect_bd_net -net axi_daq2_gt_rx_gt_disperr [get_bd_pins axi_daq2_gt/rx_gt_disperr] [get_bd_pins axi_ad9680_jesd/gt_rxdisperr_in] - connect_bd_net -net axi_daq2_gt_rx_gt_notintable [get_bd_pins axi_daq2_gt/rx_gt_notintable] [get_bd_pins axi_ad9680_jesd/gt_rxnotintable_in] - connect_bd_net -net axi_daq2_gt_rx_gt_data [get_bd_pins axi_daq2_gt/rx_gt_data] [get_bd_pins axi_ad9680_jesd/gt_rxdata_in] - connect_bd_net -net axi_daq2_gt_rx_rst_done [get_bd_pins axi_daq2_gt/rx_rst_done] [get_bd_pins axi_ad9680_jesd/rx_reset_done] - connect_bd_net -net axi_daq2_gt_rx_ip_comma_align [get_bd_pins axi_daq2_gt/rx_ip_comma_align] [get_bd_pins axi_ad9680_jesd/rxencommaalign_out] - connect_bd_net -net axi_daq2_gt_rx_ip_sync [get_bd_pins axi_daq2_gt/rx_ip_sync] [get_bd_pins axi_ad9680_jesd/rx_sync] - connect_bd_net -net axi_daq2_gt_rx_ip_sof [get_bd_pins axi_daq2_gt/rx_ip_sof] [get_bd_pins axi_ad9680_jesd/rx_start_of_frame] - connect_bd_net -net axi_daq2_gt_rx_ip_data [get_bd_pins axi_daq2_gt/rx_ip_data] [get_bd_pins axi_ad9680_jesd/rx_tdata] - connect_bd_net -net axi_daq2_gt_rx_data [get_bd_pins axi_daq2_gt/rx_data] [get_bd_pins axi_ad9680_core/rx_data] - connect_bd_net -net axi_ad9680_adc_clk [get_bd_pins axi_ad9680_core/adc_clk] [get_bd_pins axi_ad9680_dma/fifo_wr_clk] - connect_bd_net -net axi_ad9680_adc_enable_0 [get_bd_pins axi_ad9680_core/adc_enable_0] [get_bd_ports adc_enable_0] - connect_bd_net -net axi_ad9680_adc_valid_0 [get_bd_pins axi_ad9680_core/adc_valid_0] [get_bd_ports adc_valid_0] - connect_bd_net -net axi_ad9680_adc_data_0 [get_bd_pins axi_ad9680_core/adc_data_0] [get_bd_ports adc_data_0] - connect_bd_net -net axi_ad9680_adc_enable_1 [get_bd_pins axi_ad9680_core/adc_enable_1] [get_bd_ports adc_enable_1] - connect_bd_net -net axi_ad9680_adc_valid_1 [get_bd_pins axi_ad9680_core/adc_valid_1] [get_bd_ports adc_valid_1] - connect_bd_net -net axi_ad9680_adc_data_1 [get_bd_pins axi_ad9680_core/adc_data_1] [get_bd_ports adc_data_1] - connect_bd_net -net axi_ad9680_adc_dwr [get_bd_ports adc_dwr] [get_bd_pins axi_ad9680_dma/fifo_wr_en] - connect_bd_net -net axi_ad9680_adc_dsync [get_bd_ports adc_dsync] [get_bd_pins axi_ad9680_dma/fifo_wr_sync] - connect_bd_net -net axi_ad9680_adc_ddata [get_bd_ports adc_ddata] [get_bd_pins axi_ad9680_dma/fifo_wr_din] - connect_bd_net -net axi_ad9680_adc_dovf [get_bd_pins axi_ad9680_core/adc_dovf] [get_bd_pins axi_ad9680_dma/fifo_wr_overflow] - connect_bd_net -net axi_ad9680_dma_irq [get_bd_pins axi_ad9680_dma/irq] [get_bd_pins sys_concat_intc/In2] + connect_bd_net -net axi_fmcadc3_gt_rx_rst [get_bd_pins axi_fmcadc3_gt/rx_rst] [get_bd_pins axi_ad9234_jesd/rx_reset] + connect_bd_net -net axi_fmcadc3_gt_rx_sysref [get_bd_pins axi_fmcadc3_gt/rx_sysref] [get_bd_pins axi_ad9234_jesd/rx_sysref] + connect_bd_net -net axi_fmcadc3_gt_rx_gt_charisk [get_bd_pins axi_fmcadc3_gt/rx_gt_charisk] [get_bd_pins axi_ad9234_jesd/gt_rxcharisk_in] + connect_bd_net -net axi_fmcadc3_gt_rx_gt_disperr [get_bd_pins axi_fmcadc3_gt/rx_gt_disperr] [get_bd_pins axi_ad9234_jesd/gt_rxdisperr_in] + connect_bd_net -net axi_fmcadc3_gt_rx_gt_notintable [get_bd_pins axi_fmcadc3_gt/rx_gt_notintable] [get_bd_pins axi_ad9234_jesd/gt_rxnotintable_in] + connect_bd_net -net axi_fmcadc3_gt_rx_gt_data [get_bd_pins axi_fmcadc3_gt/rx_gt_data] [get_bd_pins axi_ad9234_jesd/gt_rxdata_in] + connect_bd_net -net axi_fmcadc3_gt_rx_rst_done [get_bd_pins axi_fmcadc3_gt/rx_rst_done] [get_bd_pins axi_ad9234_jesd/rx_reset_done] + connect_bd_net -net axi_fmcadc3_gt_rx_ip_comma_align [get_bd_pins axi_fmcadc3_gt/rx_ip_comma_align] [get_bd_pins axi_ad9234_jesd/rxencommaalign_out] + connect_bd_net -net axi_fmcadc3_gt_rx_ip_sync [get_bd_pins axi_fmcadc3_gt/rx_ip_sync] [get_bd_pins axi_ad9234_jesd/rx_sync] + connect_bd_net -net axi_fmcadc3_gt_rx_ip_sof [get_bd_pins axi_fmcadc3_gt/rx_ip_sof] [get_bd_pins axi_ad9234_jesd/rx_start_of_frame] + connect_bd_net -net axi_fmcadc3_gt_rx_ip_data [get_bd_pins axi_fmcadc3_gt/rx_ip_data] [get_bd_pins axi_ad9234_jesd/rx_tdata] + connect_bd_net -net axi_fmcadc3_gt_rx_data [get_bd_pins axi_fmcadc3_gt/rx_data] [get_bd_ports gt_data] + connect_bd_net -net axi_fmcadc3_gt_0_rx_data [get_bd_pins axi_ad9234_core_0/rx_data] [get_bd_ports gt_data_0] + connect_bd_net -net axi_fmcadc3_gt_1_rx_data [get_bd_pins axi_ad9234_core_1/rx_data] [get_bd_ports gt_data_1] + connect_bd_net -net axi_ad9234_adc_clk [get_bd_pins axi_ad9234_core_0/adc_clk] [get_bd_pins axi_ad9234_dma/fifo_wr_clk] + connect_bd_net -net axi_ad9234_0_adc_enable_0 [get_bd_pins axi_ad9234_core_0/adc_enable_0] [get_bd_ports adc_enable_0] + connect_bd_net -net axi_ad9234_0_adc_valid_0 [get_bd_pins axi_ad9234_core_0/adc_valid_0] [get_bd_ports adc_valid_0] + connect_bd_net -net axi_ad9234_0_adc_data_0 [get_bd_pins axi_ad9234_core_0/adc_data_0] [get_bd_ports adc_data_0] + connect_bd_net -net axi_ad9234_0_adc_enable_1 [get_bd_pins axi_ad9234_core_0/adc_enable_1] [get_bd_ports adc_enable_1] + connect_bd_net -net axi_ad9234_0_adc_valid_1 [get_bd_pins axi_ad9234_core_0/adc_valid_1] [get_bd_ports adc_valid_1] + connect_bd_net -net axi_ad9234_0_adc_data_1 [get_bd_pins axi_ad9234_core_0/adc_data_1] [get_bd_ports adc_data_1] + connect_bd_net -net axi_ad9234_1_adc_enable_0 [get_bd_pins axi_ad9234_core_1/adc_enable_0] [get_bd_ports adc_enable_2] + connect_bd_net -net axi_ad9234_1_adc_valid_0 [get_bd_pins axi_ad9234_core_1/adc_valid_0] [get_bd_ports adc_valid_2] + connect_bd_net -net axi_ad9234_1_adc_data_0 [get_bd_pins axi_ad9234_core_1/adc_data_0] [get_bd_ports adc_data_2] + connect_bd_net -net axi_ad9234_1_adc_enable_1 [get_bd_pins axi_ad9234_core_1/adc_enable_1] [get_bd_ports adc_enable_3] + connect_bd_net -net axi_ad9234_1_adc_valid_1 [get_bd_pins axi_ad9234_core_1/adc_valid_1] [get_bd_ports adc_valid_3] + connect_bd_net -net axi_ad9234_1_adc_data_1 [get_bd_pins axi_ad9234_core_1/adc_data_1] [get_bd_ports adc_data_3] + connect_bd_net -net axi_ad9234_adc_dwr [get_bd_ports adc_dwr] [get_bd_pins axi_ad9234_dma/fifo_wr_en] + connect_bd_net -net axi_ad9234_adc_dsync [get_bd_ports adc_dsync] [get_bd_pins axi_ad9234_dma/fifo_wr_sync] + connect_bd_net -net axi_ad9234_adc_ddata [get_bd_ports adc_ddata] [get_bd_pins axi_ad9234_dma/fifo_wr_din] + connect_bd_net -net axi_ad9234_adc_dovf [get_bd_pins axi_ad9234_core_0/adc_dovf] [get_bd_pins axi_ad9234_dma/fifo_wr_overflow] + connect_bd_net -net axi_ad9234_dma_irq [get_bd_pins axi_ad9234_dma/irq] [get_bd_pins sys_concat_intc/In2] # dac/adc clocks - connect_bd_net -net axi_ad9144_dac_clk [get_bd_ports dac_clk] - connect_bd_net -net axi_ad9680_adc_clk [get_bd_ports adc_clk] + connect_bd_net -net axi_ad9234_adc_clk [get_bd_ports adc_clk] # interconnect (cpu) - connect_bd_intf_net -intf_net axi_cpu_interconnect_m07_axi [get_bd_intf_pins axi_cpu_interconnect/M07_AXI] [get_bd_intf_pins axi_ad9144_dma/s_axi] - connect_bd_intf_net -intf_net axi_cpu_interconnect_m08_axi [get_bd_intf_pins axi_cpu_interconnect/M08_AXI] [get_bd_intf_pins axi_ad9144_core/s_axi] - connect_bd_intf_net -intf_net axi_cpu_interconnect_m09_axi [get_bd_intf_pins axi_cpu_interconnect/M09_AXI] [get_bd_intf_pins axi_ad9144_jesd/s_axi] - connect_bd_intf_net -intf_net axi_cpu_interconnect_m10_axi [get_bd_intf_pins axi_cpu_interconnect/M10_AXI] [get_bd_intf_pins axi_ad9680_dma/s_axi] - connect_bd_intf_net -intf_net axi_cpu_interconnect_m11_axi [get_bd_intf_pins axi_cpu_interconnect/M11_AXI] [get_bd_intf_pins axi_ad9680_core/s_axi] - connect_bd_intf_net -intf_net axi_cpu_interconnect_m12_axi [get_bd_intf_pins axi_cpu_interconnect/M12_AXI] [get_bd_intf_pins axi_ad9680_jesd/s_axi] - connect_bd_intf_net -intf_net axi_cpu_interconnect_m13_axi [get_bd_intf_pins axi_cpu_interconnect/M13_AXI] [get_bd_intf_pins axi_daq2_gt/s_axi] + connect_bd_intf_net -intf_net axi_cpu_interconnect_m07_axi [get_bd_intf_pins axi_cpu_interconnect/M07_AXI] [get_bd_intf_pins axi_ad9234_dma/s_axi] + connect_bd_intf_net -intf_net axi_cpu_interconnect_m08_axi [get_bd_intf_pins axi_cpu_interconnect/M08_AXI] [get_bd_intf_pins axi_ad9234_core_0/s_axi] + connect_bd_intf_net -intf_net axi_cpu_interconnect_m09_axi [get_bd_intf_pins axi_cpu_interconnect/M09_AXI] [get_bd_intf_pins axi_ad9234_core_1/s_axi] + connect_bd_intf_net -intf_net axi_cpu_interconnect_m10_axi [get_bd_intf_pins axi_cpu_interconnect/M10_AXI] [get_bd_intf_pins axi_ad9234_jesd/s_axi] + connect_bd_intf_net -intf_net axi_cpu_interconnect_m11_axi [get_bd_intf_pins axi_cpu_interconnect/M11_AXI] [get_bd_intf_pins axi_fmcadc3_gt/s_axi] connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M07_ACLK] $sys_100m_clk_source connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M08_ACLK] $sys_100m_clk_source connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M09_ACLK] $sys_100m_clk_source connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M10_ACLK] $sys_100m_clk_source connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M11_ACLK] $sys_100m_clk_source - connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M12_ACLK] $sys_100m_clk_source - connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M13_ACLK] $sys_100m_clk_source - connect_bd_net -net sys_100m_clk [get_bd_pins axi_daq2_gt/s_axi_aclk] - connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9144_core/s_axi_aclk] - connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9144_jesd/s_axi_aclk] - connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9144_dma/s_axi_aclk] - connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9680_core/s_axi_aclk] - connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9680_jesd/s_axi_aclk] - connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9680_dma/s_axi_aclk] + connect_bd_net -net sys_100m_clk [get_bd_pins axi_fmcadc3_gt/s_axi_aclk] + connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9234_core_0/s_axi_aclk] + connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9234_core_1/s_axi_aclk] + connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9234_jesd/s_axi_aclk] + connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9234_dma/s_axi_aclk] connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M07_ARESETN] $sys_100m_resetn_source connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M08_ARESETN] $sys_100m_resetn_source connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M09_ARESETN] $sys_100m_resetn_source connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M10_ARESETN] $sys_100m_resetn_source connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M11_ARESETN] $sys_100m_resetn_source - connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M12_ARESETN] $sys_100m_resetn_source - connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M13_ARESETN] $sys_100m_resetn_source - connect_bd_net -net sys_100m_resetn [get_bd_pins axi_daq2_gt/s_axi_aresetn] - connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9144_core/s_axi_aresetn] - connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9144_jesd/s_axi_aresetn] - connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9144_dma/s_axi_aresetn] - connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9680_core/s_axi_aresetn] - connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9680_jesd/s_axi_aresetn] - connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9680_dma/s_axi_aresetn] + connect_bd_net -net sys_100m_resetn [get_bd_pins axi_fmcadc3_gt/s_axi_aresetn] + connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9234_core_0/s_axi_aresetn] + connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9234_core_1/s_axi_aresetn] + connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9234_jesd/s_axi_aresetn] + connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9234_dma/s_axi_aresetn] if {$sys_zynq == 0} { - connect_bd_intf_net -intf_net axi_cpu_interconnect_m14_axi [get_bd_intf_pins axi_cpu_interconnect/M14_AXI] [get_bd_intf_pins axi_daq2_spi/axi_lite] - connect_bd_intf_net -intf_net axi_cpu_interconnect_m15_axi [get_bd_intf_pins axi_cpu_interconnect/M15_AXI] [get_bd_intf_pins axi_daq2_gpio/s_axi] - connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M14_ACLK] $sys_100m_clk_source - connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M15_ACLK] $sys_100m_clk_source - connect_bd_net -net sys_100m_clk [get_bd_pins axi_daq2_spi/s_axi_aclk] - connect_bd_net -net sys_100m_clk [get_bd_pins axi_daq2_spi/ext_spi_clk] - connect_bd_net -net sys_100m_clk [get_bd_pins axi_daq2_gpio/s_axi_aclk] - connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M14_ARESETN] $sys_100m_resetn_source - connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M15_ARESETN] $sys_100m_resetn_source - connect_bd_net -net sys_100m_resetn [get_bd_pins axi_daq2_spi/s_axi_aresetn] - connect_bd_net -net sys_100m_resetn [get_bd_pins axi_daq2_gpio/s_axi_aresetn] + connect_bd_intf_net -intf_net axi_cpu_interconnect_m12_axi [get_bd_intf_pins axi_cpu_interconnect/M12_AXI] [get_bd_intf_pins axi_fmcadc3_spi/axi_lite] + connect_bd_intf_net -intf_net axi_cpu_interconnect_m13_axi [get_bd_intf_pins axi_cpu_interconnect/M13_AXI] [get_bd_intf_pins axi_fmcadc3_gpio/s_axi] + connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M12_ACLK] $sys_100m_clk_source + connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M13_ACLK] $sys_100m_clk_source + connect_bd_net -net sys_100m_clk [get_bd_pins axi_fmcadc3_spi/s_axi_aclk] + connect_bd_net -net sys_100m_clk [get_bd_pins axi_fmcadc3_spi/ext_spi_clk] + connect_bd_net -net sys_100m_clk [get_bd_pins axi_fmcadc3_gpio/s_axi_aclk] + connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M12_ARESETN] $sys_100m_resetn_source + connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M13_ARESETN] $sys_100m_resetn_source + connect_bd_net -net sys_100m_resetn [get_bd_pins axi_fmcadc3_spi/s_axi_aresetn] + connect_bd_net -net sys_100m_resetn [get_bd_pins axi_fmcadc3_gpio/s_axi_aresetn] - connect_bd_net -net axi_daq2_spi_irq [get_bd_pins axi_daq2_spi/ip2intc_irpt] [get_bd_pins sys_concat_intc/In5] - connect_bd_net -net axi_daq2_gpio_irq [get_bd_pins axi_daq2_gpio/ip2intc_irpt] [get_bd_pins sys_concat_intc/In6] + connect_bd_net -net axi_fmcadc3_spi_irq [get_bd_pins axi_fmcadc3_spi/ip2intc_irpt] [get_bd_pins sys_concat_intc/In5] + connect_bd_net -net axi_fmcadc3_gpio_irq [get_bd_pins axi_fmcadc3_gpio/ip2intc_irpt] [get_bd_pins sys_concat_intc/In6] } # gt uses hp3, and 100MHz clock for both DRP and AXI4 if {$sys_zynq == 0} { - connect_bd_intf_net -intf_net axi_mem_interconnect_s08_axi [get_bd_intf_pins axi_mem_interconnect/S08_AXI] [get_bd_intf_pins axi_daq2_gt/m_axi] + connect_bd_intf_net -intf_net axi_mem_interconnect_s08_axi [get_bd_intf_pins axi_mem_interconnect/S08_AXI] [get_bd_intf_pins axi_fmcadc3_gt/m_axi] connect_bd_net -net sys_100m_clk [get_bd_pins axi_mem_interconnect/S08_ACLK] $sys_100m_clk_source - connect_bd_net -net sys_100m_clk [get_bd_pins axi_daq2_gt/m_axi_aclk] - connect_bd_net -net sys_100m_clk [get_bd_pins axi_daq2_gt/drp_clk] + connect_bd_net -net sys_100m_clk [get_bd_pins axi_fmcadc3_gt/m_axi_aclk] + connect_bd_net -net sys_100m_clk [get_bd_pins axi_fmcadc3_gt/drp_clk] connect_bd_net -net sys_100m_resetn [get_bd_pins axi_mem_interconnect/S08_ARESETN] $sys_100m_resetn_source - connect_bd_net -net sys_100m_resetn [get_bd_pins axi_daq2_gt/m_axi_aresetn] + connect_bd_net -net sys_100m_resetn [get_bd_pins axi_fmcadc3_gt/m_axi_aresetn] } else { - connect_bd_intf_net -intf_net axi_daq2_gt_interconnect_m00_axi [get_bd_intf_pins axi_daq2_gt_interconnect/M00_AXI] [get_bd_intf_pins sys_ps7/S_AXI_HP3] - connect_bd_intf_net -intf_net axi_daq2_gt_interconnect_s00_axi [get_bd_intf_pins axi_daq2_gt_interconnect/S00_AXI] [get_bd_intf_pins axi_daq2_gt/m_axi] - connect_bd_net -net sys_100m_clk [get_bd_pins axi_daq2_gt_interconnect/ACLK] $sys_100m_clk_source - connect_bd_net -net sys_100m_clk [get_bd_pins axi_daq2_gt_interconnect/M00_ACLK] $sys_100m_clk_source - connect_bd_net -net sys_100m_clk [get_bd_pins axi_daq2_gt_interconnect/S00_ACLK] $sys_100m_clk_source + connect_bd_intf_net -intf_net axi_fmcadc3_gt_interconnect_m00_axi [get_bd_intf_pins axi_fmcadc3_gt_interconnect/M00_AXI] [get_bd_intf_pins sys_ps7/S_AXI_HP3] + connect_bd_intf_net -intf_net axi_fmcadc3_gt_interconnect_s00_axi [get_bd_intf_pins axi_fmcadc3_gt_interconnect/S00_AXI] [get_bd_intf_pins axi_fmcadc3_gt/m_axi] + connect_bd_net -net sys_100m_clk [get_bd_pins axi_fmcadc3_gt_interconnect/ACLK] $sys_100m_clk_source + connect_bd_net -net sys_100m_clk [get_bd_pins axi_fmcadc3_gt_interconnect/M00_ACLK] $sys_100m_clk_source + connect_bd_net -net sys_100m_clk [get_bd_pins axi_fmcadc3_gt_interconnect/S00_ACLK] $sys_100m_clk_source connect_bd_net -net sys_100m_clk [get_bd_pins sys_ps7/S_AXI_HP3_ACLK] - connect_bd_net -net sys_100m_clk [get_bd_pins axi_daq2_gt/m_axi_aclk] - connect_bd_net -net sys_100m_clk [get_bd_pins axi_daq2_gt/drp_clk] - connect_bd_net -net sys_100m_resetn [get_bd_pins axi_daq2_gt_interconnect/ARESETN] $sys_100m_resetn_source - connect_bd_net -net sys_100m_resetn [get_bd_pins axi_daq2_gt_interconnect/M00_ARESETN] $sys_100m_resetn_source - connect_bd_net -net sys_100m_resetn [get_bd_pins axi_daq2_gt_interconnect/S00_ARESETN] $sys_100m_resetn_source - connect_bd_net -net sys_100m_resetn [get_bd_pins axi_daq2_gt/m_axi_aresetn] + connect_bd_net -net sys_100m_clk [get_bd_pins axi_fmcadc3_gt/m_axi_aclk] + connect_bd_net -net sys_100m_clk [get_bd_pins axi_fmcadc3_gt/drp_clk] + connect_bd_net -net sys_100m_resetn [get_bd_pins axi_fmcadc3_gt_interconnect/ARESETN] $sys_100m_resetn_source + connect_bd_net -net sys_100m_resetn [get_bd_pins axi_fmcadc3_gt_interconnect/M00_ARESETN] $sys_100m_resetn_source + connect_bd_net -net sys_100m_resetn [get_bd_pins axi_fmcadc3_gt_interconnect/S00_ARESETN] $sys_100m_resetn_source + connect_bd_net -net sys_100m_resetn [get_bd_pins axi_fmcadc3_gt/m_axi_aresetn] } # memory interconnects share the same clock (fclk2) @@ -410,99 +333,67 @@ if {$sys_zynq == 1} { if {$sys_zynq == 0} { - connect_bd_intf_net -intf_net axi_mem_interconnect_s09_axi [get_bd_intf_pins axi_mem_interconnect/S09_AXI] [get_bd_intf_pins axi_ad9144_dma/m_src_axi] + connect_bd_intf_net -intf_net axi_mem_interconnect_s09_axi [get_bd_intf_pins axi_mem_interconnect/S09_AXI] [get_bd_intf_pins axi_ad9234_dma/m_dest_axi] connect_bd_net -net sys_200m_clk [get_bd_pins axi_mem_interconnect/S09_ACLK] $sys_200m_clk_source - connect_bd_net -net sys_200m_clk [get_bd_pins axi_ad9144_dma/m_src_axi_aclk] + connect_bd_net -net sys_200m_clk [get_bd_pins axi_ad9234_dma/m_dest_axi_aclk] connect_bd_net -net sys_200m_resetn [get_bd_pins axi_mem_interconnect/S09_ARESETN] $sys_200m_resetn_source - connect_bd_net -net sys_200m_resetn [get_bd_pins axi_ad9144_dma/m_src_axi_aresetn] - - connect_bd_intf_net -intf_net axi_mem_interconnect_s10_axi [get_bd_intf_pins axi_mem_interconnect/S10_AXI] [get_bd_intf_pins axi_ad9680_dma/m_dest_axi] - connect_bd_net -net sys_200m_clk [get_bd_pins axi_mem_interconnect/S10_ACLK] $sys_200m_clk_source - connect_bd_net -net sys_200m_clk [get_bd_pins axi_ad9680_dma/m_dest_axi_aclk] - connect_bd_net -net sys_200m_resetn [get_bd_pins axi_mem_interconnect/S10_ARESETN] $sys_200m_resetn_source - connect_bd_net -net sys_200m_resetn [get_bd_pins axi_ad9680_dma/m_dest_axi_aresetn] + connect_bd_net -net sys_200m_resetn [get_bd_pins axi_ad9234_dma/m_dest_axi_aresetn] } else { - connect_bd_intf_net -intf_net axi_ad9144_dma_interconnect_m00_axi [get_bd_intf_pins axi_ad9144_dma_interconnect/M00_AXI] [get_bd_intf_pins sys_ps7/S_AXI_HP1] - connect_bd_intf_net -intf_net axi_ad9144_dma_interconnect_s00_axi [get_bd_intf_pins axi_ad9144_dma_interconnect/S00_AXI] [get_bd_intf_pins axi_ad9144_dma/m_src_axi] - connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_ad9144_dma_interconnect/ACLK] $sys_fmc_dma_clk_source - connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_ad9144_dma_interconnect/M00_ACLK] $sys_fmc_dma_clk_source - connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_ad9144_dma_interconnect/S00_ACLK] $sys_fmc_dma_clk_source - connect_bd_net -net sys_fmc_dma_clk [get_bd_pins sys_ps7/S_AXI_HP1_ACLK] - connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_ad9144_dma/m_src_axi_aclk] - connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_ad9144_dma_interconnect/ARESETN] $sys_fmc_dma_resetn_source - connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_ad9144_dma_interconnect/M00_ARESETN] $sys_fmc_dma_resetn_source - connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_ad9144_dma_interconnect/S00_ARESETN] $sys_fmc_dma_resetn_source - connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_ad9144_dma/m_src_axi_aresetn] - - connect_bd_intf_net -intf_net axi_ad9680_dma_interconnect_m00_axi [get_bd_intf_pins axi_ad9680_dma_interconnect/M00_AXI] [get_bd_intf_pins sys_ps7/S_AXI_HP2] - connect_bd_intf_net -intf_net axi_ad9680_dma_interconnect_s00_axi [get_bd_intf_pins axi_ad9680_dma_interconnect/S00_AXI] [get_bd_intf_pins axi_ad9680_dma/m_dest_axi] - connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_ad9680_dma_interconnect/ACLK] $sys_fmc_dma_clk_source - connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_ad9680_dma_interconnect/M00_ACLK] $sys_fmc_dma_clk_source - connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_ad9680_dma_interconnect/S00_ACLK] $sys_fmc_dma_clk_source + connect_bd_intf_net -intf_net axi_ad9234_dma_interconnect_m00_axi [get_bd_intf_pins axi_ad9234_dma_interconnect/M00_AXI] [get_bd_intf_pins sys_ps7/S_AXI_HP2] + connect_bd_intf_net -intf_net axi_ad9234_dma_interconnect_s00_axi [get_bd_intf_pins axi_ad9234_dma_interconnect/S00_AXI] [get_bd_intf_pins axi_ad9234_dma/m_dest_axi] + connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_ad9234_dma_interconnect/ACLK] $sys_fmc_dma_clk_source + connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_ad9234_dma_interconnect/M00_ACLK] $sys_fmc_dma_clk_source + connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_ad9234_dma_interconnect/S00_ACLK] $sys_fmc_dma_clk_source connect_bd_net -net sys_fmc_dma_clk [get_bd_pins sys_ps7/S_AXI_HP2_ACLK] - connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_ad9680_dma/m_dest_axi_aclk] - connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_ad9680_dma_interconnect/ARESETN] $sys_fmc_dma_resetn_source - connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_ad9680_dma_interconnect/M00_ARESETN] $sys_fmc_dma_resetn_source - connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_ad9680_dma_interconnect/S00_ARESETN] $sys_fmc_dma_resetn_source - connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_ad9680_dma/m_dest_axi_aresetn] + connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_ad9234_dma/m_dest_axi_aclk] + connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_ad9234_dma_interconnect/ARESETN] $sys_fmc_dma_resetn_source + connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_ad9234_dma_interconnect/M00_ARESETN] $sys_fmc_dma_resetn_source + connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_ad9234_dma_interconnect/S00_ARESETN] $sys_fmc_dma_resetn_source + connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_ad9234_dma/m_dest_axi_aresetn] } # ila - set ila_jesd_rx_mon [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:3.0 ila_jesd_rx_mon] + set ila_jesd_rx_mon [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:4.0 ila_jesd_rx_mon] + set_property -dict [list CONFIG.C_MONITOR_TYPE {Native}] $ila_jesd_rx_mon set_property -dict [list CONFIG.C_NUM_OF_PROBES {4}] $ila_jesd_rx_mon - set_property -dict [list CONFIG.C_PROBE0_WIDTH {334}] $ila_jesd_rx_mon - set_property -dict [list CONFIG.C_PROBE1_WIDTH {6}] $ila_jesd_rx_mon - set_property -dict [list CONFIG.C_PROBE2_WIDTH {128}] $ila_jesd_rx_mon - set_property -dict [list CONFIG.C_PROBE3_WIDTH {128}] $ila_jesd_rx_mon + set_property -dict [list CONFIG.C_PROBE0_WIDTH {662}] $ila_jesd_rx_mon + set_property -dict [list CONFIG.C_PROBE1_WIDTH {10}] $ila_jesd_rx_mon + set_property -dict [list CONFIG.C_PROBE2_WIDTH {256}] $ila_jesd_rx_mon + set_property -dict [list CONFIG.C_PROBE3_WIDTH {256}] $ila_jesd_rx_mon - connect_bd_net -net axi_daq2_gt_rx_mon_data [get_bd_pins axi_daq2_gt/rx_mon_data] - connect_bd_net -net axi_daq2_gt_rx_mon_trigger [get_bd_pins axi_daq2_gt/rx_mon_trigger] - connect_bd_net -net axi_daq2_gt_rx_clk [get_bd_pins ila_jesd_rx_mon/CLK] - connect_bd_net -net axi_daq2_gt_rx_mon_data [get_bd_pins ila_jesd_rx_mon/PROBE0] - connect_bd_net -net axi_daq2_gt_rx_mon_trigger [get_bd_pins ila_jesd_rx_mon/PROBE1] - connect_bd_net -net axi_daq2_gt_rx_data [get_bd_pins ila_jesd_rx_mon/PROBE2] - connect_bd_net -net axi_ad9680_adc_ddata [get_bd_pins ila_jesd_rx_mon/PROBE3] - - set ila_jesd_tx_mon [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:3.0 ila_jesd_tx_mon] - set_property -dict [list CONFIG.C_NUM_OF_PROBES {2}] $ila_jesd_tx_mon - set_property -dict [list CONFIG.C_PROBE0_WIDTH {150}] $ila_jesd_tx_mon - set_property -dict [list CONFIG.C_PROBE1_WIDTH {6}] $ila_jesd_tx_mon - - connect_bd_net -net axi_daq2_gt_tx_mon_data [get_bd_pins axi_daq2_gt/tx_mon_data] - connect_bd_net -net axi_daq2_gt_tx_mon_trigger [get_bd_pins axi_daq2_gt/tx_mon_trigger] - connect_bd_net -net axi_daq2_gt_tx_clk [get_bd_pins ila_jesd_tx_mon/CLK] - connect_bd_net -net axi_daq2_gt_tx_mon_data [get_bd_pins ila_jesd_tx_mon/PROBE0] - connect_bd_net -net axi_daq2_gt_tx_mon_trigger [get_bd_pins ila_jesd_tx_mon/PROBE1] + connect_bd_net -net axi_fmcadc3_gt_rx_mon_data [get_bd_pins axi_fmcadc3_gt/rx_mon_data] + connect_bd_net -net axi_fmcadc3_gt_rx_mon_trigger [get_bd_pins axi_fmcadc3_gt/rx_mon_trigger] + connect_bd_net -net axi_fmcadc3_gt_rx_clk [get_bd_pins ila_jesd_rx_mon/CLK] + connect_bd_net -net axi_fmcadc3_gt_rx_mon_data [get_bd_pins ila_jesd_rx_mon/PROBE0] + connect_bd_net -net axi_fmcadc3_gt_rx_mon_trigger [get_bd_pins ila_jesd_rx_mon/PROBE1] + connect_bd_net -net axi_fmcadc3_gt_rx_data [get_bd_pins ila_jesd_rx_mon/PROBE2] + connect_bd_net -net axi_ad9234_adc_ddata [get_bd_pins ila_jesd_rx_mon/PROBE3] # address map - create_bd_addr_seg -range 0x00010000 -offset 0x44A00000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad9144_core/s_axi/axi_lite] SEG_data_ad9144_core - create_bd_addr_seg -range 0x00010000 -offset 0x44A10000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad9680_core/s_axi/axi_lite] SEG_data_ad9680_core - create_bd_addr_seg -range 0x00010000 -offset 0x44A60000 $sys_addr_cntrl_space [get_bd_addr_segs axi_daq2_gt/s_axi/axi_lite] SEG_data_daq2_gt - create_bd_addr_seg -range 0x00001000 -offset 0x44A90000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad9144_jesd/s_axi/Reg] SEG_data_ad9144_jesd - create_bd_addr_seg -range 0x00001000 -offset 0x44A91000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad9680_jesd/s_axi/Reg] SEG_data_ad9680_jesd - create_bd_addr_seg -range 0x00010000 -offset 0x7c400000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad9680_dma/s_axi/axi_lite] SEG_data_ad9680_dma - create_bd_addr_seg -range 0x00010000 -offset 0x7c420000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad9144_dma/s_axi/axi_lite] SEG_data_ad9144_dma + create_bd_addr_seg -range 0x00010000 -offset 0x44A00000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad9234_core_0/s_axi/axi_lite] SEG_data_ad9234_0_core + create_bd_addr_seg -range 0x00010000 -offset 0x44A10000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad9234_core_1/s_axi/axi_lite] SEG_data_ad9234_1_core + create_bd_addr_seg -range 0x00010000 -offset 0x44A60000 $sys_addr_cntrl_space [get_bd_addr_segs axi_fmcadc3_gt/s_axi/axi_lite] SEG_data_fmcadc3_gt + create_bd_addr_seg -range 0x00001000 -offset 0x44A91000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad9234_jesd/s_axi/Reg] SEG_data_ad9234_jesd + create_bd_addr_seg -range 0x00010000 -offset 0x7c400000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad9234_dma/s_axi/axi_lite] SEG_data_ad9234_dma if {$sys_zynq == 0} { - create_bd_addr_seg -range 0x00010000 -offset 0x40000000 $sys_addr_cntrl_space [get_bd_addr_segs axi_daq2_gpio/S_AXI/Reg] SEG_data_daq2_gpio - create_bd_addr_seg -range 0x00010000 -offset 0x44A70000 $sys_addr_cntrl_space [get_bd_addr_segs axi_daq2_spi/axi_lite/Reg] SEG_data_daq2_spi + create_bd_addr_seg -range 0x00010000 -offset 0x40000000 $sys_addr_cntrl_space [get_bd_addr_segs axi_fmcadc3_gpio/S_AXI/Reg] SEG_data_fmcadc3_gpio + create_bd_addr_seg -range 0x00010000 -offset 0x44A70000 $sys_addr_cntrl_space [get_bd_addr_segs axi_fmcadc3_spi/axi_lite/Reg] SEG_data_fmcadc3_spi } if {$sys_zynq == 0} { - create_bd_addr_seg -range $sys_mem_size -offset 0x80000000 [get_bd_addr_spaces axi_ad9144_dma/m_src_axi] [get_bd_addr_segs axi_ddr_cntrl/memmap/memaddr] SEG_axi_ddr_cntrl - create_bd_addr_seg -range $sys_mem_size -offset 0x80000000 [get_bd_addr_spaces axi_ad9680_dma/m_dest_axi] [get_bd_addr_segs axi_ddr_cntrl/memmap/memaddr] SEG_axi_ddr_cntrl - create_bd_addr_seg -range $sys_mem_size -offset 0x80000000 [get_bd_addr_spaces axi_daq2_gt/m_axi] [get_bd_addr_segs axi_ddr_cntrl/memmap/memaddr] SEG_axi_ddr_cntrl + create_bd_addr_seg -range $sys_mem_size -offset 0x80000000 [get_bd_addr_spaces axi_ad9234_dma/m_dest_axi] [get_bd_addr_segs axi_ddr_cntrl/memmap/memaddr] SEG_axi_ddr_cntrl + create_bd_addr_seg -range $sys_mem_size -offset 0x80000000 [get_bd_addr_spaces axi_fmcadc3_gt/m_axi] [get_bd_addr_segs axi_ddr_cntrl/memmap/memaddr] SEG_axi_ddr_cntrl } else { - create_bd_addr_seg -range $sys_mem_size -offset 0x00000000 [get_bd_addr_spaces axi_ad9144_dma/m_src_axi] [get_bd_addr_segs sys_ps7/S_AXI_HP1/HP1_DDR_LOWOCM] SEG_sys_ps7_hp1_ddr_lowocm - create_bd_addr_seg -range $sys_mem_size -offset 0x00000000 [get_bd_addr_spaces axi_ad9680_dma/m_dest_axi] [get_bd_addr_segs sys_ps7/S_AXI_HP2/HP2_DDR_LOWOCM] SEG_sys_ps7_hp2_ddr_lowocm - create_bd_addr_seg -range $sys_mem_size -offset 0x00000000 [get_bd_addr_spaces axi_daq2_gt/m_axi] [get_bd_addr_segs sys_ps7/S_AXI_HP3/HP3_DDR_LOWOCM] SEG_sys_ps7_hp3_ddr_lowocm + create_bd_addr_seg -range $sys_mem_size -offset 0x00000000 [get_bd_addr_spaces axi_ad9234_dma/m_dest_axi] [get_bd_addr_segs sys_ps7/S_AXI_HP2/HP2_DDR_LOWOCM] SEG_sys_ps7_hp2_ddr_lowocm + create_bd_addr_seg -range $sys_mem_size -offset 0x00000000 [get_bd_addr_spaces axi_fmcadc3_gt/m_axi] [get_bd_addr_segs sys_ps7/S_AXI_HP3/HP3_DDR_LOWOCM] SEG_sys_ps7_hp3_ddr_lowocm } diff --git a/projects/fmcadc3/common/fmcadc3_spi.v b/projects/fmcadc3/common/fmcadc3_spi.v index eb3e7d91e..a038044cf 100644 --- a/projects/fmcadc3/common/fmcadc3_spi.v +++ b/projects/fmcadc3/common/fmcadc3_spi.v @@ -39,7 +39,9 @@ module daq2_spi ( - spi_csn, + ad9528_csn, + ad9234_1_csn, + ad9234_2_csn, spi_clk, spi_mosi, spi_miso, @@ -48,7 +50,9 @@ module daq2_spi ( // 4 wire - input [ 2:0] spi_csn; + input ad9528_csn; + input ad9234_1_csn; + input ad9234_2_csn; input spi_clk; input spi_mosi; output spi_miso; @@ -70,7 +74,7 @@ module daq2_spi ( // check on rising edge and change on falling edge - assign spi_csn_s = & spi_csn; + assign spi_csn_s = ad9528_csn & ad9234_1_csn & ad9234_2_csn; assign spi_enable_s = spi_enable & ~spi_csn_s; always @(posedge spi_clk or posedge spi_csn_s) begin diff --git a/projects/fmcadc3/zc706/system_bd.tcl b/projects/fmcadc3/zc706/system_bd.tcl index 177e09f7f..09cfe6587 100644 --- a/projects/fmcadc3/zc706/system_bd.tcl +++ b/projects/fmcadc3/zc706/system_bd.tcl @@ -1,14 +1,12 @@ source $ad_hdl_dir/projects/common/zc706/zc706_system_bd.tcl source $ad_hdl_dir/projects/common/zc706/zc706_system_plddr3.tcl -source ../common/daq2_bd.tcl +source ../common/fmcadc3_bd.tcl -set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_SRC {64}] $axi_ad9144_dma -set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_DEST {128}] $axi_ad9144_dma -set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_SRC {64}] $axi_ad9680_dma -set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_DEST {64}] $axi_ad9680_dma +set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_SRC {64}] $axi_ad9234_dma +set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_DEST {64}] $axi_ad9234_dma -p_plddr3_fifo [current_bd_instance .] plddr3_fifo 128 +p_plddr3_fifo [current_bd_instance .] plddr3_fifo 256 set DDR3 [create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 DDR3] set sys_clk [create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 sys_clk] @@ -16,41 +14,42 @@ set sys_clk [create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clo connect_bd_intf_net -intf_net DDR3 [get_bd_intf_ports DDR3] [get_bd_intf_pins plddr3_fifo/DDR3] connect_bd_intf_net -intf_net sys_clk [get_bd_intf_ports sys_clk] [get_bd_intf_pins plddr3_fifo/sys_clk] -delete_bd_objs [get_bd_nets axi_ad9680_adc_clk] -delete_bd_objs [get_bd_nets axi_ad9680_adc_dwr] -delete_bd_objs [get_bd_nets axi_ad9680_adc_ddata] -delete_bd_objs [get_bd_nets axi_ad9680_adc_dsync] -delete_bd_objs [get_bd_nets axi_ad9680_adc_dovf] +delete_bd_objs [get_bd_nets axi_ad9234_adc_clk] +delete_bd_objs [get_bd_nets axi_ad9234_adc_dwr] +delete_bd_objs [get_bd_nets axi_ad9234_adc_ddata] +delete_bd_objs [get_bd_nets axi_ad9234_adc_dsync] +delete_bd_objs [get_bd_nets axi_ad9234_adc_dovf] -connect_bd_net -net [get_bd_nets axi_daq2_gt_rx_rst] [get_bd_pins plddr3_fifo/adc_rst] [get_bd_pins axi_daq2_gt/rx_rst] -connect_bd_net -net [get_bd_nets sys_fmc_dma_resetn] [get_bd_pins plddr3_fifo/dma_rstn] [get_bd_pins sys_fmc_dma_sync_reset/sync_resetn] -connect_bd_net -net axi_ad9680_dma_xfer_req [get_bd_pins axi_ad9680_dma/fifo_wr_xfer_req] [get_bd_pins plddr3_fifo/axi_xfer_req] +connect_bd_net -net [get_bd_nets axi_fmcadc3_gt_rx_rst] [get_bd_pins plddr3_fifo/adc_rst] [get_bd_pins axi_fmcadc3_gt/rx_rst] +connect_bd_net -net [get_bd_nets sys_fmc_dma_resetn] [get_bd_pins plddr3_fifo/dma_rstn] [get_bd_pins sys_fmc_dma_sync_reset/sync_resetn] +connect_bd_net -net axi_ad9234_dma_xfer_req [get_bd_pins axi_ad9234_dma/fifo_wr_xfer_req] [get_bd_pins plddr3_fifo/axi_xfer_req] -connect_bd_net -net axi_ad9680_adc_clk [get_bd_pins axi_ad9680_core/adc_clk] [get_bd_pins plddr3_fifo/adc_clk] -connect_bd_net -net axi_ad9680_adc_dovf [get_bd_pins axi_ad9680_core/adc_dovf] [get_bd_pins plddr3_fifo/adc_wovf] -connect_bd_net -net axi_ad9680_adc_dwr [get_bd_ports adc_dwr] [get_bd_pins plddr3_fifo/adc_wr] -connect_bd_net -net axi_ad9680_adc_ddata [get_bd_ports adc_ddata] [get_bd_pins plddr3_fifo/adc_wdata] +connect_bd_net -net axi_ad9234_adc_clk [get_bd_pins axi_ad9234_core_0/adc_clk] [get_bd_pins plddr3_fifo/adc_clk] +connect_bd_net -net axi_ad9234_adc_dovf [get_bd_pins axi_ad9234_core_0/adc_dovf] [get_bd_pins plddr3_fifo/adc_wovf] +connect_bd_net -net axi_ad9234_adc_dwr [get_bd_ports adc_dwr] [get_bd_pins plddr3_fifo/adc_wr] +connect_bd_net -net axi_ad9234_adc_ddata [get_bd_ports adc_ddata] [get_bd_pins plddr3_fifo/adc_wdata] -connect_bd_net -net axi_ad9680_dma_clk [get_bd_pins plddr3_fifo/dma_clk] [get_bd_pins axi_ad9680_dma/fifo_wr_clk] -connect_bd_net -net axi_ad9680_dma_dwr [get_bd_pins plddr3_fifo/dma_wr] [get_bd_pins axi_ad9680_dma/fifo_wr_en] -connect_bd_net -net axi_ad9680_dma_ddata [get_bd_pins plddr3_fifo/dma_wdata] [get_bd_pins axi_ad9680_dma/fifo_wr_din] -connect_bd_net -net axi_ad9680_dma_dovf [get_bd_pins plddr3_fifo/dma_wovf] [get_bd_pins axi_ad9680_dma/fifo_wr_overflow] -connect_bd_net -net axi_ad9680_adc_dsync [get_bd_ports adc_dsync] [get_bd_pins axi_ad9680_dma/fifo_wr_sync] +connect_bd_net -net axi_ad9234_dma_clk [get_bd_pins plddr3_fifo/dma_clk] [get_bd_pins axi_ad9234_dma/fifo_wr_clk] +connect_bd_net -net axi_ad9234_dma_dwr [get_bd_pins plddr3_fifo/dma_wr] [get_bd_pins axi_ad9234_dma/fifo_wr_en] +connect_bd_net -net axi_ad9234_dma_ddata [get_bd_pins plddr3_fifo/dma_wdata] [get_bd_pins axi_ad9234_dma/fifo_wr_din] +connect_bd_net -net axi_ad9234_dma_dovf [get_bd_pins plddr3_fifo/dma_wovf] [get_bd_pins axi_ad9234_dma/fifo_wr_overflow] +connect_bd_net -net axi_ad9234_adc_dsync [get_bd_ports adc_dsync] [get_bd_pins axi_ad9234_dma/fifo_wr_sync] -connect_bd_net -net axi_ad9680_adc_clk [get_bd_ports adc_clk] -connect_bd_net -net axi_ad9680_adc_ddata [get_bd_pins ila_jesd_rx_mon/PROBE3] +connect_bd_net -net axi_ad9234_adc_clk [get_bd_ports adc_clk] +connect_bd_net -net axi_ad9234_adc_ddata [get_bd_pins ila_jesd_rx_mon/PROBE3] -set ila_dma_mon [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:3.0 ila_dma_mon] +set ila_dma_mon [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:4.0 ila_dma_mon] +set_property -dict [list CONFIG.C_MONITOR_TYPE {Native}] $ila_dma_mon set_property -dict [list CONFIG.C_NUM_OF_PROBES {4}] $ila_dma_mon set_property -dict [list CONFIG.C_PROBE0_WIDTH {1}] $ila_dma_mon set_property -dict [list CONFIG.C_PROBE1_WIDTH {1}] $ila_dma_mon set_property -dict [list CONFIG.C_PROBE2_WIDTH {64}] $ila_dma_mon set_property -dict [list CONFIG.C_PROBE3_WIDTH {5}] $ila_dma_mon -connect_bd_net -net axi_ad9680_dma_clk [get_bd_pins ila_dma_mon/clk] -connect_bd_net -net axi_ad9680_dma_dwr [get_bd_pins ila_dma_mon/probe0] -connect_bd_net -net axi_ad9680_dma_xfer_req [get_bd_pins ila_dma_mon/probe1] -connect_bd_net -net axi_ad9680_dma_ddata [get_bd_pins ila_dma_mon/probe2] +connect_bd_net -net axi_ad9234_dma_clk [get_bd_pins ila_dma_mon/clk] +connect_bd_net -net axi_ad9234_dma_dwr [get_bd_pins ila_dma_mon/probe0] +connect_bd_net -net axi_ad9234_dma_xfer_req [get_bd_pins ila_dma_mon/probe1] +connect_bd_net -net axi_ad9234_dma_ddata [get_bd_pins ila_dma_mon/probe2] connect_bd_net -net axi_xfer_status [get_bd_pins ila_dma_mon/probe3] [get_bd_pins plddr3_fifo/axi_xfer_status] diff --git a/projects/fmcadc3/zc706/system_constr.xdc b/projects/fmcadc3/zc706/system_constr.xdc index ff599d9e8..9b8b8a799 100644 --- a/projects/fmcadc3/zc706/system_constr.xdc +++ b/projects/fmcadc3/zc706/system_constr.xdc @@ -1,74 +1,58 @@ -# daq2 +# fmcadc3 -set_property -dict {PACKAGE_PIN AA8 } [get_ports rx_ref_clk_p] ; ## B20 FMC_HPC_GBTCLK1_M2C_P -set_property -dict {PACKAGE_PIN AA7 } [get_ports rx_ref_clk_n] ; ## B21 FMC_HPC_GBTCLK1_M2C_N -set_property -dict {PACKAGE_PIN AE8 } [get_ports rx_data_p[0]] ; ## A10 FMC_HPC_DP3_M2C_P -set_property -dict {PACKAGE_PIN AE7 } [get_ports rx_data_n[0]] ; ## A11 FMC_HPC_DP3_M2C_N -set_property -dict {PACKAGE_PIN AH10} [get_ports rx_data_p[1]] ; ## C06 FMC_HPC_DP0_M2C_P -set_property -dict {PACKAGE_PIN AH9 } [get_ports rx_data_n[1]] ; ## C07 FMC_HPC_DP0_M2C_N -set_property -dict {PACKAGE_PIN AG8 } [get_ports rx_data_p[2]] ; ## A06 FMC_HPC_DP2_M2C_P -set_property -dict {PACKAGE_PIN AG7 } [get_ports rx_data_n[2]] ; ## A07 FMC_HPC_DP2_M2C_N -set_property -dict {PACKAGE_PIN AJ8 } [get_ports rx_data_p[3]] ; ## A02 FMC_HPC_DP1_M2C_P -set_property -dict {PACKAGE_PIN AJ7 } [get_ports rx_data_n[3]] ; ## A03 FMC_HPC_DP1_M2C_N -set_property -dict {PACKAGE_PIN AG21 IOSTANDARD LVDS_25} [get_ports rx_sync_p] ; ## D08 FMC_HPC_LA01_CC_P -set_property -dict {PACKAGE_PIN AH21 IOSTANDARD LVDS_25} [get_ports rx_sync_n] ; ## D09 FMC_HPC_LA01_CC_N -set_property -dict {PACKAGE_PIN AH19 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_sysref_p] ; ## G09 FMC_HPC_LA03_P -set_property -dict {PACKAGE_PIN AJ19 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_sysref_n] ; ## G10 FMC_HPC_LA03_N +set_property -dict {PACKAGE_PIN AD10} [get_ports rx_ref_clk_p] ; ## D04 FMC_HPC_GBTCLK0_M2C_P +set_property -dict {PACKAGE_PIN AD9 } [get_ports rx_ref_clk_n] ; ## D05 FMC_HPC_GBTCLK0_M2C_N +set_property -dict {PACKAGE_PIN AH6 } [get_ports rx_data_p[0]] ; ## A14 FMC_HPC_DP4_M2C_P +set_property -dict {PACKAGE_PIN AH5 } [get_ports rx_data_n[0]] ; ## A15 FMC_HPC_DP4_M2C_N +set_property -dict {PACKAGE_PIN AG4 } [get_ports rx_data_p[1]] ; ## A18 FMC_HPC_DP5_M2C_P +set_property -dict {PACKAGE_PIN AG3 } [get_ports rx_data_n[1]] ; ## A19 FMC_HPC_DP5_M2C_N +set_property -dict {PACKAGE_PIN AF6 } [get_ports rx_data_p[2]] ; ## B16 FMC_HPC_DP6_M2C_P +set_property -dict {PACKAGE_PIN AF5 } [get_ports rx_data_n[2]] ; ## B17 FMC_HPC_DP6_M2C_N +set_property -dict {PACKAGE_PIN AD6 } [get_ports rx_data_p[3]] ; ## B12 FMC_HPC_DP7_M2C_P +set_property -dict {PACKAGE_PIN AD5 } [get_ports rx_data_n[3]] ; ## B13 FMC_HPC_DP7_M2C_N +set_property -dict {PACKAGE_PIN AE8 } [get_ports rx_data_p[4]] ; ## A10 FMC_HPC_DP3_M2C_P +set_property -dict {PACKAGE_PIN AE7 } [get_ports rx_data_n[4]] ; ## A11 FMC_HPC_DP3_M2C_N +set_property -dict {PACKAGE_PIN AH10} [get_ports rx_data_p[5]] ; ## C06 FMC_HPC_DP0_M2C_P +set_property -dict {PACKAGE_PIN AH9 } [get_ports rx_data_n[5]] ; ## C07 FMC_HPC_DP0_M2C_N +set_property -dict {PACKAGE_PIN AG8 } [get_ports rx_data_p[6]] ; ## A06 FMC_HPC_DP2_M2C_P +set_property -dict {PACKAGE_PIN AG7 } [get_ports rx_data_n[6]] ; ## A07 FMC_HPC_DP2_M2C_N +set_property -dict {PACKAGE_PIN AJ8 } [get_ports rx_data_p[7]] ; ## A02 FMC_HPC_DP1_M2C_P +set_property -dict {PACKAGE_PIN AJ7 } [get_ports rx_data_n[7]] ; ## A03 FMC_HPC_DP1_M2C_N +set_property -dict {PACKAGE_PIN AF23 IOSTANDARD LVDS_25} [get_ports rx_sync_0_p] ; ## G15 FMC_HPC_LA12_P +set_property -dict {PACKAGE_PIN AF24 IOSTANDARD LVDS_25} [get_ports rx_sync_0_n] ; ## G16 FMC_HPC_LA12_N +set_property -dict {PACKAGE_PIN AJ20 IOSTANDARD LVDS_25} [get_ports rx_sync_1_p] ; ## H10 FMC_HPC_LA04_P +set_property -dict {PACKAGE_PIN AK20 IOSTANDARD LVDS_25} [get_ports rx_sync_1_n] ; ## H11 FMC_HPC_LA04_N +set_property -dict {PACKAGE_PIN AG21 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_sysref_p] ; ## D08 FMC_HPC_LA01_CC_P +set_property -dict {PACKAGE_PIN AH21 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_sysref_n] ; ## D09 FMC_HPC_LA01_CC_N -set_property -dict {PACKAGE_PIN AD10} [get_ports tx_ref_clk_p] ; ## D04 FMC_HPC_GBTCLK0_M2C_P -set_property -dict {PACKAGE_PIN AD9 } [get_ports tx_ref_clk_n] ; ## D05 FMC_HPC_GBTCLK0_M2C_N -set_property -dict {PACKAGE_PIN AK2 } [get_ports tx_data_p[0]] ; ## A30 FMC_HPC_DP3_C2M_P -set_property -dict {PACKAGE_PIN AK1 } [get_ports tx_data_n[0]] ; ## A31 FMC_HPC_DP3_C2M_N -set_property -dict {PACKAGE_PIN AJ4 } [get_ports tx_data_p[1]] ; ## A26 FMC_HPC_DP2_C2M_P -set_property -dict {PACKAGE_PIN AJ3 } [get_ports tx_data_n[1]] ; ## A27 FMC_HPC_DP2_C2M_N -set_property -dict {PACKAGE_PIN AK6 } [get_ports tx_data_p[2]] ; ## A22 FMC_HPC_DP1_C2M_P -set_property -dict {PACKAGE_PIN AK5 } [get_ports tx_data_n[2]] ; ## A23 FMC_HPC_DP1_C2M_N -set_property -dict {PACKAGE_PIN AK10} [get_ports tx_data_p[3]] ; ## C02 FMC_HPC_DP0_C2M_P -set_property -dict {PACKAGE_PIN AK9 } [get_ports tx_data_n[3]] ; ## C03 FMC_HPC_DP0_C2M_N -set_property -dict {PACKAGE_PIN AK17 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports tx_sync_p] ; ## H07 FMC_HPC_LA02_P -set_property -dict {PACKAGE_PIN AK18 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports tx_sync_n] ; ## H08 FMC_HPC_LA02_N -set_property -dict {PACKAGE_PIN AJ20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports tx_sysref_p] ; ## H10 FMC_HPC_LA04_P -set_property -dict {PACKAGE_PIN AK20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports tx_sysref_n] ; ## H11 FMC_HPC_LA04_N +set_property -dict {PACKAGE_PIN AG19 IOSTANDARD LVCMOS25} [get_ports ad9528_csn] ; ## G13 FMC_HPC_LA08_N +set_property -dict {PACKAGE_PIN AH19 IOSTANDARD LVCMOS25} [get_ports ada4961_1a_csn] ; ## G09 FMC_HPC_LA03_P +set_property -dict {PACKAGE_PIN AJ19 IOSTANDARD LVCMOS25} [get_ports ada4961_1b_csn] ; ## G10 FMC_HPC_LA03_N +set_property -dict {PACKAGE_PIN AJ23 IOSTANDARD LVCMOS25} [get_ports ad9234_1_csn] ; ## H13 FMC_HPC_LA07_P +set_property -dict {PACKAGE_PIN AG22 IOSTANDARD LVCMOS25} [get_ports ada4961_2a_csn] ; ## C10 FMC_HPC_LA06_P +set_property -dict {PACKAGE_PIN AH22 IOSTANDARD LVCMOS25} [get_ports ada4961_2b_csn] ; ## C11 FMC_HPC_LA06_N +set_property -dict {PACKAGE_PIN AJ24 IOSTANDARD LVCMOS25} [get_ports ad9234_2_csn] ; ## H14 FMC_HPC_LA07_N +set_property -dict {PACKAGE_PIN AA23 IOSTANDARD LVCMOS25} [get_ports spi_sclk] ; ## D18 FMC_HPC_LA13_N +set_property -dict {PACKAGE_PIN AA22 IOSTANDARD LVCMOS25} [get_ports spi_sdio] ; ## D17 FMC_HPC_LA13_P -set_property -dict {PACKAGE_PIN AH23 IOSTANDARD LVCMOS25} [get_ports spi_csn_clk] ; ## D11 FMC_HPC_LA05_P -set_property -dict {PACKAGE_PIN AG24 IOSTANDARD LVCMOS25} [get_ports spi_csn_dac] ; ## C14 FMC_HPC_LA10_P -set_property -dict {PACKAGE_PIN AE21 IOSTANDARD LVCMOS25} [get_ports spi_csn_adc] ; ## D15 FMC_HPC_LA09_N -set_property -dict {PACKAGE_PIN AH24 IOSTANDARD LVCMOS25} [get_ports spi_clk] ; ## D12 FMC_HPC_LA05_N -set_property -dict {PACKAGE_PIN AD21 IOSTANDARD LVCMOS25} [get_ports spi_sdio] ; ## D14 FMC_HPC_LA09_P - -set_property -dict {PACKAGE_PIN AH22 IOSTANDARD LVCMOS25} [get_ports clkd_reset] ; ## C11 FMC_HPC_LA06_N -set_property -dict {PACKAGE_PIN AF19 IOSTANDARD LVCMOS25} [get_ports clkd_sync] ; ## G12 FMC_HPC_LA08_P -set_property -dict {PACKAGE_PIN AG19 IOSTANDARD LVCMOS25} [get_ports clkd_pd] ; ## G13 FMC_HPC_LA08_N -set_property -dict {PACKAGE_PIN AG25 IOSTANDARD LVCMOS25} [get_ports dac_reset] ; ## C15 FMC_HPC_LA10_N -set_property -dict {PACKAGE_PIN AF24 IOSTANDARD LVCMOS25} [get_ports dac_txen] ; ## G16 FMC_HPC_LA12_N -set_property -dict {PACKAGE_PIN AG22 IOSTANDARD LVCMOS25} [get_ports adc_pd] ; ## C10 FMC_HPC_LA06_P - -set_property -dict {PACKAGE_PIN AA22 IOSTANDARD LVCMOS25} [get_ports clkd_status[0]] ; ## D17 FMC_HPC_LA13_P -set_property -dict {PACKAGE_PIN AA23 IOSTANDARD LVCMOS25} [get_ports clkd_status[1]] ; ## D18 FMC_HPC_LA13_N -set_property -dict {PACKAGE_PIN AF23 IOSTANDARD LVCMOS25} [get_ports dac_irq] ; ## G15 FMC_HPC_LA12_P -set_property -dict {PACKAGE_PIN AD23 IOSTANDARD LVCMOS25} [get_ports adc_fda] ; ## H16 FMC_HPC_LA11_P -set_property -dict {PACKAGE_PIN AE23 IOSTANDARD LVCMOS25} [get_ports adc_fdb] ; ## H17 FMC_HPC_LA11_N +set_property -dict {PACKAGE_PIN AE21 IOSTANDARD LVCMOS25} [get_ports ad9528_rstn] ; ## D15 FMC_HPC_LA09_N +set_property -dict {PACKAGE_PIN AD21 IOSTANDARD LVCMOS25} [get_ports ad9528_status] ; ## D14 FMC_HPC_LA09_P +set_property -dict {PACKAGE_PIN AG24 IOSTANDARD LVCMOS25} [get_ports ad9234_1_fda] ; ## C14 FMC_HPC_LA10_P +set_property -dict {PACKAGE_PIN AG25 IOSTANDARD LVCMOS25} [get_ports ad9234_1_fdb] ; ## C15 FMC_HPC_LA10_N +set_property -dict {PACKAGE_PIN AD23 IOSTANDARD LVCMOS25} [get_ports ad9234_2_fda] ; ## H16 FMC_HPC_LA11_P +set_property -dict {PACKAGE_PIN AE23 IOSTANDARD LVCMOS25} [get_ports ad9234_2_fdb] ; ## H17 FMC_HPC_LA11_N # clocks -create_clock -name tx_ref_clk -period 2.00 [get_ports tx_ref_clk_p] create_clock -name rx_ref_clk -period 2.00 [get_ports rx_ref_clk_p] -create_clock -name tx_div_clk -period 4.00 [get_nets i_system_wrapper/system_i/axi_daq2_gt_tx_clk] -create_clock -name rx_div_clk -period 4.00 [get_nets i_system_wrapper/system_i/axi_daq2_gt_rx_clk] +create_clock -name rx_div_clk -period 4.00 [get_nets i_system_wrapper/system_i/axi_fmcadc3_gt_rx_clk] create_clock -name fmc_dma_clk -period 5.00 [get_pins i_system_wrapper/system_i/sys_ps7/FCLK_CLK2] create_clock -name pl_ddr_clk -period 5.00 [get_pins i_system_wrapper/system_i/plddr3_fifo/axi_ddr_cntrl/ui_clk] create_clock -name pl_dma_clk -period 15.62 [get_pins i_system_wrapper/system_i/plddr3_fifo/axi_ddr_cntrl/ui_addn_clk_0] -set_clock_groups -asynchronous -group {tx_div_clk} set_clock_groups -asynchronous -group {rx_div_clk} set_clock_groups -asynchronous -group {fmc_dma_clk} set_clock_groups -asynchronous -group {pl_ddr_clk} set_clock_groups -asynchronous -group {pl_dma_clk} -set_false_path -through [get_pins i_system_wrapper/system_i/axi_daq2_gt/inst/i_up_gt/i_drp_rst_reg/i_rst_reg/PRE] -set_false_path -through [get_pins i_system_wrapper/system_i/axi_daq2_gt/inst/i_up_gt/i_gt_pll_rst_reg/i_rst_reg/PRE] -set_false_path -through [get_pins i_system_wrapper/system_i/axi_daq2_gt/inst/i_up_gt/i_gt_rx_rst_reg/i_rst_reg/PRE] -set_false_path -through [get_pins i_system_wrapper/system_i/axi_daq2_gt/inst/i_up_gt/i_gt_tx_rst_reg/i_rst_reg/PRE] -set_false_path -through [get_pins i_system_wrapper/system_i/axi_daq2_gt/inst/i_up_gt/i_rx_rst_reg/i_rst_reg/PRE] -set_false_path -through [get_pins i_system_wrapper/system_i/axi_daq2_gt/inst/i_up_gt/i_tx_rst_reg/i_rst_reg/PRE] diff --git a/projects/fmcadc3/zc706/system_project.tcl b/projects/fmcadc3/zc706/system_project.tcl index 73e0af659..8df512560 100644 --- a/projects/fmcadc3/zc706/system_project.tcl +++ b/projects/fmcadc3/zc706/system_project.tcl @@ -4,14 +4,14 @@ source ../../scripts/adi_env.tcl source $ad_hdl_dir/projects/scripts/adi_project.tcl -adi_project_create daq2_zc706 -adi_project_files daq2_zc706 [list \ - "../common/daq2_spi.v" \ +adi_project_create fmcadc3_zc706 +adi_project_files fmcadc3_zc706 [list \ + "../common/fmcadc3_spi.v" \ "system_top.v" \ "system_constr.xdc"\ "$ad_hdl_dir/library/common/ad_iobuf.v" \ "$ad_hdl_dir/projects/common/zc706/zc706_system_constr.xdc" ] -adi_project_run daq2_zc706 +adi_project_run fmcadc3_zc706 diff --git a/projects/fmcadc3/zc706/system_top.v b/projects/fmcadc3/zc706/system_top.v index 17917e91c..089932a70 100644 --- a/projects/fmcadc3/zc706/system_top.v +++ b/projects/fmcadc3/zc706/system_top.v @@ -100,35 +100,27 @@ module system_top ( rx_ref_clk_n, rx_sysref_p, rx_sysref_n, - rx_sync_p, - rx_sync_n, + rx_sync_0_p, + rx_sync_0_n, + rx_sync_1_p, + rx_sync_1_n, rx_data_p, rx_data_n, - tx_ref_clk_p, - tx_ref_clk_n, - tx_sysref_p, - tx_sysref_n, - tx_sync_p, - tx_sync_n, - tx_data_p, - tx_data_n, - - adc_fdb, - adc_fda, - dac_irq, - clkd_status, - - adc_pd, - dac_txen, - dac_reset, - clkd_pd, - clkd_sync, - clkd_reset, + ad9528_rstn, + ad9528_status, + ad9234_1_fda; + ad9234_1_fdb; + ad9234_2_fda; + ad9234_2_fdb; - spi_csn_clk, - spi_csn_dac, - spi_csn_adc, + ad9528_csn, + ada4961_1a_csn, + ada4961_1b_csn, + ad9234_1_csn, + ada4961_2a_csn, + ada4961_2b_csn, + ad9234_2_csn, spi_clk, spi_sdio); @@ -191,175 +183,162 @@ module system_top ( input rx_ref_clk_n; input rx_sysref_p; input rx_sysref_n; - output rx_sync_p; - output rx_sync_n; - input [ 3:0] rx_data_p; - input [ 3:0] rx_data_n; + output rx_sync_0_p; + output rx_sync_0_n; + output rx_sync_1_p; + output rx_sync_1_n; + input [ 7:0] rx_data_p; + input [ 7:0] rx_data_n; - input tx_ref_clk_p; - input tx_ref_clk_n; - input tx_sysref_p; - input tx_sysref_n; - input tx_sync_p; - input tx_sync_n; - output [ 3:0] tx_data_p; - output [ 3:0] tx_data_n; + inout ad9528_rstn; + inout ad9528_status; + inout ad9234_1_fda; + inout ad9234_1_fdb; + inout ad9234_2_fda; + inout ad9234_2_fdb; - inout adc_fdb; - inout adc_fda; - inout dac_irq; - inout [ 1:0] clkd_status; - - inout adc_pd; - inout dac_txen; - inout dac_reset; - inout clkd_pd; - inout clkd_sync; - inout clkd_reset; - - output spi_csn_clk; - output spi_csn_dac; - output spi_csn_adc; + output ad9528_csn; + output ada4961_1a_csn; + output ada4961_1b_csn; + output ad9234_1_csn; + output ada4961_2a_csn; + output ada4961_2b_csn; + output ad9234_2_csn; output spi_clk; inout spi_sdio; // internal registers - reg dac_drd = 'd0; - reg [63:0] dac_ddata_0 = 'd0; - reg [63:0] dac_ddata_1 = 'd0; - reg [63:0] dac_ddata_2 = 'd0; - reg [63:0] dac_ddata_3 = 'd0; + reg [ 1:0] adc_dcnt = 'd0; reg adc_dsync = 'd0; reg adc_dwr = 'd0; - reg [127:0] adc_ddata = 'd0; + reg [255:0] adc_ddata = 'd0; // internal signals - wire [42:0] gpio_i; - wire [42:0] gpio_o; - wire [42:0] gpio_t; + wire [37:0] gpio_i; + wire [37:0] gpio_o; + wire [37:0] gpio_t; wire rx_ref_clk; wire rx_sysref; wire rx_sync; - wire tx_ref_clk; - wire tx_sysref; - wire tx_sync; - wire [ 2:0] spi_csn; wire spi_mosi; wire spi_miso; - wire dac_clk; - wire [127:0] dac_ddata; - wire dac_enable_0; - wire dac_enable_1; - wire dac_enable_2; - wire dac_enable_3; - wire dac_valid_0; - wire dac_valid_1; - wire dac_valid_2; - wire dac_valid_3; wire adc_clk; wire [63:0] adc_data_0; wire [63:0] adc_data_1; + wire [63:0] adc_data_2; + wire [63:0] adc_data_3; wire adc_enable_0; wire adc_enable_1; + wire adc_enable_2; + wire adc_enable_3; wire adc_valid_0; wire adc_valid_1; + wire adc_valid_2; + wire adc_valid_3; + wire [255:0] gt_data; - // adc-dac data - - always @(posedge dac_clk) begin - case ({dac_enable_1, dac_enable_0}) - 2'b11: begin - dac_drd <= dac_valid_0 & dac_valid_1; - dac_ddata_0[63:48] <= dac_ddata[111: 96]; - dac_ddata_0[47:32] <= dac_ddata[ 79: 64]; - dac_ddata_0[31:16] <= dac_ddata[ 47: 32]; - dac_ddata_0[15: 0] <= dac_ddata[ 15: 0]; - dac_ddata_1[63:48] <= dac_ddata[127:112]; - dac_ddata_1[47:32] <= dac_ddata[ 95: 80]; - dac_ddata_1[31:16] <= dac_ddata[ 63: 48]; - dac_ddata_1[15: 0] <= dac_ddata[ 31: 16]; - dac_ddata_2 <= 64'd0; - dac_ddata_3 <= 64'd0; - end - 2'b10: begin - dac_drd <= dac_valid_1 & ~dac_drd; - dac_ddata_0 <= 64'd0; - if (dac_drd == 1'b1) begin - dac_ddata_1[63:48] <= dac_ddata[127:112]; - dac_ddata_1[47:32] <= dac_ddata[111: 96]; - dac_ddata_1[31:16] <= dac_ddata[ 95: 80]; - dac_ddata_1[15: 0] <= dac_ddata[ 79: 64]; - end else begin - dac_ddata_1[63:48] <= dac_ddata[ 63: 48]; - dac_ddata_1[47:32] <= dac_ddata[ 47: 32]; - dac_ddata_1[31:16] <= dac_ddata[ 31: 16]; - dac_ddata_1[15: 0] <= dac_ddata[ 15: 0]; - end - dac_ddata_2 <= 64'd0; - dac_ddata_3 <= 64'd0; - end - 2'b01: begin - dac_drd <= dac_valid_0 & ~dac_drd; - if (dac_drd == 1'b1) begin - dac_ddata_0[63:48] <= dac_ddata[127:112]; - dac_ddata_0[47:32] <= dac_ddata[111: 96]; - dac_ddata_0[31:16] <= dac_ddata[ 95: 80]; - dac_ddata_0[15: 0] <= dac_ddata[ 79: 64]; - end else begin - dac_ddata_0[63:48] <= dac_ddata[ 63: 48]; - dac_ddata_0[47:32] <= dac_ddata[ 47: 32]; - dac_ddata_0[31:16] <= dac_ddata[ 31: 16]; - dac_ddata_0[15: 0] <= dac_ddata[ 15: 0]; - end - dac_ddata_1 <= 64'd0; - dac_ddata_2 <= 64'd0; - dac_ddata_3 <= 64'd0; - end - default: begin - dac_drd <= 1'b0; - dac_ddata_0 <= 64'd0; - dac_ddata_1 <= 64'd0; - dac_ddata_2 <= 64'd0; - dac_ddata_3 <= 64'd0; - end - endcase - end + // adc-pack place holder always @(posedge adc_clk) begin - case ({adc_enable_1, adc_enable_0}) - 2'b11: begin + adc_dcnt <= adc_dcnt + 1'b1; + case ({adc_enable_3, adc_enable_2, adc_enable_1, adc_enable_0}) + 4'b1111: begin adc_dsync <= 1'b1; - adc_dwr <= adc_valid_1 & adc_valid_0; - adc_ddata[127:112] <= adc_data_1[63:48]; - adc_ddata[111: 96] <= adc_data_0[63:48]; - adc_ddata[ 95: 80] <= adc_data_1[47:32]; - adc_ddata[ 79: 64] <= adc_data_0[47:32]; - adc_ddata[ 63: 48] <= adc_data_1[31:16]; - adc_ddata[ 47: 32] <= adc_data_0[31:16]; + adc_dwr <= adc_valid_3 & adc_valid_2 & adc_valid_1 & adc_valid_0; + adc_ddata[255:240] <= adc_data_3[63:48]; + adc_ddata[239:224] <= adc_data_2[63:48]; + adc_ddata[223:208] <= adc_data_1[63:48]; + adc_ddata[207:192] <= adc_data_0[63:48]; + adc_ddata[191:176] <= adc_data_3[47:32]; + adc_ddata[175:160] <= adc_data_2[47:32]; + adc_ddata[159:144] <= adc_data_1[47:32]; + adc_ddata[143:128] <= adc_data_0[47:32]; + adc_ddata[127:112] <= adc_data_3[31:16]; + adc_ddata[111: 96] <= adc_data_2[31:16]; + adc_ddata[ 95: 80] <= adc_data_1[31:16]; + adc_ddata[ 79: 64] <= adc_data_0[31:16]; + adc_ddata[ 63: 48] <= adc_data_3[15: 0]; + adc_ddata[ 47: 32] <= adc_data_2[15: 0]; adc_ddata[ 31: 16] <= adc_data_1[15: 0]; adc_ddata[ 15: 0] <= adc_data_0[15: 0]; end - 2'b10: begin + 4'b0001: begin adc_dsync <= 1'b1; - adc_dwr <= adc_valid_1 & ~adc_dwr; - adc_ddata[127:112] <= adc_data_1[63:48]; - adc_ddata[111: 96] <= adc_data_1[47:32]; - adc_ddata[ 95: 80] <= adc_data_1[31:16]; - adc_ddata[ 79: 64] <= adc_data_1[15: 0]; + adc_dwr <= adc_valid_0 & adc_dcnt[0] & adc_dcnt[1]; + adc_ddata[255:240] <= adc_data_0[63:48]; + adc_ddata[239:224] <= adc_data_0[47:32]; + adc_ddata[223:208] <= adc_data_0[31:16]; + adc_ddata[207:192] <= adc_data_0[15: 0]; + adc_ddata[191:176] <= adc_ddata[255:240]; + adc_ddata[175:160] <= adc_ddata[239:224]; + adc_ddata[159:144] <= adc_ddata[223:208]; + adc_ddata[143:128] <= adc_ddata[207:192]; + adc_ddata[127:112] <= adc_ddata[191:176]; + adc_ddata[111: 96] <= adc_ddata[175:160]; + adc_ddata[ 95: 80] <= adc_ddata[159:144]; + adc_ddata[ 79: 64] <= adc_ddata[143:128]; adc_ddata[ 63: 48] <= adc_ddata[127:112]; adc_ddata[ 47: 32] <= adc_ddata[111: 96]; adc_ddata[ 31: 16] <= adc_ddata[ 95: 80]; adc_ddata[ 15: 0] <= adc_ddata[ 79: 64]; end - 2'b01: begin + 4'b0010: begin adc_dsync <= 1'b1; - adc_dwr <= adc_valid_0 & ~adc_dwr; - adc_ddata[127:112] <= adc_data_0[63:48]; - adc_ddata[111: 96] <= adc_data_0[47:32]; - adc_ddata[ 95: 80] <= adc_data_0[31:16]; - adc_ddata[ 79: 64] <= adc_data_0[15: 0]; + adc_dwr <= adc_valid_1 & adc_dcnt[0] & adc_dcnt[1]; + adc_ddata[255:240] <= adc_data_1[63:48]; + adc_ddata[239:224] <= adc_data_1[47:32]; + adc_ddata[223:208] <= adc_data_1[31:16]; + adc_ddata[207:192] <= adc_data_1[15: 0]; + adc_ddata[191:176] <= adc_ddata[255:240]; + adc_ddata[175:160] <= adc_ddata[239:224]; + adc_ddata[159:144] <= adc_ddata[223:208]; + adc_ddata[143:128] <= adc_ddata[207:192]; + adc_ddata[127:112] <= adc_ddata[191:176]; + adc_ddata[111: 96] <= adc_ddata[175:160]; + adc_ddata[ 95: 80] <= adc_ddata[159:144]; + adc_ddata[ 79: 64] <= adc_ddata[143:128]; + adc_ddata[ 63: 48] <= adc_ddata[127:112]; + adc_ddata[ 47: 32] <= adc_ddata[111: 96]; + adc_ddata[ 31: 16] <= adc_ddata[ 95: 80]; + adc_ddata[ 15: 0] <= adc_ddata[ 79: 64]; + end + 4'b0100: begin + adc_dsync <= 1'b1; + adc_dwr <= adc_valid_2 & adc_dcnt[0] & adc_dcnt[1]; + adc_ddata[255:240] <= adc_data_2[63:48]; + adc_ddata[239:224] <= adc_data_2[47:32]; + adc_ddata[223:208] <= adc_data_2[31:16]; + adc_ddata[207:192] <= adc_data_2[15: 0]; + adc_ddata[191:176] <= adc_ddata[255:240]; + adc_ddata[175:160] <= adc_ddata[239:224]; + adc_ddata[159:144] <= adc_ddata[223:208]; + adc_ddata[143:128] <= adc_ddata[207:192]; + adc_ddata[127:112] <= adc_ddata[191:176]; + adc_ddata[111: 96] <= adc_ddata[175:160]; + adc_ddata[ 95: 80] <= adc_ddata[159:144]; + adc_ddata[ 79: 64] <= adc_ddata[143:128]; + adc_ddata[ 63: 48] <= adc_ddata[127:112]; + adc_ddata[ 47: 32] <= adc_ddata[111: 96]; + adc_ddata[ 31: 16] <= adc_ddata[ 95: 80]; + adc_ddata[ 15: 0] <= adc_ddata[ 79: 64]; + end + 4'b1000: begin + adc_dsync <= 1'b1; + adc_dwr <= adc_valid_3 & adc_dcnt[0] & adc_dcnt[1]; + adc_ddata[255:240] <= adc_data_3[63:48]; + adc_ddata[239:224] <= adc_data_3[47:32]; + adc_ddata[223:208] <= adc_data_3[31:16]; + adc_ddata[207:192] <= adc_data_3[15: 0]; + adc_ddata[191:176] <= adc_ddata[255:240]; + adc_ddata[175:160] <= adc_ddata[239:224]; + adc_ddata[159:144] <= adc_ddata[223:208]; + adc_ddata[143:128] <= adc_ddata[207:192]; + adc_ddata[127:112] <= adc_ddata[191:176]; + adc_ddata[111: 96] <= adc_ddata[175:160]; + adc_ddata[ 95: 80] <= adc_ddata[159:144]; + adc_ddata[ 79: 64] <= adc_ddata[143:128]; adc_ddata[ 63: 48] <= adc_ddata[127:112]; adc_ddata[ 47: 32] <= adc_ddata[111: 96]; adc_ddata[ 31: 16] <= adc_ddata[ 95: 80]; @@ -368,17 +347,11 @@ module system_top ( default: begin adc_dsync <= 1'b0; adc_dwr <= 1'b0; - adc_ddata <= 128'd0; + adc_ddata <= 256'd0; end endcase end - // spi - - assign spi_csn_adc = spi_csn[2]; - assign spi_csn_dac = spi_csn[1]; - assign spi_csn_clk = spi_csn[0]; - // instantiations IBUFDS_GTE2 i_ibufds_rx_ref_clk ( @@ -393,49 +366,40 @@ module system_top ( .IB (rx_sysref_n), .O (rx_sysref)); - OBUFDS i_obufds_rx_sync ( + OBUFDS i_obufds_rx_sync_0 ( .I (rx_sync), - .O (rx_sync_p), - .OB (rx_sync_n)); + .O (rx_sync_0_p), + .OB (rx_sync_0_n)); - IBUFDS_GTE2 i_ibufds_tx_ref_clk ( - .CEB (1'd0), - .I (tx_ref_clk_p), - .IB (tx_ref_clk_n), - .O (tx_ref_clk), - .ODIV2 ()); + OBUFDS i_obufds_rx_sync_1 ( + .I (rx_sync), + .O (rx_sync_1_p), + .OB (rx_sync_1_n)); - IBUFDS i_ibufds_tx_sysref ( - .I (tx_sysref_p), - .IB (tx_sysref_n), - .O (tx_sysref)); + assign ada4961_1a_csn = 1'b1; + assign ada4961_1b_csn = 1'b1; + assign ada4961_2a_csn = 1'b1; + assign ada4961_2b_csn = 1'b1; - IBUFDS i_ibufds_tx_sync ( - .I (tx_sync_p), - .IB (tx_sync_n), - .O (tx_sync)); - - daq2_spi i_spi ( - .spi_csn (spi_csn), + fmcadc3_spi i_spi ( + .ad9528_csn (ad9528_csn), + .ad9234_1_csn (ad9234_1_csn), + .ad9234_2_csn (ad9234_2_csn), .spi_clk (spi_clk), .spi_mosi (spi_mosi), .spi_miso (spi_miso), .spi_sdio (spi_sdio)); - ad_iobuf #(.DATA_WIDTH(26)) i_iobuf ( - .dt ({gpio_t[42:32], gpio_t[14:0]}), - .di ({gpio_o[42:32], gpio_o[14:0]}), - .do ({gpio_i[42:32], gpio_i[14:0]}), - .dio ({ adc_pd, // 42 - dac_txen, // 41 - dac_reset, // 40 - clkd_pd, // 39 - clkd_sync, // 38 - clkd_reset, // 37 - adc_fdb, // 36 - adc_fda, // 35 - dac_irq, // 34 - clkd_status, // 32 + ad_iobuf #(.DATA_WIDTH(38)) i_iobuf ( + .dt ({gpio_t[37:32], gpio_t[14:0]}), + .di ({gpio_o[37:32], gpio_o[14:0]}), + .do ({gpio_i[37:32], gpio_i[14:0]}), + .dio ({ ad9234_2_fdb, // 37 + ad9234_2_fda, // 36 + ad9234_1_fdb, // 35 + ad9234_1_fda, // 34 + ad9528_status, // 33 + ad9528_rstn, // 32 gpio_bd})); // 0 system_wrapper i_system_wrapper ( @@ -481,28 +445,22 @@ module system_top ( .adc_clk (adc_clk), .adc_data_0 (adc_data_0), .adc_data_1 (adc_data_1), + .adc_data_2 (adc_data_2), + .adc_data_3 (adc_data_3), .adc_ddata (adc_ddata), .adc_dsync (adc_dsync), .adc_dwr (adc_dwr), .adc_enable_0 (adc_enable_0), .adc_enable_1 (adc_enable_1), + .adc_enable_2 (adc_enable_2), + .adc_enable_3 (adc_enable_3), .adc_valid_0 (adc_valid_0), .adc_valid_1 (adc_valid_1), - .dac_clk (dac_clk), - .dac_ddata (dac_ddata), - .dac_ddata_0 (dac_ddata_0), - .dac_ddata_1 (dac_ddata_1), - .dac_ddata_2 (dac_ddata_2), - .dac_ddata_3 (dac_ddata_3), - .dac_drd (dac_drd), - .dac_enable_0 (dac_enable_0), - .dac_enable_1 (dac_enable_1), - .dac_enable_2 (dac_enable_2), - .dac_enable_3 (dac_enable_3), - .dac_valid_0 (dac_valid_0), - .dac_valid_1 (dac_valid_1), - .dac_valid_2 (dac_valid_2), - .dac_valid_3 (dac_valid_3), + .adc_valid_2 (adc_valid_2), + .adc_valid_3 (adc_valid_3), + .gt_data (gt_data), + .gt_data_0 (gt_data[127:0]), + .gt_data_1 (gt_data[255:128]), .hdmi_data (hdmi_data), .hdmi_data_e (hdmi_data_e), .hdmi_hsync (hdmi_hsync), @@ -518,18 +476,15 @@ module system_top ( .spdif (spdif), .spi_clk_i (spi_clk), .spi_clk_o (spi_clk), - .spi_csn_i (spi_csn), - .spi_csn_o (spi_csn), + .spi_csn_0 (ad9528_csn), + .spi_csn_1 (ad9234_1_csn), + .spi_csn_2 (ad9234_2_csn), + .spi_csn_i (1'b1), .spi_sdi_i (spi_miso), .spi_sdo_i (spi_mosi), .spi_sdo_o (spi_mosi), .sys_clk_clk_n (sys_clk_n), - .sys_clk_clk_p (sys_clk_p), - .tx_data_n (tx_data_n), - .tx_data_p (tx_data_p), - .tx_ref_clk (tx_ref_clk), - .tx_sync (tx_sync), - .tx_sysref (tx_sysref)); + .sys_clk_clk_p (sys_clk_p)); endmodule From 09387431dd5322ffdf92fd21673d4763d10574f3 Mon Sep 17 00:00:00 2001 From: Adrian Costina Date: Mon, 22 Sep 2014 14:40:11 -0400 Subject: [PATCH 05/42] fmcomms2: Improved constraints for ac701 and zc702. Fixed common design so that ILA works correctly on microblaze based systems --- projects/fmcomms2/ac701/system_constr.xdc | 4 ++-- projects/fmcomms2/common/fmcomms2_bd.tcl | 26 +++++++++++++++-------- projects/fmcomms2/zc702/system_constr.xdc | 4 ++-- 3 files changed, 21 insertions(+), 13 deletions(-) diff --git a/projects/fmcomms2/ac701/system_constr.xdc b/projects/fmcomms2/ac701/system_constr.xdc index 07ffbca77..2db1e7675 100644 --- a/projects/fmcomms2/ac701/system_constr.xdc +++ b/projects/fmcomms2/ac701/system_constr.xdc @@ -60,8 +60,8 @@ set_property -dict {PACKAGE_PIN E23 IOSTANDARD LVCMOS25} [get_ports spi_miso] # clocks -create_clock -name rx_clk -period 5 [get_ports rx_clk_in_p] -create_clock -name ad9361_clk -period 5 [get_pins i_system_wrapper/system_i/axi_ad9361/clk] +create_clock -name rx_clk -period 4 [get_ports rx_clk_in_p] +create_clock -name ad9361_clk -period 4 [get_pins i_system_wrapper/system_i/axi_ad9361/clk] set_clock_groups -asynchronous -group {ad9361_clk} diff --git a/projects/fmcomms2/common/fmcomms2_bd.tcl b/projects/fmcomms2/common/fmcomms2_bd.tcl index 3a962a5c2..b9c9d505e 100644 --- a/projects/fmcomms2/common/fmcomms2_bd.tcl +++ b/projects/fmcomms2/common/fmcomms2_bd.tcl @@ -274,11 +274,11 @@ if {$sys_zynq == 0} { # memory interconnects share the same clock (fclk2) if {$sys_zynq == 1} { - set sys_fmc_dma_clk_source [get_bd_pins sys_ps7/FCLK_CLK2] - - connect_bd_net -net sys_fmc_dma_clk $sys_fmc_dma_clk_source + set sys_fmc_dma_clk_source [get_bd_pins sys_ps7/FCLK_CLK2] + connect_bd_net -net sys_fmc_dma_clk $sys_fmc_dma_clk_source } + # interconnect (mem/dac) if {$sys_zynq == 0} { @@ -339,19 +339,28 @@ if {$sys_zynq == 0} { p_sys_wfifo [current_bd_instance .] sys_wfifo_2 16 16 p_sys_wfifo [current_bd_instance .] sys_wfifo_3 16 16 - connect_bd_net -net axi_ad9361_clk [get_bd_pins sys_wfifo_0/m_clk] [get_bd_pins axi_ad9361/l_clk] - connect_bd_net -net axi_ad9361_clk [get_bd_pins sys_wfifo_1/m_clk] [get_bd_pins axi_ad9361/l_clk] - connect_bd_net -net axi_ad9361_clk [get_bd_pins sys_wfifo_2/m_clk] [get_bd_pins axi_ad9361/l_clk] - connect_bd_net -net axi_ad9361_clk [get_bd_pins sys_wfifo_3/m_clk] [get_bd_pins axi_ad9361/l_clk] + if {$sys_zynq == 0} { + connect_bd_net -net sys_200m_clk [get_bd_pins ila_adc/clk] + connect_bd_net -net sys_200m_clk [get_bd_pins sys_wfifo_0/s_clk] $sys_200m_clk_source + connect_bd_net -net sys_200m_clk [get_bd_pins sys_wfifo_1/s_clk] $sys_200m_clk_source + connect_bd_net -net sys_200m_clk [get_bd_pins sys_wfifo_2/s_clk] $sys_200m_clk_source + connect_bd_net -net sys_200m_clk [get_bd_pins sys_wfifo_3/s_clk] $sys_200m_clk_source + } else { + connect_bd_net -net sys_fmc_dma_clk [get_bd_pins ila_adc/clk] connect_bd_net -net sys_fmc_dma_clk [get_bd_pins sys_wfifo_0/s_clk] $sys_fmc_dma_clk_source connect_bd_net -net sys_fmc_dma_clk [get_bd_pins sys_wfifo_1/s_clk] $sys_fmc_dma_clk_source connect_bd_net -net sys_fmc_dma_clk [get_bd_pins sys_wfifo_2/s_clk] $sys_fmc_dma_clk_source connect_bd_net -net sys_fmc_dma_clk [get_bd_pins sys_wfifo_3/s_clk] $sys_fmc_dma_clk_source + } + + connect_bd_net -net axi_ad9361_clk [get_bd_pins sys_wfifo_0/m_clk] [get_bd_pins axi_ad9361/l_clk] + connect_bd_net -net axi_ad9361_clk [get_bd_pins sys_wfifo_1/m_clk] [get_bd_pins axi_ad9361/l_clk] + connect_bd_net -net axi_ad9361_clk [get_bd_pins sys_wfifo_2/m_clk] [get_bd_pins axi_ad9361/l_clk] + connect_bd_net -net axi_ad9361_clk [get_bd_pins sys_wfifo_3/m_clk] [get_bd_pins axi_ad9361/l_clk] connect_bd_net -net sys_100m_resetn [get_bd_pins sys_wfifo_0/rstn] $sys_100m_resetn_source connect_bd_net -net sys_100m_resetn [get_bd_pins sys_wfifo_1/rstn] $sys_100m_resetn_source connect_bd_net -net sys_100m_resetn [get_bd_pins sys_wfifo_2/rstn] $sys_100m_resetn_source connect_bd_net -net sys_100m_resetn [get_bd_pins sys_wfifo_3/rstn] $sys_100m_resetn_source - connect_bd_net -net axi_ad9361_adc_valid_i0 [get_bd_pins sys_wfifo_0/m_wr] [get_bd_pins axi_ad9361/adc_valid_i0] connect_bd_net -net axi_ad9361_adc_valid_q0 [get_bd_pins sys_wfifo_1/m_wr] [get_bd_pins axi_ad9361/adc_valid_q0] connect_bd_net -net axi_ad9361_adc_valid_i1 [get_bd_pins sys_wfifo_2/m_wr] [get_bd_pins axi_ad9361/adc_valid_i1] @@ -361,7 +370,6 @@ if {$sys_zynq == 0} { connect_bd_net -net axi_ad9361_adc_chan_i1 [get_bd_pins sys_wfifo_2/m_wdata] [get_bd_pins axi_ad9361/adc_data_i1] connect_bd_net -net axi_ad9361_adc_chan_q1 [get_bd_pins sys_wfifo_3/m_wdata] [get_bd_pins axi_ad9361/adc_data_q1] - connect_bd_net -net sys_fmc_dma_clk [get_bd_pins ila_adc/clk] connect_bd_net -net util_wfifo_0_s_wr [get_bd_pins sys_wfifo_0/s_wr] [get_bd_pins ila_adc/probe0] connect_bd_net -net util_wfifo_1_s_wr [get_bd_pins sys_wfifo_1/s_wr] [get_bd_pins ila_adc/probe1] connect_bd_net -net util_wfifo_2_s_wr [get_bd_pins sys_wfifo_2/s_wr] [get_bd_pins ila_adc/probe2] diff --git a/projects/fmcomms2/zc702/system_constr.xdc b/projects/fmcomms2/zc702/system_constr.xdc index 7dac9a31c..4ef2af723 100644 --- a/projects/fmcomms2/zc702/system_constr.xdc +++ b/projects/fmcomms2/zc702/system_constr.xdc @@ -60,8 +60,8 @@ set_property -dict {PACKAGE_PIN C18 IOSTANDARD LVCMOS25} [get_ports spi_miso] # clocks -create_clock -name rx_clk -period 5 [get_ports rx_clk_in_p] -create_clock -name ad9361_clk -period 5 [get_pins i_system_wrapper/system_i/axi_ad9361/clk] +create_clock -name rx_clk -period 4 [get_ports rx_clk_in_p] +create_clock -name ad9361_clk -period 4 [get_pins i_system_wrapper/system_i/axi_ad9361/clk] create_clock -name fmc_dma_clk -period 10.00 [get_pins i_system_wrapper/system_i/sys_ps7/FCLK_CLK2] set_clock_groups -asynchronous -group {ad9361_clk} From bc93a15229d7bfb8362c443c4269cf0363d50c52 Mon Sep 17 00:00:00 2001 From: Adrian Costina Date: Thu, 25 Sep 2014 15:25:26 -0400 Subject: [PATCH 06/42] fmcomms1: Fixed missing sample issue on ZC706. Added modifications for all other platforms --- projects/fmcomms1/ac701/system_top.v | 74 ++++++++++++++++++++++++ projects/fmcomms1/common/fmcomms1_bd.tcl | 1 + projects/fmcomms1/kc705/system_top.v | 73 +++++++++++++++++++++++ projects/fmcomms1/vc707/system_top.v | 73 +++++++++++++++++++++++ projects/fmcomms1/zc702/system_top.v | 71 +++++++++++++++++++++++ projects/fmcomms1/zc706/system_top.v | 20 +++---- projects/fmcomms1/zed/system_top.v | 71 +++++++++++++++++++++++ 7 files changed, 373 insertions(+), 10 deletions(-) diff --git a/projects/fmcomms1/ac701/system_top.v b/projects/fmcomms1/ac701/system_top.v index ffdaf0039..3f9325a38 100644 --- a/projects/fmcomms1/ac701/system_top.v +++ b/projects/fmcomms1/ac701/system_top.v @@ -181,8 +181,33 @@ module system_top ( output spdif; + // internal registers + + reg [63:0] dac_ddata_0 = 'd0; + reg [63:0] dac_ddata_1 = 'd0; + reg dac_dma_rd = 'd0; + reg adc_data_cnt = 'd0; + reg adc_dma_wr = 'd0; + reg [31:0] adc_dma_wdata = 'd0; + + // internal signals + + wire dac_clk; + wire dac_valid_0; + wire dac_enable_0; + wire dac_valid_1; + wire dac_enable_1; + wire [63:0] dac_dma_rdata; + wire adc_clk; + wire adc_valid_0; + wire adc_enable_0; + wire [15:0] adc_data_0; + wire adc_valid_1; + wire adc_enable_1; + wire [15:0] adc_data_1; wire ref_clk; wire oddr_ref_clk; + // assignments assign mgt_clk_sel = 2'd0; @@ -207,6 +232,36 @@ module system_top ( .O (ref_clk_out_p), .OB (ref_clk_out_n)); + always @(posedge dac_clk) begin + dac_dma_rd <= dac_valid_0 & dac_enable_0; + dac_ddata_1[63:48] <= dac_dma_rdata[63:48]; + dac_ddata_1[47:32] <= dac_dma_rdata[63:48]; + dac_ddata_1[31:16] <= dac_dma_rdata[31:16]; + dac_ddata_1[15: 0] <= dac_dma_rdata[31:16]; + dac_ddata_0[63:48] <= dac_dma_rdata[47:32]; + dac_ddata_0[47:32] <= dac_dma_rdata[47:32]; + dac_ddata_0[31:16] <= dac_dma_rdata[15: 0]; + dac_ddata_0[15: 0] <= dac_dma_rdata[15: 0]; + end + + always @(posedge adc_clk) begin + adc_data_cnt <= ~adc_data_cnt; + case ({adc_enable_1, adc_enable_0}) + 2'b10: begin + adc_dma_wr <= adc_data_cnt; + adc_dma_wdata <= {adc_data_1, adc_dma_wdata[31:16]}; + end + 2'b01: begin + adc_dma_wr <= adc_data_cnt; + adc_dma_wdata <= {adc_data_0, adc_dma_wdata[31:16]}; + end + default: begin + adc_dma_wr <= 1'b1; + adc_dma_wdata <= {adc_data_1, adc_data_0}; + end + endcase + end + system_wrapper i_system_wrapper ( .ddr3_addr (ddr3_addr), .ddr3_ba (ddr3_ba), @@ -235,20 +290,39 @@ module system_top ( .iic_main_scl_io (iic_scl), .iic_main_sda_io (iic_sda), .iic_rstn (iic_rstn), + .adc_clk (adc_clk), .adc_clk_in_n (adc_clk_in_n), .adc_clk_in_p (adc_clk_in_p), + .adc_data_0 (adc_data_0), + .adc_data_1 (adc_data_1), .adc_data_in_n (adc_data_in_n), .adc_data_in_p (adc_data_in_p), + .adc_dma_sync (1'b1), + .adc_dma_wdata (adc_dma_wdata), + .adc_dma_wr (adc_dma_wr), + .adc_enable_0 (adc_enable_0), + .adc_enable_1 (adc_enable_1), .adc_or_in_n (adc_or_in_n), .adc_or_in_p (adc_or_in_p), + .adc_valid_0 (adc_valid_0), + .adc_valid_1 (adc_valid_1), + .dac_clk (dac_clk), .dac_clk_in_n (dac_clk_in_n), .dac_clk_in_p (dac_clk_in_p), .dac_clk_out_n (dac_clk_out_n), .dac_clk_out_p (dac_clk_out_p), .dac_data_out_n (dac_data_out_n), .dac_data_out_p (dac_data_out_p), + .dac_ddata_0 (dac_ddata_0), + .dac_ddata_1 (dac_ddata_1), + .dac_dma_rd (dac_dma_rd), + .dac_dma_rdata (dac_dma_rdata), + .dac_enable_0 (dac_enable_0), + .dac_enable_1 (dac_enable_1), .dac_frame_out_n (dac_frame_out_n), .dac_frame_out_p (dac_frame_out_p), + .dac_valid_0 (dac_valid_0), + .dac_valid_1 (dac_valid_1), .ref_clk (ref_clk), .mdio_io (phy_mdio), .mdio_mdc (phy_mdc), diff --git a/projects/fmcomms1/common/fmcomms1_bd.tcl b/projects/fmcomms1/common/fmcomms1_bd.tcl index 9e3cc2900..dd5d21ce5 100644 --- a/projects/fmcomms1/common/fmcomms1_bd.tcl +++ b/projects/fmcomms1/common/fmcomms1_bd.tcl @@ -245,6 +245,7 @@ if {$sys_zynq == 0 } { set_property -dict [list CONFIG.C_NUM_OF_PROBES {2}] $ila_adc set_property -dict [list CONFIG.C_PROBE0_WIDTH {1}] $ila_adc set_property -dict [list CONFIG.C_PROBE1_WIDTH {64}] $ila_adc + set_property -dict [list CONFIG.C_EN_STRG_QUAL {1}] $ila_adc set_property -dict [list CONFIG.C_TRIGIN_EN {false}] $ila_adc connect_bd_net -net sys_200m_clk [get_bd_pins ila_adc/clk] diff --git a/projects/fmcomms1/kc705/system_top.v b/projects/fmcomms1/kc705/system_top.v index d07108b7e..f436aabc8 100644 --- a/projects/fmcomms1/kc705/system_top.v +++ b/projects/fmcomms1/kc705/system_top.v @@ -191,6 +191,30 @@ module system_top ( output spdif; + // internal registers + + reg [63:0] dac_ddata_0 = 'd0; + reg [63:0] dac_ddata_1 = 'd0; + reg dac_dma_rd = 'd0; + reg adc_data_cnt = 'd0; + reg adc_dma_wr = 'd0; + reg [31:0] adc_dma_wdata = 'd0; + + // internal signals + + wire dac_clk; + wire dac_valid_0; + wire dac_enable_0; + wire dac_valid_1; + wire dac_enable_1; + wire [63:0] dac_dma_rdata; + wire adc_clk; + wire adc_valid_0; + wire adc_enable_0; + wire [15:0] adc_data_0; + wire adc_valid_1; + wire adc_enable_1; + wire [15:0] adc_data_1; wire ref_clk; wire oddr_ref_clk; @@ -214,6 +238,36 @@ module system_top ( .O (ref_clk_out_p), .OB (ref_clk_out_n)); + always @(posedge dac_clk) begin + dac_dma_rd <= dac_valid_0 & dac_enable_0; + dac_ddata_1[63:48] <= dac_dma_rdata[63:48]; + dac_ddata_1[47:32] <= dac_dma_rdata[63:48]; + dac_ddata_1[31:16] <= dac_dma_rdata[31:16]; + dac_ddata_1[15: 0] <= dac_dma_rdata[31:16]; + dac_ddata_0[63:48] <= dac_dma_rdata[47:32]; + dac_ddata_0[47:32] <= dac_dma_rdata[47:32]; + dac_ddata_0[31:16] <= dac_dma_rdata[15: 0]; + dac_ddata_0[15: 0] <= dac_dma_rdata[15: 0]; + end + + always @(posedge adc_clk) begin + adc_data_cnt <= ~adc_data_cnt; + case ({adc_enable_1, adc_enable_0}) + 2'b10: begin + adc_dma_wr <= adc_data_cnt; + adc_dma_wdata <= {adc_data_1, adc_dma_wdata[31:16]}; + end + 2'b01: begin + adc_dma_wr <= adc_data_cnt; + adc_dma_wdata <= {adc_data_0, adc_dma_wdata[31:16]}; + end + default: begin + adc_dma_wr <= 1'b1; + adc_dma_wdata <= {adc_data_1, adc_data_0}; + end + endcase + end + system_wrapper i_system_wrapper ( .ddr3_1_n (ddr3_1_n), .ddr3_1_p (ddr3_1_p), @@ -236,20 +290,39 @@ module system_top ( .gpio_lcd_tri_io (gpio_lcd), .gpio_led_tri_io (gpio_led), .gpio_sw_tri_io (gpio_sw), + .adc_clk (adc_clk), .adc_clk_in_n (adc_clk_in_n), .adc_clk_in_p (adc_clk_in_p), + .adc_data_0 (adc_data_0), + .adc_data_1 (adc_data_1), .adc_data_in_n (adc_data_in_n), .adc_data_in_p (adc_data_in_p), + .adc_dma_sync (1'b1), + .adc_dma_wdata (adc_dma_wdata), + .adc_dma_wr (adc_dma_wr), + .adc_enable_0 (adc_enable_0), + .adc_enable_1 (adc_enable_1), .adc_or_in_n (adc_or_in_n), .adc_or_in_p (adc_or_in_p), + .adc_valid_0 (adc_valid_0), + .adc_valid_1 (adc_valid_1), + .dac_clk (dac_clk), .dac_clk_in_n (dac_clk_in_n), .dac_clk_in_p (dac_clk_in_p), .dac_clk_out_n (dac_clk_out_n), .dac_clk_out_p (dac_clk_out_p), .dac_data_out_n (dac_data_out_n), .dac_data_out_p (dac_data_out_p), + .dac_ddata_0 (dac_ddata_0), + .dac_ddata_1 (dac_ddata_1), + .dac_dma_rd (dac_dma_rd), + .dac_dma_rdata (dac_dma_rdata), + .dac_enable_0 (dac_enable_0), + .dac_enable_1 (dac_enable_1), .dac_frame_out_n (dac_frame_out_n), .dac_frame_out_p (dac_frame_out_p), + .dac_valid_0 (dac_valid_0), + .dac_valid_1 (dac_valid_1), .ref_clk (ref_clk), .hdmi_data (hdmi_data), .hdmi_data_e (hdmi_data_e), diff --git a/projects/fmcomms1/vc707/system_top.v b/projects/fmcomms1/vc707/system_top.v index 8c47d30a9..579006aef 100644 --- a/projects/fmcomms1/vc707/system_top.v +++ b/projects/fmcomms1/vc707/system_top.v @@ -182,6 +182,30 @@ module system_top ( output spdif; + // internal registers + + reg [63:0] dac_ddata_0 = 'd0; + reg [63:0] dac_ddata_1 = 'd0; + reg dac_dma_rd = 'd0; + reg adc_data_cnt = 'd0; + reg adc_dma_wr = 'd0; + reg [31:0] adc_dma_wdata = 'd0; + + // internal signals + + wire dac_clk; + wire dac_valid_0; + wire dac_enable_0; + wire dac_valid_1; + wire dac_enable_1; + wire [63:0] dac_dma_rdata; + wire adc_clk; + wire adc_valid_0; + wire adc_enable_0; + wire [15:0] adc_data_0; + wire adc_valid_1; + wire adc_enable_1; + wire [15:0] adc_data_1; wire ref_clk; wire oddr_ref_clk; @@ -205,6 +229,36 @@ module system_top ( .O (ref_clk_out_p), .OB (ref_clk_out_n)); + always @(posedge dac_clk) begin + dac_dma_rd <= dac_valid_0 & dac_enable_0; + dac_ddata_1[63:48] <= dac_dma_rdata[63:48]; + dac_ddata_1[47:32] <= dac_dma_rdata[63:48]; + dac_ddata_1[31:16] <= dac_dma_rdata[31:16]; + dac_ddata_1[15: 0] <= dac_dma_rdata[31:16]; + dac_ddata_0[63:48] <= dac_dma_rdata[47:32]; + dac_ddata_0[47:32] <= dac_dma_rdata[47:32]; + dac_ddata_0[31:16] <= dac_dma_rdata[15: 0]; + dac_ddata_0[15: 0] <= dac_dma_rdata[15: 0]; + end + + always @(posedge adc_clk) begin + adc_data_cnt <= ~adc_data_cnt; + case ({adc_enable_1, adc_enable_0}) + 2'b10: begin + adc_dma_wr <= adc_data_cnt; + adc_dma_wdata <= {adc_data_1, adc_dma_wdata[31:16]}; + end + 2'b01: begin + adc_dma_wr <= adc_data_cnt; + adc_dma_wdata <= {adc_data_0, adc_dma_wdata[31:16]}; + end + default: begin + adc_dma_wr <= 1'b1; + adc_dma_wdata <= {adc_data_1, adc_data_0}; + end + endcase + end + system_wrapper i_system_wrapper ( .ddr3_addr (ddr3_addr), .ddr3_ba (ddr3_ba), @@ -230,20 +284,39 @@ module system_top ( .hdmi_hsync (hdmi_hsync), .hdmi_out_clk (hdmi_out_clk), .hdmi_vsync (hdmi_vsync), + .adc_clk (adc_clk), .adc_clk_in_n (adc_clk_in_n), .adc_clk_in_p (adc_clk_in_p), + .adc_data_0 (adc_data_0), + .adc_data_1 (adc_data_1), .adc_data_in_n (adc_data_in_n), .adc_data_in_p (adc_data_in_p), + .adc_dma_sync (1'b1), + .adc_dma_wdata (adc_dma_wdata), + .adc_dma_wr (adc_dma_wr), + .adc_enable_0 (adc_enable_0), + .adc_enable_1 (adc_enable_1), .adc_or_in_n (adc_or_in_n), .adc_or_in_p (adc_or_in_p), + .adc_valid_0 (adc_valid_0), + .adc_valid_1 (adc_valid_1), + .dac_clk (dac_clk), .dac_clk_in_n (dac_clk_in_n), .dac_clk_in_p (dac_clk_in_p), .dac_clk_out_n (dac_clk_out_n), .dac_clk_out_p (dac_clk_out_p), .dac_data_out_n (dac_data_out_n), .dac_data_out_p (dac_data_out_p), + .dac_ddata_0 (dac_ddata_0), + .dac_ddata_1 (dac_ddata_1), + .dac_dma_rd (dac_dma_rd), + .dac_dma_rdata (dac_dma_rdata), + .dac_enable_0 (dac_enable_0), + .dac_enable_1 (dac_enable_1), .dac_frame_out_n (dac_frame_out_n), .dac_frame_out_p (dac_frame_out_p), + .dac_valid_0 (dac_valid_0), + .dac_valid_1 (dac_valid_1), .ref_clk (ref_clk), .iic_main_scl_io (iic_scl), .iic_main_sda_io (iic_sda), diff --git a/projects/fmcomms1/zc702/system_top.v b/projects/fmcomms1/zc702/system_top.v index 2527b89db..b7c8ca5e7 100644 --- a/projects/fmcomms1/zc702/system_top.v +++ b/projects/fmcomms1/zc702/system_top.v @@ -151,11 +151,33 @@ module system_top ( inout iic_scl; inout iic_sda; + // internal registers + + reg [63:0] dac_ddata_0 = 'd0; + reg [63:0] dac_ddata_1 = 'd0; + reg dac_dma_rd = 'd0; + reg adc_data_cnt = 'd0; + reg adc_dma_wr = 'd0; + reg [31:0] adc_dma_wdata = 'd0; + // internal signals wire [31:0] gpio_i; wire [31:0] gpio_o; wire [31:0] gpio_t; + wire dac_clk; + wire dac_valid_0; + wire dac_enable_0; + wire dac_valid_1; + wire dac_enable_1; + wire [63:0] dac_dma_rdata; + wire adc_clk; + wire adc_valid_0; + wire adc_enable_0; + wire [15:0] adc_data_0; + wire adc_valid_1; + wire adc_enable_1; + wire [15:0] adc_data_1; wire ref_clk; wire oddr_ref_clk; @@ -190,6 +212,36 @@ module system_top ( end endgenerate + always @(posedge dac_clk) begin + dac_dma_rd <= dac_valid_0 & dac_enable_0; + dac_ddata_1[63:48] <= dac_dma_rdata[63:48]; + dac_ddata_1[47:32] <= dac_dma_rdata[63:48]; + dac_ddata_1[31:16] <= dac_dma_rdata[31:16]; + dac_ddata_1[15: 0] <= dac_dma_rdata[31:16]; + dac_ddata_0[63:48] <= dac_dma_rdata[47:32]; + dac_ddata_0[47:32] <= dac_dma_rdata[47:32]; + dac_ddata_0[31:16] <= dac_dma_rdata[15: 0]; + dac_ddata_0[15: 0] <= dac_dma_rdata[15: 0]; + end + + always @(posedge adc_clk) begin + adc_data_cnt <= ~adc_data_cnt ; + case ({adc_enable_1, adc_enable_0}) + 2'b10: begin + adc_dma_wr <= adc_data_cnt; + adc_dma_wdata <= {adc_data_1, adc_dma_wdata[31:16]}; + end + 2'b01: begin + adc_dma_wr <= adc_data_cnt; + adc_dma_wdata <= {adc_data_0, adc_dma_wdata[31:16]}; + end + default: begin + adc_dma_wr <= 1'b1; + adc_dma_wdata <= {adc_data_1, adc_data_0}; + end + endcase + end + system_wrapper i_system_wrapper ( .DDR_addr (DDR_addr), .DDR_ba (DDR_ba), @@ -215,20 +267,39 @@ module system_top ( .GPIO_I (gpio_i), .GPIO_O (gpio_o), .GPIO_T (gpio_t), + .adc_clk (adc_clk), .adc_clk_in_n (adc_clk_in_n), .adc_clk_in_p (adc_clk_in_p), + .adc_data_0 (adc_data_0), + .adc_data_1 (adc_data_1), .adc_data_in_n (adc_data_in_n), .adc_data_in_p (adc_data_in_p), + .adc_dma_sync (1'b1), + .adc_dma_wdata (adc_dma_wdata), + .adc_dma_wr (adc_dma_wr), + .adc_enable_0 (adc_enable_0), + .adc_enable_1 (adc_enable_1), .adc_or_in_n (adc_or_in_n), .adc_or_in_p (adc_or_in_p), + .adc_valid_0 (adc_valid_0), + .adc_valid_1 (adc_valid_1), + .dac_clk (dac_clk), .dac_clk_in_n (dac_clk_in_n), .dac_clk_in_p (dac_clk_in_p), .dac_clk_out_n (dac_clk_out_n), .dac_clk_out_p (dac_clk_out_p), .dac_data_out_n (dac_data_out_n), .dac_data_out_p (dac_data_out_p), + .dac_ddata_0 (dac_ddata_0), + .dac_ddata_1 (dac_ddata_1), + .dac_dma_rd (dac_dma_rd), + .dac_dma_rdata (dac_dma_rdata), + .dac_enable_0 (dac_enable_0), + .dac_enable_1 (dac_enable_1), .dac_frame_out_n (dac_frame_out_n), .dac_frame_out_p (dac_frame_out_p), + .dac_valid_0 (dac_valid_0), + .dac_valid_1 (dac_valid_1), .hdmi_data (hdmi_data), .hdmi_data_e (hdmi_data_e), .hdmi_hsync (hdmi_hsync), diff --git a/projects/fmcomms1/zc706/system_top.v b/projects/fmcomms1/zc706/system_top.v index f7bc70495..a24bf9e71 100644 --- a/projects/fmcomms1/zc706/system_top.v +++ b/projects/fmcomms1/zc706/system_top.v @@ -156,9 +156,9 @@ module system_top ( reg [63:0] dac_ddata_0 = 'd0; reg [63:0] dac_ddata_1 = 'd0; reg dac_dma_rd = 'd0; - reg [ 1:0] adc_data_cnt = 'd0; + reg adc_data_cnt = 'd0; reg adc_dma_wr = 'd0; - reg [63:0] adc_dma_wdata = 'd0; + reg [31:0] adc_dma_wdata = 'd0; // internal signals @@ -224,20 +224,20 @@ module system_top ( dac_ddata_0[15: 0] <= dac_dma_rdata[15: 0]; end - always @(posedge adc_clk) begin - adc_data_cnt <= adc_data_cnt + 1'b1; + always @(posedge adc_clk) begin + adc_data_cnt <= ~adc_data_cnt ; case ({adc_enable_1, adc_enable_0}) 2'b10: begin - adc_dma_wr <= adc_data_cnt[0] & adc_data_cnt[1]; - adc_dma_wdata <= {adc_data_1, adc_dma_wdata[63:16]}; + adc_dma_wr <= adc_data_cnt; + adc_dma_wdata <= {adc_data_1, adc_dma_wdata[31:16]}; end 2'b01: begin - adc_dma_wr <= adc_data_cnt[0] & adc_data_cnt[1]; - adc_dma_wdata <= {adc_data_0, adc_dma_wdata[63:16]}; + adc_dma_wr <= adc_data_cnt; + adc_dma_wdata <= {adc_data_0, adc_dma_wdata[31:16]}; end default: begin - adc_dma_wr <= adc_data_cnt[0]; - adc_dma_wdata <= {adc_data_1, adc_data_0, adc_dma_wdata[63:32]}; + adc_dma_wr <= 1'b1; + adc_dma_wdata <= {adc_data_1, adc_data_0}; end endcase end diff --git a/projects/fmcomms1/zed/system_top.v b/projects/fmcomms1/zed/system_top.v index fb73f892d..05aac0da6 100644 --- a/projects/fmcomms1/zed/system_top.v +++ b/projects/fmcomms1/zed/system_top.v @@ -171,11 +171,33 @@ module system_top ( input otg_vbusoc; + // internal registers + + reg [63:0] dac_ddata_0 = 'd0; + reg [63:0] dac_ddata_1 = 'd0; + reg dac_dma_rd = 'd0; + reg adc_data_cnt = 'd0; + reg adc_dma_wr = 'd0; + reg [31:0] adc_dma_wdata = 'd0; + // internal signals wire [31:0] gpio_i; wire [31:0] gpio_o; wire [31:0] gpio_t; + wire dac_clk; + wire dac_valid_0; + wire dac_enable_0; + wire dac_valid_1; + wire dac_enable_1; + wire [63:0] dac_dma_rdata; + wire adc_clk; + wire adc_valid_0; + wire adc_enable_0; + wire [15:0] adc_data_0; + wire adc_valid_1; + wire adc_enable_1; + wire [15:0] adc_data_1; wire ref_clk; wire oddr_ref_clk; @@ -222,6 +244,36 @@ module system_top ( IOBUF i_iic_mux_sda_0 (.I(iic_mux_sda_o_s[0]), .O(iic_mux_sda_i_s[0]), .T(iic_mux_sda_t_s), .IO(iic_mux_sda[0])); IOBUF i_iic_mux_sda_1 (.I(iic_mux_sda_o_s[1]), .O(iic_mux_sda_i_s[1]), .T(iic_mux_sda_t_s), .IO(iic_mux_sda[1])); + always @(posedge dac_clk) begin + dac_dma_rd <= dac_valid_0 & dac_enable_0; + dac_ddata_1[63:48] <= dac_dma_rdata[63:48]; + dac_ddata_1[47:32] <= dac_dma_rdata[63:48]; + dac_ddata_1[31:16] <= dac_dma_rdata[31:16]; + dac_ddata_1[15: 0] <= dac_dma_rdata[31:16]; + dac_ddata_0[63:48] <= dac_dma_rdata[47:32]; + dac_ddata_0[47:32] <= dac_dma_rdata[47:32]; + dac_ddata_0[31:16] <= dac_dma_rdata[15: 0]; + dac_ddata_0[15: 0] <= dac_dma_rdata[15: 0]; + end + + always @(posedge adc_clk) begin + adc_data_cnt <= ~adc_data_cnt ; + case ({adc_enable_1, adc_enable_0}) + 2'b10: begin + adc_dma_wr <= adc_data_cnt; + adc_dma_wdata <= {adc_data_1, adc_dma_wdata[31:16]}; + end + 2'b01: begin + adc_dma_wr <= adc_data_cnt; + adc_dma_wdata <= {adc_data_0, adc_dma_wdata[31:16]}; + end + default: begin + adc_dma_wr <= 1'b1; + adc_dma_wdata <= {adc_data_1, adc_data_0}; + end + endcase + end + system_wrapper i_system_wrapper ( .DDR_addr (DDR_addr), .DDR_ba (DDR_ba), @@ -247,20 +299,39 @@ module system_top ( .GPIO_I (gpio_i), .GPIO_O (gpio_o), .GPIO_T (gpio_t), + .adc_clk (adc_clk), .adc_clk_in_n (adc_clk_in_n), .adc_clk_in_p (adc_clk_in_p), + .adc_data_0 (adc_data_0), + .adc_data_1 (adc_data_1), .adc_data_in_n (adc_data_in_n), .adc_data_in_p (adc_data_in_p), + .adc_dma_sync (1'b1), + .adc_dma_wdata (adc_dma_wdata), + .adc_dma_wr (adc_dma_wr), + .adc_enable_0 (adc_enable_0), + .adc_enable_1 (adc_enable_1), .adc_or_in_n (adc_or_in_n), .adc_or_in_p (adc_or_in_p), + .adc_valid_0 (adc_valid_0), + .adc_valid_1 (adc_valid_1), + .dac_clk (dac_clk), .dac_clk_in_n (dac_clk_in_n), .dac_clk_in_p (dac_clk_in_p), .dac_clk_out_n (dac_clk_out_n), .dac_clk_out_p (dac_clk_out_p), .dac_data_out_n (dac_data_out_n), .dac_data_out_p (dac_data_out_p), + .dac_ddata_0 (dac_ddata_0), + .dac_ddata_1 (dac_ddata_1), + .dac_dma_rd (dac_dma_rd), + .dac_dma_rdata (dac_dma_rdata), + .dac_enable_0 (dac_enable_0), + .dac_enable_1 (dac_enable_1), .dac_frame_out_n (dac_frame_out_n), .dac_frame_out_p (dac_frame_out_p), + .dac_valid_0 (dac_valid_0), + .dac_valid_1 (dac_valid_1), .hdmi_data (hdmi_data), .hdmi_data_e (hdmi_data_e), .hdmi_hsync (hdmi_hsync), From 889a6565ea5b9aea62fb2dfaeb495b3343d2c63a Mon Sep 17 00:00:00 2001 From: Istvan Csomortani Date: Mon, 29 Sep 2014 12:51:46 +0300 Subject: [PATCH 07/42] ad9467 ZED: Cosmetic changes on bd script. --- projects/ad9467_fmc/common/ad9467_bd.tcl | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/projects/ad9467_fmc/common/ad9467_bd.tcl b/projects/ad9467_fmc/common/ad9467_bd.tcl index 44f9189c9..508b2acd5 100644 --- a/projects/ad9467_fmc/common/ad9467_bd.tcl +++ b/projects/ad9467_fmc/common/ad9467_bd.tcl @@ -91,13 +91,13 @@ if {$sys_zynq == 1} { # connections (spi) if {$sys_zynq == 0} { - connect_bd_net -net spi_csn_i [get_bd_ports spi_csn_i] [get_bd_pins axi_ad9467_spi/ss_i] - connect_bd_net -net spi_csn_o [get_bd_ports spi_csn_o] [get_bd_pins axi_ad9467_spi/ss_o] - connect_bd_net -net spi_sclk_i [get_bd_ports spi_clk_i] [get_bd_pins axi_ad9467_spi/sck_i] - connect_bd_net -net spi_sclk_o [get_bd_ports spi_clk_o] [get_bd_pins axi_ad9467_spi/sck_o] - connect_bd_net -net spi_mosi_i [get_bd_ports spi_sdo_i] [get_bd_pins axi_ad9467_spi/io0_i] - connect_bd_net -net spi_mosi_o [get_bd_ports spi_sdo_o] [get_bd_pins axi_ad9467_spi/io0_o] - connect_bd_net -net spi_miso_i [get_bd_ports spi_sdi_i] [get_bd_pins axi_ad9467_spi/io1_i] + connect_bd_net -net spi_csn_i [get_bd_ports spi_csn_i] [get_bd_pins axi_ad9467_spi/ss_i] + connect_bd_net -net spi_csn_o [get_bd_ports spi_csn_o] [get_bd_pins axi_ad9467_spi/ss_o] + connect_bd_net -net spi_sclk_i [get_bd_ports spi_clk_i] [get_bd_pins axi_ad9467_spi/sck_i] + connect_bd_net -net spi_sclk_o [get_bd_ports spi_clk_o] [get_bd_pins axi_ad9467_spi/sck_o] + connect_bd_net -net spi_mosi_i [get_bd_ports spi_sdo_i] [get_bd_pins axi_ad9467_spi/io0_i] + connect_bd_net -net spi_mosi_o [get_bd_ports spi_sdo_o] [get_bd_pins axi_ad9467_spi/io0_o] + connect_bd_net -net spi_miso_i [get_bd_ports spi_sdi_i] [get_bd_pins axi_ad9467_spi/io1_i] delete_bd_objs [get_bd_nets sys_concat_intc_din_2] delete_bd_objs [get_bd_ports unc_int2] @@ -132,8 +132,8 @@ connect_bd_net -net sys_200m_clk [get_bd_pins axi_ad9467/delay_clk] connect_bd_net -net axi_ad9467_dma_dwr [get_bd_pins axi_ad9467/adc_dwr] [get_bd_pins axi_ad9467_dma/fifo_wr_en] connect_bd_net -net axi_ad9467_dma_ddata [get_bd_pins axi_ad9467/adc_ddata] [get_bd_pins axi_ad9467_dma/fifo_wr_din] connect_bd_net -net axi_ad9467_dma_dovf [get_bd_pins axi_ad9467/adc_doverflow] [get_bd_pins axi_ad9467_dma/fifo_wr_overflow] +connect_bd_net -net axi_ad9467_dma_irq [get_bd_pins axi_ad9467_dma/irq] [get_bd_pins sys_concat_intc/In2] -connect_bd_net -net axi_ad9467_dma_irq [get_bd_pins axi_ad9467_dma/irq] [get_bd_pins sys_concat_intc/In2] # interconnect (cpu) connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M07_ACLK] [get_bd_pins $sys_100m_clk_source] connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M08_ACLK] [get_bd_pins $sys_100m_clk_source] From 74e6e3df0fb367e735f820739d391847e0ec3862 Mon Sep 17 00:00:00 2001 From: Istvan Csomortani Date: Mon, 29 Sep 2014 12:56:09 +0300 Subject: [PATCH 08/42] ad9467 ZED: Fix over range signal path, and the dma interface. --- projects/ad9467_fmc/common/ad9467_bd.tcl | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/projects/ad9467_fmc/common/ad9467_bd.tcl b/projects/ad9467_fmc/common/ad9467_bd.tcl index 508b2acd5..2953d038e 100644 --- a/projects/ad9467_fmc/common/ad9467_bd.tcl +++ b/projects/ad9467_fmc/common/ad9467_bd.tcl @@ -121,17 +121,18 @@ connect_bd_net -net axi_ad9467_adc_clk_in_n [get_bd_ports adc_clk_in_p] connect_bd_net -net axi_ad9467_adc_clk_in_p [get_bd_ports adc_clk_in_n] [get_bd_pins axi_ad9467/adc_clk_in_n] connect_bd_net -net axi_ad9467_adc_data_in_n [get_bd_ports adc_data_in_n] [get_bd_pins axi_ad9467/adc_data_in_n] connect_bd_net -net axi_ad9467_adc_data_in_p [get_bd_ports adc_data_in_p] [get_bd_pins axi_ad9467/adc_data_in_p] -connect_bd_net -net axi_ad9467_adc_data_or_n [get_bd_ports adc_data_or_p] [get_bd_pins axi_ad9467/adc_data_or_p] -connect_bd_net -net axi_ad9467_adc_data_or_p [get_bd_ports adc_data_or_n] [get_bd_pins axi_ad9467/adc_data_or_n] +connect_bd_net -net axi_ad9467_adc_data_or_n [get_bd_ports adc_data_or_p] [get_bd_pins axi_ad9467/adc_or_in_p] +connect_bd_net -net axi_ad9467_adc_data_or_p [get_bd_ports adc_data_or_n] [get_bd_pins axi_ad9467/adc_or_in_n] set adc_250m_clk_source [get_bd_pins axi_ad9467/adc_clk] connect_bd_net -net adc_250m_clk [get_bd_pins axi_ad9467_dma/fifo_wr_clk] $adc_250m_clk_source connect_bd_net -net sys_200m_clk [get_bd_pins axi_ad9467/delay_clk] -connect_bd_net -net axi_ad9467_dma_dwr [get_bd_pins axi_ad9467/adc_dwr] [get_bd_pins axi_ad9467_dma/fifo_wr_en] -connect_bd_net -net axi_ad9467_dma_ddata [get_bd_pins axi_ad9467/adc_ddata] [get_bd_pins axi_ad9467_dma/fifo_wr_din] -connect_bd_net -net axi_ad9467_dma_dovf [get_bd_pins axi_ad9467/adc_doverflow] [get_bd_pins axi_ad9467_dma/fifo_wr_overflow] +connect_bd_net -net axi_ad9467_dma_dwr [get_bd_pins axi_ad9467/adc_valid] [get_bd_pins axi_ad9467_dma/fifo_wr_en] +connect_bd_net -net axi_ad9467_dma_ddata [get_bd_pins axi_ad9467/adc_data] [get_bd_pins axi_ad9467_dma/fifo_wr_din] +connect_bd_net -net axi_ad9467_dma_dovf [get_bd_pins axi_ad9467/adc_dovf] [get_bd_pins axi_ad9467_dma/fifo_wr_overflow] + connect_bd_net -net axi_ad9467_dma_irq [get_bd_pins axi_ad9467_dma/irq] [get_bd_pins sys_concat_intc/In2] # interconnect (cpu) From 40cbabf57312ab6fddb9173afc427fdacb646d20 Mon Sep 17 00:00:00 2001 From: Lars-Peter Clausen Date: Mon, 29 Sep 2014 15:22:19 +0200 Subject: [PATCH 09/42] axi_i2s/axi_spdif: Remove manual creation of Streaming AXI bus It looks like Vivado is now able to infer these buses from the sources. Signed-off-by: Lars-Peter Clausen --- library/axi_i2s_adi/axi_i2s_adi_ip.tcl | 16 ---------------- library/axi_spdif_tx/axi_spdif_tx_ip.tcl | 8 -------- 2 files changed, 24 deletions(-) diff --git a/library/axi_i2s_adi/axi_i2s_adi_ip.tcl b/library/axi_i2s_adi/axi_i2s_adi_ip.tcl index 3c0468342..b82b7dbd4 100644 --- a/library/axi_i2s_adi/axi_i2s_adi_ip.tcl +++ b/library/axi_i2s_adi/axi_i2s_adi_ip.tcl @@ -19,22 +19,6 @@ adi_ip_files axi_i2s_adi [list \ adi_ip_properties_lite axi_i2s_adi -adi_add_bus "M_AXIS" "axis" "master" \ - [list {"M_AXIS_ACLK" "ACLK"} \ - {"M_AXIS_TREADY" "TREADY"} \ - {"M_AXIS_TVALID" "VALID"} \ - {"M_AXIS_TDATA" "TDATA"} \ - {"M_AXIS_TLAST" "TLAST"} \ - {"M_AXIS_TKEEP" "TKEEP"} ] - -adi_add_bus "S_AXIS" "axis" "slave" \ - [list {"S_AXIS_ACLK" "ACLK"} \ - {"S_AXIS_ARESETN" "ARESETN"} \ - {"S_AXIS_TREADY" "TREADY"} \ - {"S_AXIS_TVALID" "VALID"} \ - {"S_AXIS_TDATA" "TDATA"} \ - {"S_AXIS_TLAST" "TLAST"} ] - adi_add_bus "DMA_ACK_RX" "axis" "slave" \ [list {"DMA_REQ_RX_DAVALID" "TVALID"} \ {"DMA_REQ_RX_DAREADY" "TREADY"} \ diff --git a/library/axi_spdif_tx/axi_spdif_tx_ip.tcl b/library/axi_spdif_tx/axi_spdif_tx_ip.tcl index c28d300c4..6a722bbc5 100644 --- a/library/axi_spdif_tx/axi_spdif_tx_ip.tcl +++ b/library/axi_spdif_tx/axi_spdif_tx_ip.tcl @@ -21,14 +21,6 @@ ipx::add_file $ip_constr_files $proj_filegroup set_property type {{xdc}} [ipx::get_file $ip_constr_files $proj_filegroup] set_property library_name {} [ipx::get_file $ip_constr_files $proj_filegroup] -adi_add_bus "S_AXIS" "axis" "slave" \ - [list {"S_AXIS_ACLK" "ACLK"} \ - {"S_AXIS_ARESETN" "ARESETN"} \ - {"S_AXIS_TREADY" "TREADY"} \ - {"S_AXIS_TVALID" "VALID"} \ - {"S_AXIS_TDATA" "TDATA"} \ - {"S_AXIS_TLAST" "TLAST"} ] - adi_add_bus "DMA_ACK" "axis" "slave" \ [list {"DMA_REQ_DAVALID" "TVALID"} \ {"DMA_REQ_DAREADY" "TREADY"} \ From 7682400a28d8fbf7c9bfe399608200e78904e99a Mon Sep 17 00:00:00 2001 From: Lars-Peter Clausen Date: Mon, 29 Sep 2014 15:23:18 +0200 Subject: [PATCH 10/42] scripts/adi_ip: Add helper function to create bus clock and reset interface Add a helper function that can be used to register a clock and a reset interface for the clock and reset signals of a bus. Signed-off-by: Lars-Peter Clausen --- library/scripts/adi_ip.tcl | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/library/scripts/adi_ip.tcl b/library/scripts/adi_ip.tcl index da3c453ca..91fbbd1e5 100644 --- a/library/scripts/adi_ip.tcl +++ b/library/scripts/adi_ip.tcl @@ -131,3 +131,33 @@ proc adi_add_bus {bus_name bus_type mode port_maps} { adi_add_port_map $bus {*}$port_map } } + +proc adi_add_bus_clock {clock_signal_name bus_inf_name {reset_signal_name ""}} { + set bus_inf_name_clean [string map {":" "_"} $bus_inf_name] + set clock_inf_name [format "%s%s" $bus_inf_name_clean "_signal_clock"] + set clock_inf [ipx::add_bus_interface $clock_inf_name [ipx::current_core]] + set_property abstraction_type_vlnv "xilinx.com:signal:clock_rtl:1.0" $clock_inf + set_property bus_type_vlnv "xilinx.com:signal:clock:1.0" $clock_inf + set_property display_name $clock_inf_name $clock_inf + set clock_map [ipx::add_port_map "CLK" $clock_inf] + set_property physical_name $clock_signal_name $clock_map + + set assoc_busif [ipx::add_bus_parameter "ASSOCIATED_BUSIF" $clock_inf] + set_property value $bus_inf_name $assoc_busif + + if { $reset_signal_name != "" } { + set assoc_reset [ipx::add_bus_parameter "ASSOCIATED_RESET" $clock_inf] + set_property value $reset_signal_name $assoc_reset + + set reset_inf_name [format "%s%s" $bus_inf_name_clean "_signal_reset"] + set reset_inf [ipx::add_bus_interface $reset_inf_name [ipx::current_core]] + set_property abstraction_type_vlnv "xilinx.com:signal:reset_rtl:1.0" $reset_inf + set_property bus_type_vlnv "xilinx.com:signal:reset:1.0" $reset_inf + set_property display_name $reset_inf_name $reset_inf + set reset_map [ipx::add_port_map "RST" $reset_inf] + set_property physical_name $reset_signal_name $reset_map + + set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_inf] + set_property value "ACTIVE_LOW" $reset_polarity + } +} From 6a08f269059498aa6c470dbae99e50e60c1ee324 Mon Sep 17 00:00:00 2001 From: Lars-Peter Clausen Date: Mon, 29 Sep 2014 15:24:14 +0200 Subject: [PATCH 11/42] axi_i2s/axi_spdif: Create clock and reset interface for DMA bus This avoids some critical warnings from Vivado that the DMA bus does not has any associated clocks. Signed-off-by: Lars-Peter Clausen --- library/axi_i2s_adi/axi_i2s_adi_ip.tcl | 4 ++++ library/axi_spdif_tx/axi_spdif_tx_ip.tcl | 3 +++ 2 files changed, 7 insertions(+) diff --git a/library/axi_i2s_adi/axi_i2s_adi_ip.tcl b/library/axi_i2s_adi/axi_i2s_adi_ip.tcl index b82b7dbd4..8d994fd72 100644 --- a/library/axi_i2s_adi/axi_i2s_adi_ip.tcl +++ b/library/axi_i2s_adi/axi_i2s_adi_ip.tcl @@ -28,6 +28,8 @@ adi_add_bus "DMA_REQ_RX" "axis" "master" \ {"DMA_REQ_RX_DRREADY" "TREADY"} \ {"DMA_REQ_RX_DRTYPE" "TUSER"} \ {"DMA_REQ_RX_DRLAST" "TLAST"} ] +# Clock and reset are for both DMA_REQ and DMA_ACK +adi_add_bus_clock "DMA_REQ_RX_ACLK" "DMA_REQ_RX:DMA_ACK_RX" "DMA_REQ_RX_RSTN" adi_add_bus "DMA_ACK_TX" "axis" "slave" \ [list {"DMA_REQ_TX_DAVALID" "TVALID"} \ @@ -38,6 +40,8 @@ adi_add_bus "DMA_REQ_TX" "axis" "master" \ {"DMA_REQ_TX_DRREADY" "TREADY"} \ {"DMA_REQ_TX_DRTYPE" "TUSER"} \ {"DMA_REQ_TX_DRLAST" "TLAST"} ] +# Clock and reset are for both DMA_REQ and DMA_ACK +adi_add_bus_clock "DMA_REQ_TX_ACLK" "DMA_REQ_TX:DMA_ACK_TX" "DMA_REQ_TX_RSTN" adi_set_bus_dependency "S_AXIS" "S_AXIS" \ "(spirit:decode(id('MODELPARAM_VALUE.C_DMA_TYPE')) = 0)" diff --git a/library/axi_spdif_tx/axi_spdif_tx_ip.tcl b/library/axi_spdif_tx/axi_spdif_tx_ip.tcl index 6a722bbc5..0fea3aea2 100644 --- a/library/axi_spdif_tx/axi_spdif_tx_ip.tcl +++ b/library/axi_spdif_tx/axi_spdif_tx_ip.tcl @@ -31,6 +31,9 @@ adi_add_bus "DMA_REQ" "axis" "master" \ {"DMA_REQ_DRTYPE" "TUSER"} \ {"DMA_REQ_DRLAST" "TLAST"} ] +# Clock and reset are for both DMA_REQ and DMA_ACK +adi_add_bus_clock "DMA_REQ_ACLK" "DMA_REQ:DMA_ACK" "DMA_REQ_RSTN" + adi_set_bus_dependency "S_AXIS" "S_AXIS" \ "(spirit:decode(id('MODELPARAM_VALUE.C_DMA_TYPE')) = 0)" From f7ad7e7ab218cf3cf43fe11e0acc949687a2dd57 Mon Sep 17 00:00:00 2001 From: Lars-Peter Clausen Date: Mon, 29 Sep 2014 19:08:33 +0200 Subject: [PATCH 12/42] common: Disable TTC0 MMIO routing for PS7 We do not use the ttc0 to MMIO routing, but it is enabled by default, so explicitly disable it. Signed-off-by: Lars-Peter Clausen --- projects/common/mitx045/mitx045_system_bd.tcl | 1 + projects/common/zc702/zc702_system_bd.tcl | 1 + projects/common/zc706/zc706_system_bd.tcl | 1 + projects/common/zed/zed_system_bd.tcl | 1 + 4 files changed, 4 insertions(+) diff --git a/projects/common/mitx045/mitx045_system_bd.tcl b/projects/common/mitx045/mitx045_system_bd.tcl index fe39a5403..5248ccd2c 100755 --- a/projects/common/mitx045/mitx045_system_bd.tcl +++ b/projects/common/mitx045/mitx045_system_bd.tcl @@ -33,6 +33,7 @@ set i2s_sdata_in [create_bd_port -dir I i2s_sdata_in] set sys_ps7 [create_bd_cell -type ip -vlnv xilinx.com:ip:processing_system7:5.3 sys_ps7] set_property -dict [list CONFIG.PCW_IMPORT_BOARD_PRESET $ad_hdl_dir/projects/common/mitx045/mitx045.xml ] [get_bd_cells sys_ps7] +set_property -dict [list CONFIG.PCW_TTC0_PERIPHERAL_ENABLE {0}] $sys_ps7 set_property -dict [list CONFIG.PCW_GPIO_MIO_GPIO_ENABLE {1} ] $sys_ps7 set_property -dict [list CONFIG.PCW_EN_CLK1_PORT {1}] $sys_ps7 set_property -dict [list CONFIG.PCW_EN_RST1_PORT {1}] $sys_ps7 diff --git a/projects/common/zc702/zc702_system_bd.tcl b/projects/common/zc702/zc702_system_bd.tcl index b2ec711d3..316d4a483 100644 --- a/projects/common/zc702/zc702_system_bd.tcl +++ b/projects/common/zc702/zc702_system_bd.tcl @@ -26,6 +26,7 @@ set spdif [create_bd_port -dir O spdif] set sys_ps7 [create_bd_cell -type ip -vlnv xilinx.com:ip:processing_system7:5.3 sys_ps7] set_property -dict [list CONFIG.PCW_IMPORT_BOARD_PRESET {ZC702}] $sys_ps7 +set_property -dict [list CONFIG.PCW_TTC0_PERIPHERAL_ENABLE {0}] $sys_ps7 set_property -dict [list CONFIG.PCW_EN_CLK1_PORT {1}] $sys_ps7 set_property -dict [list CONFIG.PCW_EN_RST1_PORT {1}] $sys_ps7 set_property -dict [list CONFIG.PCW_FPGA0_PERIPHERAL_FREQMHZ {100.0}] $sys_ps7 diff --git a/projects/common/zc706/zc706_system_bd.tcl b/projects/common/zc706/zc706_system_bd.tcl index 319e87998..63d8f7706 100644 --- a/projects/common/zc706/zc706_system_bd.tcl +++ b/projects/common/zc706/zc706_system_bd.tcl @@ -26,6 +26,7 @@ set spdif [create_bd_port -dir O spdif] set sys_ps7 [create_bd_cell -type ip -vlnv xilinx.com:ip:processing_system7:5.3 sys_ps7] set_property -dict [list CONFIG.PCW_IMPORT_BOARD_PRESET {ZC706}] $sys_ps7 +set_property -dict [list CONFIG.PCW_TTC0_PERIPHERAL_ENABLE {0}] $sys_ps7 set_property -dict [list CONFIG.PCW_EN_CLK1_PORT {1}] $sys_ps7 set_property -dict [list CONFIG.PCW_EN_RST1_PORT {1}] $sys_ps7 set_property -dict [list CONFIG.PCW_FPGA0_PERIPHERAL_FREQMHZ {100.0}] $sys_ps7 diff --git a/projects/common/zed/zed_system_bd.tcl b/projects/common/zed/zed_system_bd.tcl index 21932d6be..433944696 100644 --- a/projects/common/zed/zed_system_bd.tcl +++ b/projects/common/zed/zed_system_bd.tcl @@ -45,6 +45,7 @@ set spdif [create_bd_port -dir O spdif] set sys_ps7 [create_bd_cell -type ip -vlnv xilinx.com:ip:processing_system7:5.3 sys_ps7] set_property -dict [list CONFIG.PCW_IMPORT_BOARD_PRESET {ZedBoard}] $sys_ps7 +set_property -dict [list CONFIG.PCW_TTC0_PERIPHERAL_ENABLE {0}] $sys_ps7 set_property -dict [list CONFIG.PCW_EN_CLK1_PORT {1}] $sys_ps7 set_property -dict [list CONFIG.PCW_EN_RST1_PORT {1}] $sys_ps7 set_property -dict [list CONFIG.PCW_FPGA0_PERIPHERAL_FREQMHZ {100.0}] $sys_ps7 From 50c434044e498ec910ca2297021ab2b049fe9d99 Mon Sep 17 00:00:00 2001 From: Lars-Peter Clausen Date: Mon, 29 Sep 2014 19:53:10 +0200 Subject: [PATCH 13/42] util_dac_unpack: Drive unused ports to 0 Silences a few warnings about undriven ports from the tools. Signed-off-by: Lars-Peter Clausen --- library/util_dac_unpack/util_dac_unpack.v | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/library/util_dac_unpack/util_dac_unpack.v b/library/util_dac_unpack/util_dac_unpack.v index cf2b9e8cf..ab1761f91 100644 --- a/library/util_dac_unpack/util_dac_unpack.v +++ b/library/util_dac_unpack/util_dac_unpack.v @@ -164,6 +164,11 @@ module util_dac_unpack ( assign dac_data_05 = dac_data[DATA_WIDTH*6-1:DATA_WIDTH*5]; assign dac_data_06 = dac_data[DATA_WIDTH*7-1:DATA_WIDTH*6]; assign dac_data_07 = dac_data[DATA_WIDTH*8-1:DATA_WIDTH*7]; + end else begin + assign dac_data_04 = 'h0; + assign dac_data_05 = 'h0; + assign dac_data_06 = 'h0; + assign dac_data_07 = 'h0; end endgenerate From 8fa4b0c56d95330ab434266632223e025b56ddf9 Mon Sep 17 00:00:00 2001 From: Lars-Peter Clausen Date: Mon, 29 Sep 2014 19:55:16 +0200 Subject: [PATCH 14/42] util_dac_unpack: Don't use localparam symbols in input/output signals When using a localparam for the width of a input/output signal the tools won't be able to infer the size of the signal. This results in the signal always being only 1 bit wide which causes the design to not work. Signed-off-by: Lars-Peter Clausen --- library/util_dac_unpack/util_dac_unpack.v | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/library/util_dac_unpack/util_dac_unpack.v b/library/util_dac_unpack/util_dac_unpack.v index ab1761f91..21ac70aae 100644 --- a/library/util_dac_unpack/util_dac_unpack.v +++ b/library/util_dac_unpack/util_dac_unpack.v @@ -81,7 +81,6 @@ module util_dac_unpack ( parameter CHANNELS = 8; // valid values are 4 and 8 parameter DATA_WIDTH = 16; - localparam DMA_WIDTH = CHANNELS * DATA_WIDTH; input clk; @@ -117,11 +116,12 @@ module util_dac_unpack ( input dac_valid_07; output [DATA_WIDTH-1:0] dac_data_07; - input fifo_valid; - output dma_rd; - input [DMA_WIDTH-1:0] dma_data; + input fifo_valid; + output dma_rd; + input [CHANNELS*DATA_WIDTH-1:0] dma_data; + localparam DMA_WIDTH = CHANNELS*DATA_WIDTH; wire [CHANNELS-1:0] dac_enable; wire [CHANNELS-1:0] dac_valid; From 48921bc872e19483dc0730f7b32892cd77fcfda3 Mon Sep 17 00:00:00 2001 From: Lars-Peter Clausen Date: Mon, 29 Sep 2014 19:56:55 +0200 Subject: [PATCH 15/42] util_adc_pack: Hide unused signals Hide unused signals based on the number of selected channels. This silences a few warnings from the tools about unconnected pins. Signed-off-by: Lars-Peter Clausen --- library/util_adc_pack/util_adc_pack_ip.tcl | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/library/util_adc_pack/util_adc_pack_ip.tcl b/library/util_adc_pack/util_adc_pack_ip.tcl index d85d8ba24..6d8de5c1a 100644 --- a/library/util_adc_pack/util_adc_pack_ip.tcl +++ b/library/util_adc_pack/util_adc_pack_ip.tcl @@ -18,6 +18,14 @@ ipx::remove_memory_map {m} [ipx::current_core] ipx::remove_address_space {s} [ipx::current_core] ipx::remove_address_space {fifo} [ipx::current_core] +for {set i 0} {$i < 8} {incr i} { + foreach port {"chan_enable" "chan_valid" "chan_data"} { + set name [format "%s_%d" $port $i] + set_property ENABLEMENT_DEPENDENCY \ + "(spirit:decode(id('MODELPARAM_VALUE.CHANNELS')) > $i)" \ + [ipx::get_ports $name] + set_property DRIVER_VALUE "0" [ipx::get_ports $name] + } +} + ipx::save_core [ipx::current_core] - - From f83fd6dae3cf8703bfb0a50f2b9ecd888c81346c Mon Sep 17 00:00:00 2001 From: Lars-Peter Clausen Date: Tue, 30 Sep 2014 10:38:01 +0200 Subject: [PATCH 16/42] util_dac_unpack: Hide unused signals Hide unused signals based on the number of selected channels. This silences a few warnings from the tools about unconnected pins. Signed-off-by: Lars-Peter Clausen --- library/util_dac_unpack/util_dac_unpack_ip.tcl | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/library/util_dac_unpack/util_dac_unpack_ip.tcl b/library/util_dac_unpack/util_dac_unpack_ip.tcl index b91c85021..0a0bd7393 100644 --- a/library/util_dac_unpack/util_dac_unpack_ip.tcl +++ b/library/util_dac_unpack/util_dac_unpack_ip.tcl @@ -18,6 +18,19 @@ ipx::remove_memory_map {m} [ipx::current_core] ipx::remove_address_space {s} [ipx::current_core] ipx::remove_address_space {fifo} [ipx::current_core] +for {set i 0} {$i < 8} {incr i} { + foreach port {"dac_enable" "dac_valid" "dac_data"} { + set name [format "%s_%.2d" $port $i] + set_property ENABLEMENT_DEPENDENCY \ + "(spirit:decode(id('MODELPARAM_VALUE.CHANNELS')) > $i)" \ + [ipx::get_ports $name] + } + foreach port {"dac_enable" "dac_valid"} { + set name [format "%s_%.2d" $port $i] + set_property DRIVER_VALUE "0" [ipx::get_ports $name] + } +} + ipx::save_core [ipx::current_core] From d32db3a993ba9d265d8d8f0e7ea6a355c50a5ca8 Mon Sep 17 00:00:00 2001 From: Lars-Peter Clausen Date: Mon, 29 Sep 2014 21:47:15 +0200 Subject: [PATCH 17/42] axi_dmac: Fix dummy AXI a{r,w}len fields width The dummy a{r,w}len fields should have the same width as the real a{w,r}len fields in order to not break auto AXI bus version detection. Signed-off-by: Lars-Peter Clausen --- library/axi_dmac/axi_dmac.v | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/library/axi_dmac/axi_dmac.v b/library/axi_dmac/axi_dmac.v index 179c8946f..df8653c64 100644 --- a/library/axi_dmac/axi_dmac.v +++ b/library/axi_dmac/axi_dmac.v @@ -95,7 +95,7 @@ module axi_dmac ( // Unused read interface output m_dest_axi_arvalid, output [31:0] m_dest_axi_araddr, - output [ 7:0] m_dest_axi_arlen, + output [7-(4*C_DMA_AXI_PROTOCOL_DEST):0] m_dest_axi_arlen, output [ 2:0] m_dest_axi_arsize, output [ 1:0] m_dest_axi_arburst, output [ 3:0] m_dest_axi_arcache, @@ -125,7 +125,7 @@ module axi_dmac ( // Unused write interface output m_src_axi_awvalid, output [31:0] m_src_axi_awaddr, - output [ 7:0] m_src_axi_awlen, + output [7-(4*C_DMA_AXI_PROTOCOL_SRC):0] m_src_axi_awlen, output [ 2:0] m_src_axi_awsize, output [ 1:0] m_src_axi_awburst, output [ 3:0] m_src_axi_awcache, From 3944af4179b85c252ab693b02a1473477a4e63af Mon Sep 17 00:00:00 2001 From: Lars-Peter Clausen Date: Mon, 29 Sep 2014 19:55:46 +0200 Subject: [PATCH 18/42] axi_dmac: Drive unused signals to 0 This silences a few warnings from the tools about undriven signals. Signed-off-by: Lars-Peter Clausen --- library/axi_dmac/axi_dmac.v | 17 +++++++++++++++++ library/axi_dmac/request_arb.v | 1 + 2 files changed, 18 insertions(+) diff --git a/library/axi_dmac/axi_dmac.v b/library/axi_dmac/axi_dmac.v index df8653c64..5f3c30da7 100644 --- a/library/axi_dmac/axi_dmac.v +++ b/library/axi_dmac/axi_dmac.v @@ -601,9 +601,26 @@ dmac_request_arb #( assign m_dest_axi_arvalid = 1'b0; assign m_dest_axi_rready = 1'b0; +assign m_dest_axi_araddr = 'h0; +assign m_dest_axi_arlen = 'h0; +assign m_dest_axi_arsize = 'h0; +assign m_dest_axi_arburst = 'h0; +assign m_dest_axi_arcache = 'h0; +assign m_dest_axi_arprot = 'h0; assign m_src_axi_awvalid = 1'b0; assign m_src_axi_wvalid = 1'b0; assign m_src_axi_bready = 1'b0; +assign m_src_axi_awvalid = 'h0; +assign m_src_axi_awaddr = 'h0; +assign m_src_axi_awlen = 'h0; +assign m_src_axi_awsize = 'h0; +assign m_src_axi_awburst = 'h0; +assign m_src_axi_awcache = 'h0; +assign m_src_axi_awprot = 'h0; +assign m_src_axi_wvalid = 'h0; +assign m_src_axi_wdata = 'h0; +assign m_src_axi_wstrb = 'h0; +assign m_src_axi_wlast = 'h0; endmodule diff --git a/library/axi_dmac/request_arb.v b/library/axi_dmac/request_arb.v index ee7c9518d..d7caf7e26 100644 --- a/library/axi_dmac/request_arb.v +++ b/library/axi_dmac/request_arb.v @@ -750,6 +750,7 @@ dmac_src_fifo_inf #( end else begin assign fifo_wr_overflow = 1'b0; +assign fifo_wr_xfer_req = 1'b0; end endgenerate From e1451d8b7e9f5c08c90e500eb0607fed341870ca Mon Sep 17 00:00:00 2001 From: Lars-Peter Clausen Date: Mon, 29 Sep 2014 19:59:19 +0200 Subject: [PATCH 19/42] fmcomms2: Set dac_unpack channels to 4 There are only 4 DAC channels in the fmcomms2 design, so set the number of channels of the dac_unpack core to 4. This slightly reduces resource usage as well as reducing the DMA alignment requirement from 128bit to 64bit. The later value is what existing applications expect the alignement requirement to be. Signed-off-by: Lars-Peter Clausen --- projects/fmcomms2/common/fmcomms2_bd.tcl | 19 ++----------------- 1 file changed, 2 insertions(+), 17 deletions(-) diff --git a/projects/fmcomms2/common/fmcomms2_bd.tcl b/projects/fmcomms2/common/fmcomms2_bd.tcl index b9c9d505e..7befbd555 100644 --- a/projects/fmcomms2/common/fmcomms2_bd.tcl +++ b/projects/fmcomms2/common/fmcomms2_bd.tcl @@ -47,13 +47,14 @@ set_property -dict [list CONFIG.C_CLKS_ASYNC_SRC_DEST {1}] $axi_ad9361_dac_dma set_property -dict [list CONFIG.C_CLKS_ASYNC_REQ_SRC {1}] $axi_ad9361_dac_dma set_property -dict [list CONFIG.C_2D_TRANSFER {0}] $axi_ad9361_dac_dma - set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_DEST {128}] $axi_ad9361_dac_dma + set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_DEST {64}] $axi_ad9361_dac_dma # channel packing for the ADC set util_adc_pack [create_bd_cell -type ip -vlnv analog.com:user:util_adc_pack:1.0 util_adc_pack] set_property -dict [list CONFIG.CHANNELS {4}] $util_adc_pack set util_dac_unpack [create_bd_cell -type ip -vlnv analog.com:user:util_dac_unpack:1.0 util_dac_unpack] + set_property -dict [list CONFIG.CHANNELS {4}] $util_dac_unpack # constant 0 set constant_0 [create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.0 constant_0] @@ -177,14 +178,6 @@ if {$sys_zynq == 0} { connect_bd_net -net axi_ad9361_tx_data_out_n [get_bd_ports tx_data_out_n] [get_bd_pins axi_ad9361/tx_data_out_n] connect_bd_net -net axi_ad9361_clk [get_bd_pins util_adc_pack/clk] - connect_bd_net -net gnd [get_bd_pins constant_0/const] [get_bd_pins util_adc_pack/chan_valid_4] - connect_bd_net -net gnd [get_bd_pins constant_0/const] [get_bd_pins util_adc_pack/chan_valid_5] - connect_bd_net -net gnd [get_bd_pins constant_0/const] [get_bd_pins util_adc_pack/chan_valid_6] - connect_bd_net -net gnd [get_bd_pins constant_0/const] [get_bd_pins util_adc_pack/chan_valid_7] - connect_bd_net -net gnd [get_bd_pins constant_0/const] [get_bd_pins util_adc_pack/chan_enable_4] - connect_bd_net -net gnd [get_bd_pins constant_0/const] [get_bd_pins util_adc_pack/chan_enable_5] - connect_bd_net -net gnd [get_bd_pins constant_0/const] [get_bd_pins util_adc_pack/chan_enable_6] - connect_bd_net -net gnd [get_bd_pins constant_0/const] [get_bd_pins util_adc_pack/chan_enable_7] connect_bd_net -net axi_ad9361_adc_valid_i0 [get_bd_pins axi_ad9361/adc_valid_i0] [get_bd_pins util_adc_pack/chan_valid_0] connect_bd_net -net axi_ad9361_adc_valid_q0 [get_bd_pins axi_ad9361/adc_valid_q0] [get_bd_pins util_adc_pack/chan_valid_1] connect_bd_net -net axi_ad9361_adc_valid_i1 [get_bd_pins axi_ad9361/adc_valid_i1] [get_bd_pins util_adc_pack/chan_valid_2] @@ -208,18 +201,10 @@ if {$sys_zynq == 0} { connect_bd_net -net axi_ad9361_dac_valid_1 [get_bd_pins util_dac_unpack/dac_valid_01] [get_bd_pins axi_ad9361/dac_valid_q0] connect_bd_net -net axi_ad9361_dac_valid_2 [get_bd_pins util_dac_unpack/dac_valid_02] [get_bd_pins axi_ad9361/dac_valid_i1] connect_bd_net -net axi_ad9361_dac_valid_3 [get_bd_pins util_dac_unpack/dac_valid_03] [get_bd_pins axi_ad9361/dac_valid_q1] - connect_bd_net -net gnd [get_bd_pins constant_0/const] [get_bd_pins util_dac_unpack/dac_valid_04] - connect_bd_net -net gnd [get_bd_pins constant_0/const] [get_bd_pins util_dac_unpack/dac_valid_05] - connect_bd_net -net gnd [get_bd_pins constant_0/const] [get_bd_pins util_dac_unpack/dac_valid_06] - connect_bd_net -net gnd [get_bd_pins constant_0/const] [get_bd_pins util_dac_unpack/dac_valid_07] connect_bd_net -net axi_ad9361_dac_enable_0 [get_bd_pins util_dac_unpack/dac_enable_00] [get_bd_pins axi_ad9361/dac_enable_i0] connect_bd_net -net axi_ad9361_dac_enable_1 [get_bd_pins util_dac_unpack/dac_enable_01] [get_bd_pins axi_ad9361/dac_enable_q0] connect_bd_net -net axi_ad9361_dac_enable_2 [get_bd_pins util_dac_unpack/dac_enable_02] [get_bd_pins axi_ad9361/dac_enable_i1] connect_bd_net -net axi_ad9361_dac_enable_3 [get_bd_pins util_dac_unpack/dac_enable_03] [get_bd_pins axi_ad9361/dac_enable_q1] - connect_bd_net -net gnd [get_bd_pins constant_0/const] [get_bd_pins util_dac_unpack/dac_enable_04] - connect_bd_net -net gnd [get_bd_pins constant_0/const] [get_bd_pins util_dac_unpack/dac_enable_05] - connect_bd_net -net gnd [get_bd_pins constant_0/const] [get_bd_pins util_dac_unpack/dac_enable_06] - connect_bd_net -net gnd [get_bd_pins constant_0/const] [get_bd_pins util_dac_unpack/dac_enable_07] connect_bd_net -net axi_ad9361_dac_data_0 [get_bd_pins util_dac_unpack/dac_data_00] [get_bd_pins axi_ad9361/dac_data_i0] connect_bd_net -net axi_ad9361_dac_data_1 [get_bd_pins util_dac_unpack/dac_data_01] [get_bd_pins axi_ad9361/dac_data_q0] connect_bd_net -net axi_ad9361_dac_data_2 [get_bd_pins util_dac_unpack/dac_data_02] [get_bd_pins axi_ad9361/dac_data_i1] From fd6b3b5427fc292a3affabb9b6564df58f654bcc Mon Sep 17 00:00:00 2001 From: Lars-Peter Clausen Date: Tue, 30 Sep 2014 10:40:46 +0200 Subject: [PATCH 20/42] fmcomms2: Connect DMA directly to the HP ports The DMA controller is able to send AXI3 compatible requests, no need to add a interconnect for protocol conversion in between the DMA controller and the HP port. Signed-off-by: Lars-Peter Clausen --- projects/fmcomms2/common/fmcomms2_bd.tcl | 27 ++++++------------------ 1 file changed, 6 insertions(+), 21 deletions(-) diff --git a/projects/fmcomms2/common/fmcomms2_bd.tcl b/projects/fmcomms2/common/fmcomms2_bd.tcl index 7befbd555..6c388e422 100644 --- a/projects/fmcomms2/common/fmcomms2_bd.tcl +++ b/projects/fmcomms2/common/fmcomms2_bd.tcl @@ -61,8 +61,7 @@ set_property -dict [list CONFIG.CONST_VAL {0}] $constant_0 if {$sys_zynq == 1} { - set axi_ad9361_dac_dma_interconnect [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_ad9361_dac_dma_interconnect] - set_property -dict [list CONFIG.NUM_MI {1}] $axi_ad9361_dac_dma_interconnect + set_property -dict [list CONFIG.C_DMA_AXI_PROTOCOL_SRC {1}] $axi_ad9361_dac_dma } set axi_ad9361_adc_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad9361_adc_dma] @@ -79,8 +78,7 @@ if {$sys_zynq == 1} { set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_SRC {64}] $axi_ad9361_adc_dma if {$sys_zynq == 1} { - set axi_ad9361_adc_dma_interconnect [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_ad9361_adc_dma_interconnect] - set_property -dict [list CONFIG.NUM_MI {1}] $axi_ad9361_adc_dma_interconnect + set_property -dict [list CONFIG.C_DMA_AXI_PROTOCOL_DEST {1}] $axi_ad9361_adc_dma } # spi @@ -279,29 +277,16 @@ if {$sys_zynq == 0} { connect_bd_net -net sys_100m_resetn [get_bd_pins axi_mem_interconnect/S09_ARESETN] $sys_100m_resetn_source connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9361_adc_dma/m_dest_axi_aresetn] } else { - connect_bd_intf_net -intf_net axi_ad9361_dac_dma_interconnect_s00_axi [get_bd_intf_pins axi_ad9361_dac_dma_interconnect/S00_AXI] [get_bd_intf_pins axi_ad9361_dac_dma/m_src_axi] - connect_bd_intf_net -intf_net axi_ad9361_dac_dma_interconnect_m00_axi [get_bd_intf_pins axi_ad9361_dac_dma_interconnect/M00_AXI] [get_bd_intf_pins sys_ps7/S_AXI_HP2] - connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_ad9361_dac_dma_interconnect/ACLK] $sys_fmc_dma_clk_source - connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_ad9361_dac_dma_interconnect/M00_ACLK] $sys_fmc_dma_clk_source - connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_ad9361_dac_dma_interconnect/S00_ACLK] $sys_fmc_dma_clk_source + connect_bd_intf_net -intf_net axi_ad9361_dac_dma_axi [get_bd_intf_pins axi_ad9361_dac_dma/m_src_axi] [get_bd_intf_pins sys_ps7/S_AXI_HP2] connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_ad9361_dac_dma/m_src_axi_aclk] connect_bd_net -net sys_fmc_dma_clk [get_bd_pins sys_ps7/S_AXI_HP2_ACLK] - connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9361_dac_dma_interconnect/ARESETN] $sys_100m_resetn_source - connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9361_dac_dma_interconnect/M00_ARESETN] $sys_100m_resetn_source - connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9361_dac_dma_interconnect/S00_ARESETN] $sys_100m_resetn_source connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9361_dac_dma/m_src_axi_aresetn] - connect_bd_intf_net -intf_net axi_ad9361_adc_dma_interconnect_s00_axi [get_bd_intf_pins axi_ad9361_adc_dma_interconnect/S00_AXI] [get_bd_intf_pins axi_ad9361_adc_dma/m_dest_axi] - connect_bd_intf_net -intf_net axi_ad9361_adc_dma_interconnect_m00_axi [get_bd_intf_pins axi_ad9361_adc_dma_interconnect/M00_AXI] [get_bd_intf_pins sys_ps7/S_AXI_HP1] - connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_ad9361_adc_dma_interconnect/ACLK] $sys_fmc_dma_clk_source - connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_ad9361_adc_dma_interconnect/M00_ACLK] $sys_fmc_dma_clk_source - connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_ad9361_adc_dma_interconnect/S00_ACLK] $sys_fmc_dma_clk_source + connect_bd_intf_net -intf_net axi_ad9361_adc_dma_axi [get_bd_intf_pins axi_ad9361_adc_dma/m_dest_axi] [get_bd_intf_pins sys_ps7/S_AXI_HP1] connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_ad9361_adc_dma/m_dest_axi_aclk] - connect_bd_net -net sys_fmc_dma_clk [get_bd_pins sys_ps7/S_AXI_HP1_ACLK] - connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9361_adc_dma_interconnect/ARESETN] $sys_100m_resetn_source - connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9361_adc_dma_interconnect/M00_ARESETN] $sys_100m_resetn_source - connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9361_adc_dma_interconnect/S00_ARESETN] $sys_100m_resetn_source connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9361_adc_dma/m_dest_axi_aresetn] + connect_bd_net -net sys_fmc_dma_clk [get_bd_pins sys_ps7/S_AXI_HP1_ACLK] + } # ila (adc) From ff2e1021827f8a4f19b3777ed9dad0e1c1cceb52 Mon Sep 17 00:00:00 2001 From: Lars-Peter Clausen Date: Tue, 30 Sep 2014 10:46:27 +0200 Subject: [PATCH 21/42] axi_dmac: Add clock signal spec for m_axis/s_axis bus This silences warnings from the tools about having no clock assigned to the bus. Also fix the name of the TVALID signal. Signed-off-by: Lars-Peter Clausen --- library/axi_dmac/axi_dmac_ip.tcl | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/library/axi_dmac/axi_dmac_ip.tcl b/library/axi_dmac/axi_dmac_ip.tcl index 4bc9d5672..6307edf26 100644 --- a/library/axi_dmac/axi_dmac_ip.tcl +++ b/library/axi_dmac/axi_dmac_ip.tcl @@ -38,17 +38,17 @@ set_property physical_name {s_axi_aclk} [ipx::get_port_map CLK \ [ipx::get_bus_interface s_axi_signal_clock [ipx::current_core]]] adi_add_bus "s_axis" "axis" "slave" \ - [list {"s_axis_aclk" "ACLK"} \ - {"s_axis_ready" "TREADY"} \ - {"s_axis_valid" "VALID"} \ + [list {"s_axis_ready" "TREADY"} \ + {"s_axis_valid" "TVALID"} \ {"s_axis_data" "TDATA"} \ {"s_axis_user" "TUSER"} ] +adi_add_bus_clock "s_axis_aclk" "s_axis" adi_add_bus "m_axis" "axis" "master" \ - [list {"m_axis_aclk" "ACLK"} \ - {"m_axis_ready" "TREADY"} \ - {"m_axis_valid" "VALID"} \ + [list {"m_axis_ready" "TREADY"} \ + {"m_axis_valid" "TVALID"} \ {"m_axis_data" "TDATA"} ] +adi_add_bus_clock "m_axis_aclk" "m_axis" adi_set_bus_dependency "m_src_axi" "m_src_axi" \ "(spirit:decode(id('MODELPARAM_VALUE.C_DMA_TYPE_SRC')) = 0)" From 77cbf26241456cf4e98bea7c738ea04ce5a82308 Mon Sep 17 00:00:00 2001 From: Lars-Peter Clausen Date: Tue, 30 Sep 2014 10:47:32 +0200 Subject: [PATCH 22/42] axi_dmac: Hide fifo_wr bus when source type is not the fifo interface Signed-off-by: Lars-Peter Clausen --- library/axi_dmac/axi_dmac_ip.tcl | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/library/axi_dmac/axi_dmac_ip.tcl b/library/axi_dmac/axi_dmac_ip.tcl index 6307edf26..1b7be5eda 100644 --- a/library/axi_dmac/axi_dmac_ip.tcl +++ b/library/axi_dmac/axi_dmac_ip.tcl @@ -58,8 +58,6 @@ adi_set_bus_dependency "s_axis" "s_axis" \ "(spirit:decode(id('MODELPARAM_VALUE.C_DMA_TYPE_SRC')) = 1)" adi_set_bus_dependency "m_axis" "m_axis" \ "(spirit:decode(id('MODELPARAM_VALUE.C_DMA_TYPE_DEST')) = 1)" -adi_set_ports_dependency "fifo_wr" \ - "(spirit:decode(id('MODELPARAM_VALUE.C_DMA_TYPE_SRC')) = 2)" adi_set_ports_dependency "fifo_rd" \ "(spirit:decode(id('MODELPARAM_VALUE.C_DMA_TYPE_DEST')) = 2)" @@ -83,5 +81,7 @@ set_property physical_name {fifo_wr_clk} [ipx::get_port_map CLK [ipx::get_bus_in ipx::add_bus_parameter {ASSOCIATED_BUSIF} [ipx::get_bus_interface fifo_wr_clock [ipx::current_core]] set_property value {fifo_wr} [ipx::get_bus_parameter ASSOCIATED_BUSIF [ipx::get_bus_interface fifo_wr_clock [ipx::current_core]]] -ipx::save_core [ipx::current_core] +adi_set_bus_dependency "fifo_wr" "fifo_wr" \ + "(spirit:decode(id('MODELPARAM_VALUE.C_DMA_TYPE_SRC')) = 2)" +ipx::save_core [ipx::current_core] From 9e7eb81b76eefed7cd2cdbc3e3119da32961e2b8 Mon Sep 17 00:00:00 2001 From: Lars-Peter Clausen Date: Tue, 30 Sep 2014 10:48:45 +0200 Subject: [PATCH 23/42] axi_dmac: Hide fifo_wr_sync signal if C_SYNC_TRANSFER_START != 1 The fifo_wr_sync signal is only used when C_SYNC_TRANSFER_START = 1, so hide it otherwise. Signed-off-by: Lars-Peter Clausen --- library/axi_dmac/axi_dmac_ip.tcl | 3 +++ 1 file changed, 3 insertions(+) diff --git a/library/axi_dmac/axi_dmac_ip.tcl b/library/axi_dmac/axi_dmac_ip.tcl index 1b7be5eda..237c87339 100644 --- a/library/axi_dmac/axi_dmac_ip.tcl +++ b/library/axi_dmac/axi_dmac_ip.tcl @@ -83,5 +83,8 @@ set_property value {fifo_wr} [ipx::get_bus_parameter ASSOCIATED_BUSIF [ipx::get_ adi_set_bus_dependency "fifo_wr" "fifo_wr" \ "(spirit:decode(id('MODELPARAM_VALUE.C_DMA_TYPE_SRC')) = 2)" +set_property ENABLEMENT_DEPENDENCY \ + "(spirit:decode(id('MODELPARAM_VALUE.C_DMA_TYPE_SRC')) = 2 and spirit:decode(id('MODELPARAM_VALUE.C_SYNC_TRANSFER_START')) = 1)" \ + [ipx::get_ports "fifo_wr_sync"] ipx::save_core [ipx::current_core] From e5a9633f84ea103fb8a8979160ebe7e33a5a8a7a Mon Sep 17 00:00:00 2001 From: Lars-Peter Clausen Date: Tue, 30 Sep 2014 10:49:51 +0200 Subject: [PATCH 24/42] axi_dmac: Add default driver values for optional input ports This silences warnings from the tools about undriven ports. Signed-off-by: Lars-Peter Clausen --- library/axi_dmac/axi_dmac_ip.tcl | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/library/axi_dmac/axi_dmac_ip.tcl b/library/axi_dmac/axi_dmac_ip.tcl index 237c87339..dda6b1897 100644 --- a/library/axi_dmac/axi_dmac_ip.tcl +++ b/library/axi_dmac/axi_dmac_ip.tcl @@ -87,4 +87,13 @@ set_property ENABLEMENT_DEPENDENCY \ "(spirit:decode(id('MODELPARAM_VALUE.C_DMA_TYPE_SRC')) = 2 and spirit:decode(id('MODELPARAM_VALUE.C_SYNC_TRANSFER_START')) = 1)" \ [ipx::get_ports "fifo_wr_sync"] +foreach port {"m_dest_axi_aresetn" "m_src_axi_aresetn" "s_axis_valid" \ + "s_axis_data" "m_axis_ready" "fifo_wr_en" "fifo_wr_din" "fifo_rd_en"} { + set_property DRIVER_VALUE "0" [ipx::get_ports $port] +} + +foreach port {"s_axis_user" "fifo_wr_sync"} { + set_property DRIVER_VALUE "1" [ipx::get_ports $port] +} + ipx::save_core [ipx::current_core] From 32dd1d1a4a68ff4a930f5cae9bfedc405b24a58a Mon Sep 17 00:00:00 2001 From: Lars-Peter Clausen Date: Tue, 30 Sep 2014 11:22:14 +0200 Subject: [PATCH 25/42] axi_i2s: Set unused signals to 0 Fixes warnings from the tools about undriven signals. Signed-off-by: Lars-Peter Clausen --- library/axi_i2s_adi/axi_i2s_adi.vhd | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/library/axi_i2s_adi/axi_i2s_adi.vhd b/library/axi_i2s_adi/axi_i2s_adi.vhd index 789420e5e..322aa2bd1 100644 --- a/library/axi_i2s_adi/axi_i2s_adi.vhd +++ b/library/axi_i2s_adi/axi_i2s_adi.vhd @@ -200,6 +200,10 @@ begin ); end generate; + no_streaming_dma_tx_gen: if C_DMA_TYPE /= 0 or C_HAS_TX /= 1 generate + S_AXIS_TREADY <= '0'; + end generate; + streaming_dma_rx_gen: if C_DMA_TYPE = 0 and C_HAS_RX = 1 generate rx_fifo : entity axi_streaming_dma_rx_fifo generic map( @@ -229,6 +233,15 @@ begin M_AXIS_TDATA(7 downto 0) <= (others => '0'); end generate; + no_streaming_dma_rx_gen: if C_DMA_TYPE /= 0 or C_HAS_RX /= 1 generate + M_AXIS_TDATA <= (others => '0'); + M_AXIS_TLAST <= '0'; + M_AXIS_TVALID <= '0'; + M_AXIS_TKEEP <= (others => '0'); + end generate; + + + pl330_dma_tx_gen: if C_DMA_TYPE = 1 and C_HAS_TX = 1 generate tx_fifo_stb <= '1' when wr_addr = 11 and wr_stb = '1' else '0'; @@ -263,6 +276,12 @@ begin ); end generate; + no_pl330_dma_tx_gen: if C_DMA_TYPE /= 1 or C_HAS_TX /= 1 generate + DMA_REQ_TX_DAREADY <= '0'; + DMA_REQ_TX_DRVALID <= '0'; + DMA_REQ_TX_DRTYPE <= (others => '0'); + DMA_REQ_TX_DRLAST <= '0'; + end generate; pl330_dma_rx_gen: if C_DMA_TYPE = 1 and C_HAS_RX = 1 generate rx_fifo_ack <= '1' when rd_addr = 10 and rd_ack = '1' else '0'; @@ -296,6 +315,14 @@ begin drtype => DMA_REQ_RX_DRTYPE, drlast => DMA_REQ_RX_DRLAST ); + + end generate; + + no_pl330_dma_rx_gen: if C_DMA_TYPE /= 1 or C_HAS_RX /= 1 generate + DMA_REQ_RX_DAREADY <= '0'; + DMA_REQ_RX_DRVALID <= '0'; + DMA_REQ_RX_DRTYPE <= (others => '0'); + DMA_REQ_RX_DRLAST <= '0'; end generate; ctrl : entity i2s_controller From 96339ba96f205c515e01f3ceb8c59147dc39616f Mon Sep 17 00:00:00 2001 From: Lars-Peter Clausen Date: Tue, 30 Sep 2014 11:34:57 +0200 Subject: [PATCH 26/42] axi_i2s: Add missing signals to the regmap read process sensitivity list Signed-off-by: Lars-Peter Clausen --- library/axi_i2s_adi/axi_i2s_adi.vhd | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/library/axi_i2s_adi/axi_i2s_adi.vhd b/library/axi_i2s_adi/axi_i2s_adi.vhd index 322aa2bd1..9d3bd5a6a 100644 --- a/library/axi_i2s_adi/axi_i2s_adi.vhd +++ b/library/axi_i2s_adi/axi_i2s_adi.vhd @@ -405,7 +405,7 @@ begin wr_stb => wr_stb ); - process(rd_addr) + process(rd_addr, I2S_CONTROL_REG, I2S_CLK_CONTROL_REG, PERIOD_LEN_REG, rx_sample, cnt) begin case rd_addr is when 1 => rd_data <= I2S_CONTROL_REG and x"00000003"; From 8a994db28ba58e35ace46c909de9bb0593272de2 Mon Sep 17 00:00:00 2001 From: Lars-Peter Clausen Date: Tue, 30 Sep 2014 11:23:20 +0200 Subject: [PATCH 27/42] axi_spdif: Set unused signals to 0 Fixes warnings about undriven signals from the tools. Signed-off-by: Lars-Peter Clausen --- library/axi_spdif_tx/axi_spdif_tx.vhd | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/library/axi_spdif_tx/axi_spdif_tx.vhd b/library/axi_spdif_tx/axi_spdif_tx.vhd index 8c2256595..89f71230c 100644 --- a/library/axi_spdif_tx/axi_spdif_tx.vhd +++ b/library/axi_spdif_tx/axi_spdif_tx.vhd @@ -158,6 +158,10 @@ begin ); end generate; + no_streaming_dma_gen: if C_DMA_TYPE /= 0 generate + S_AXIS_TREADY <= '0'; + end generate; + pl330_dma_gen: if C_DMA_TYPE = 1 generate tx_fifo_stb <= '1' when wr_addr = 3 and wr_stb = '1' else '0'; @@ -191,6 +195,13 @@ begin ); end generate; + no_pl330_dma_gen: if C_DMA_TYPE /= 1 generate + DMA_REQ_DAREADY <= '0'; + DMA_REQ_DRVALID <= '0'; + DMA_REQ_DRTYPE <= (others => '0'); + DMA_REQ_DRLAST <= '0'; + end generate; + sample_data_mux: process (fifo_data_out, channel) is begin if channel = '0' then From f60e112b50ef63eb77a088ffdfc8e4a456708e53 Mon Sep 17 00:00:00 2001 From: Lars-Peter Clausen Date: Tue, 30 Sep 2014 11:32:28 +0200 Subject: [PATCH 28/42] axi_spdif: Don't use non-static expressions in port assignments Fixes a warning from the tools. Signed-off-by: Lars-Peter Clausen --- library/axi_spdif_tx/axi_spdif_tx.vhd | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/library/axi_spdif_tx/axi_spdif_tx.vhd b/library/axi_spdif_tx/axi_spdif_tx.vhd index 89f71230c..c5aed5a84 100644 --- a/library/axi_spdif_tx/axi_spdif_tx.vhd +++ b/library/axi_spdif_tx/axi_spdif_tx.vhd @@ -120,8 +120,10 @@ architecture IMP of axi_spdif_tx is signal conf_ratio : std_logic_vector(7 downto 0); signal conf_tinten, conf_txdata, conf_txen : std_logic; signal channel : std_logic; + signal enable : boolean; signal fifo_data_out : std_logic_vector(31 downto 0); + signal fifo_data_ack : std_logic; signal fifo_reset : std_logic; signal tx_fifo_stb : std_logic; @@ -135,6 +137,8 @@ architecture IMP of axi_spdif_tx is begin fifo_reset <= not conf_txdata; + enable <= conf_txdata = '1'; + fifo_data_ack <= channel and sample_data_ack; streaming_dma_gen: if C_DMA_TYPE = 0 generate fifo: entity axi_streaming_dma_tx_fifo @@ -146,14 +150,14 @@ begin clk => S_AXI_ACLK, resetn => S_AXI_ARESETN, fifo_reset => fifo_reset, - enable => conf_txdata = '1', + enable => enable, S_AXIS_ACLK => S_AXIS_ACLK, S_AXIS_TREADY => S_AXIS_TREADY, S_AXIS_TDATA => S_AXIS_TDATA, S_AXIS_TVALID => S_AXIS_TLAST, S_AXIS_TLAST => S_AXIS_TVALID, - out_ack => channel and sample_data_ack, + out_ack => fifo_data_ack, out_data => fifo_data_out ); end generate; @@ -175,12 +179,12 @@ begin clk => S_AXI_ACLK, resetn => S_AXI_ARESETN, fifo_reset => fifo_reset, - enable => conf_txdata = '1', + enable => enable, in_data => wr_data, in_stb => tx_fifo_stb, - out_ack => channel and sample_data_ack, + out_ack => fifo_data_ack, out_data => fifo_data_out, dclk => DMA_REQ_ACLK, From 98dd47e783f666946b7d54023581173bddee1f3b Mon Sep 17 00:00:00 2001 From: Lars-Peter Clausen Date: Tue, 30 Sep 2014 11:33:25 +0200 Subject: [PATCH 29/42] axi_spdif: Add missing signals to the regmap read sensitifity list Signed-off-by: Lars-Peter Clausen --- library/axi_spdif_tx/axi_spdif_tx.vhd | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/library/axi_spdif_tx/axi_spdif_tx.vhd b/library/axi_spdif_tx/axi_spdif_tx.vhd index c5aed5a84..3834c8aad 100644 --- a/library/axi_spdif_tx/axi_spdif_tx.vhd +++ b/library/axi_spdif_tx/axi_spdif_tx.vhd @@ -309,7 +309,7 @@ begin end if; end process; - process (rd_addr) + process (rd_addr, config_reg, chstatus_reg) begin case rd_addr is when 0 => rd_data <= config_reg; From 68c0c72e53cdf05d2dab2f629c735ff20f032f04 Mon Sep 17 00:00:00 2001 From: Lars-Peter Clausen Date: Tue, 30 Sep 2014 18:48:04 +0200 Subject: [PATCH 30/42] util_dac_unpack: Fix unpack order with 1 channel Due to the delay between the dac_valid and the fifo_valid signal we need to have two counters. One counter which counts the number of incoming dac_valid signals and generates the dma_rd signal and one counter for the offset which gets set to 0 when fifo_valid is set. This fixes issues with the unpack order when only one channel is active. Signed-off-by: Lars-Peter Clausen --- library/util_dac_unpack/util_dac_unpack.v | 27 ++++++++++++++--------- 1 file changed, 17 insertions(+), 10 deletions(-) diff --git a/library/util_dac_unpack/util_dac_unpack.v b/library/util_dac_unpack/util_dac_unpack.v index 21ac70aae..0c5df5b35 100644 --- a/library/util_dac_unpack/util_dac_unpack.v +++ b/library/util_dac_unpack/util_dac_unpack.v @@ -134,7 +134,8 @@ module util_dac_unpack ( reg [DATA_WIDTH*CHANNELS-1:0] dac_data = 'h00; reg [DMA_WIDTH-1:0] buffer = 'h00; reg dma_rd = 1'b0; - reg [$clog2(CHANNELS)-1:0] counter = 'h00; + reg [$clog2(CHANNELS)-1:0] rd_counter = 'h00; + reg [$clog2(CHANNELS)-1:0] req_counter = 'h00; reg [CHANNELS-1:0] dac_enable_d1 = 'h00; assign dac_enable[0] = dac_enable_00; @@ -187,18 +188,22 @@ module util_dac_unpack ( always @(posedge clk) begin if (fifo_valid == 1'b1) begin - buffer <= dma_data; + buffer <= dma_data; + rd_counter <= 'h0; + end else if (dac_chan_valid == 1'b1) begin + rd_counter <= rd_counter + enable_reduce(CHANNELS); end end always @(posedge clk) begin dma_rd <= 1'b0; if (dac_enable != dac_enable_d1) begin - counter <= 'h00; + req_counter <= 'h00; end else if (dac_chan_valid == 1'b1) begin - counter <= counter + enable_reduce(CHANNELS); - if (counter == 'h00) + req_counter <= req_counter + enable_reduce(CHANNELS); + if (req_counter == 'h00) begin dma_rd <= 1'b1; + end end dac_enable_d1 <= dac_enable; end @@ -213,12 +218,14 @@ module util_dac_unpack ( generate genvar j; for (j = 0; j < CHANNELS; j = j + 1) begin : gen_dac_data - assign offset[j] = counter + enable_reduce(j); + assign offset[j] = rd_counter + enable_reduce(j); always @(posedge clk) begin - if (dac_enable[j]) - dac_data[DATA_WIDTH+j*DATA_WIDTH-1:j*DATA_WIDTH] <= data_array[offset[j]]; - else - dac_data[DATA_WIDTH+j*DATA_WIDTH-1:j*DATA_WIDTH] <= 'h0000; + if (dac_chan_valid) begin + if (dac_enable[j]) + dac_data[DATA_WIDTH+j*DATA_WIDTH-1:j*DATA_WIDTH] <= data_array[offset[j]]; + else + dac_data[DATA_WIDTH+j*DATA_WIDTH-1:j*DATA_WIDTH] <= 'h0000; + end end end endgenerate From 801f12f37388fe683323ebc2c213c79fcb04adb6 Mon Sep 17 00:00:00 2001 From: Istvan Csomortani Date: Thu, 2 Oct 2014 11:34:37 +0300 Subject: [PATCH 31/42] ad9467: Fix LVDS delay interface. --- library/axi_ad9467/axi_ad9467.v | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/library/axi_ad9467/axi_ad9467.v b/library/axi_ad9467/axi_ad9467.v index 7d1f4d4e9..c1d10bfd5 100644 --- a/library/axi_ad9467/axi_ad9467.v +++ b/library/axi_ad9467/axi_ad9467.v @@ -211,7 +211,7 @@ module axi_ad9467( .delay_addr (delay_addr_s), .delay_wdata (delay_wdata_s), .delay_rdata (delay_rdata_s), - .delay_ack_t (delay_ack_t), + .delay_ack_t (delay_ack_t_s), .delay_locked (delay_locked_s)); // channel @@ -258,7 +258,7 @@ module axi_ad9467( .delay_addr (delay_addr_s), .delay_wdata (delay_wdata_s), .delay_rdata (delay_rdata_s), - .delay_ack_t (delay_ack_t), + .delay_ack_t (delay_ack_t_s), .delay_locked (delay_locked_s), .drp_clk (1'b0), .drp_rst (), From 1defad36b8799e9369ee658b0e443d9e40931f39 Mon Sep 17 00:00:00 2001 From: Lars-Peter Clausen Date: Thu, 2 Oct 2014 13:33:50 +0200 Subject: [PATCH 32/42] fmcomms1: Connect DMA controller directly to the HP ports The AXI DMAC controller nativly supports AXI3, there is no need to insert a interconnect to do protocol conversion. Signed-off-by: Lars-Peter Clausen --- projects/fmcomms1/common/fmcomms1_bd.tcl | 24 ++++-------------------- 1 file changed, 4 insertions(+), 20 deletions(-) diff --git a/projects/fmcomms1/common/fmcomms1_bd.tcl b/projects/fmcomms1/common/fmcomms1_bd.tcl index dd5d21ce5..21c5d1cf3 100644 --- a/projects/fmcomms1/common/fmcomms1_bd.tcl +++ b/projects/fmcomms1/common/fmcomms1_bd.tcl @@ -60,8 +60,7 @@ set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_DEST {64}] $axi_ad9122_dma if {$sys_zynq == 1} { - set axi_ad9122_dma_interconnect [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_ad9122_dma_interconnect] - set_property -dict [list CONFIG.NUM_MI {1}] $axi_ad9122_dma_interconnect + set_property -dict [list CONFIG.C_DMA_AXI_PROTOCOL_SRC {1}] $axi_ad9122_dma } # adc peripherals @@ -76,8 +75,7 @@ if {$sys_zynq == 1} { set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_DEST {64}] $axi_ad9643_dma if {$sys_zynq == 1} { - set axi_ad9643_dma_interconnect [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_ad9643_dma_interconnect] - set_property -dict [list CONFIG.NUM_MI {1}] $axi_ad9643_dma_interconnect + set_property -dict [list CONFIG.C_DMA_AXI_PROTOCOL_DEST {1}] $axi_ad9643_dma } # additions to default configuration @@ -204,16 +202,9 @@ if {$sys_zynq == 0 } { connect_bd_net -net sys_100m_resetn [get_bd_pins axi_mem_interconnect/S08_ARESETN] $sys_100m_resetn_source connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9122_dma/m_src_axi_aresetn] } else { - connect_bd_intf_net -intf_net axi_ad9122_dma_interconnect_s00_axi [get_bd_intf_pins axi_ad9122_dma_interconnect/S00_AXI] [get_bd_intf_pins axi_ad9122_dma/m_src_axi] - connect_bd_intf_net -intf_net axi_ad9122_dma_interconnect_m00_axi [get_bd_intf_pins axi_ad9122_dma_interconnect/M00_AXI] [get_bd_intf_pins sys_ps7/S_AXI_HP2] - connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_ad9122_dma_interconnect/ACLK] $sys_fmc_dma_clk_source - connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_ad9122_dma_interconnect/M00_ACLK] $sys_fmc_dma_clk_source - connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_ad9122_dma_interconnect/S00_ACLK] $sys_fmc_dma_clk_source + connect_bd_intf_net -intf_net axi_ad9122_dma_axi [get_bd_intf_pins sys_ps7/S_AXI_HP2] [get_bd_intf_pins axi_ad9122_dma/m_src_axi] connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_ad9122_dma/m_src_axi_aclk] connect_bd_net -net sys_fmc_dma_clk [get_bd_pins sys_ps7/S_AXI_HP2_ACLK] - connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9122_dma_interconnect/ARESETN] $sys_100m_resetn_source - connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9122_dma_interconnect/M00_ARESETN] $sys_100m_resetn_source - connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9122_dma_interconnect/S00_ARESETN] $sys_100m_resetn_source connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9122_dma/m_src_axi_aresetn] } @@ -226,16 +217,9 @@ if {$sys_zynq == 0 } { connect_bd_net -net sys_100m_resetn [get_bd_pins axi_mem_interconnect/S09_ARESETN] $sys_100m_resetn_source connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9643_dma/m_dest_axi_aresetn] } else { - connect_bd_intf_net -intf_net axi_ad9643_dma_interconnect_s00_axi [get_bd_intf_pins axi_ad9643_dma_interconnect/S00_AXI] [get_bd_intf_pins axi_ad9643_dma/m_dest_axi] - connect_bd_intf_net -intf_net axi_ad9643_dma_interconnect_m00_axi [get_bd_intf_pins axi_ad9643_dma_interconnect/M00_AXI] [get_bd_intf_pins sys_ps7/S_AXI_HP1] - connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_ad9643_dma_interconnect/ACLK] $sys_fmc_dma_clk_source - connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_ad9643_dma_interconnect/M00_ACLK] $sys_fmc_dma_clk_source - connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_ad9643_dma_interconnect/S00_ACLK] $sys_fmc_dma_clk_source + connect_bd_intf_net -intf_net axi_ad9643_dma_axi [get_bd_intf_pins sys_ps7/S_AXI_HP1] [get_bd_intf_pins axi_ad9643_dma/m_dest_axi] connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_ad9643_dma/m_dest_axi_aclk] connect_bd_net -net sys_fmc_dma_clk [get_bd_pins sys_ps7/S_AXI_HP1_ACLK] - connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9643_dma_interconnect/ARESETN] $sys_100m_resetn_source - connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9643_dma_interconnect/M00_ARESETN] $sys_100m_resetn_source - connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9643_dma_interconnect/S00_ARESETN] $sys_100m_resetn_source connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9643_dma/m_dest_axi_aresetn] } From 54053e0d87ce486da365a003c666c1fead03e0ad Mon Sep 17 00:00:00 2001 From: Lars-Peter Clausen Date: Tue, 30 Sep 2014 19:36:03 +0200 Subject: [PATCH 33/42] common: Set cpu interconnect strategy to minimize area There will rarely be concurrent access to the peripheral control bus interconnect, so there is no need to optimize for performace. Setting the interconnect strategy to minimize area can reduce the resource usage by ~90%. Signed-off-by: Lars-Peter Clausen --- projects/common/ac701/ac701_system_bd.tcl | 2 ++ projects/common/kc705/kc705_system_bd.tcl | 2 ++ projects/common/kcu105/kcu105_system_bd.tcl | 2 ++ projects/common/mitx045/mitx045_system_bd.tcl | 1 + projects/common/vc707/vc707_system_bd.tcl | 2 ++ projects/common/zc702/zc702_system_bd.tcl | 1 + projects/common/zc706/zc706_system_bd.tcl | 1 + projects/common/zed/zed_system_bd.tcl | 1 + 8 files changed, 12 insertions(+) diff --git a/projects/common/ac701/ac701_system_bd.tcl b/projects/common/ac701/ac701_system_bd.tcl index 16644e26a..6579ec9d2 100755 --- a/projects/common/ac701/ac701_system_bd.tcl +++ b/projects/common/ac701/ac701_system_bd.tcl @@ -94,9 +94,11 @@ set_property -dict [list CONFIG.XML_INPUT_FILE {ac701_system_mig.prj}] $axi_ddr_ # instance: axi interconnect (lite) set axi_cpu_aux_interconnect [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_cpu_aux_interconnect] set_property -dict [list CONFIG.NUM_MI {8}] $axi_cpu_aux_interconnect +set_property -dict [list CONFIG.STRATEGY {1}] $axi_cpu_aux_interconnect set axi_cpu_interconnect [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_cpu_interconnect] set_property -dict [list CONFIG.NUM_MI {7}] $axi_cpu_interconnect +set_property -dict [list CONFIG.STRATEGY {1}] $axi_cpu_interconnect # instance: axi interconnect diff --git a/projects/common/kc705/kc705_system_bd.tcl b/projects/common/kc705/kc705_system_bd.tcl index 79cea6a1b..4f8055fe9 100644 --- a/projects/common/kc705/kc705_system_bd.tcl +++ b/projects/common/kc705/kc705_system_bd.tcl @@ -107,9 +107,11 @@ set_property -dict [list CONFIG.CONST_VAL {1}] $sys_const_ddr3_1 set axi_cpu_aux_interconnect [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_cpu_aux_interconnect] set_property -dict [list CONFIG.NUM_MI {8}] $axi_cpu_aux_interconnect +set_property -dict [list CONFIG.STRATEGY {1}] $axi_cpu_aux_interconnect set axi_cpu_interconnect [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_cpu_interconnect] set_property -dict [list CONFIG.NUM_MI {7}] $axi_cpu_interconnect +set_property -dict [list CONFIG.STRATEGY {1}] $axi_cpu_interconnect # instance: axi interconnect diff --git a/projects/common/kcu105/kcu105_system_bd.tcl b/projects/common/kcu105/kcu105_system_bd.tcl index 52c80ef65..3e8f7621c 100644 --- a/projects/common/kcu105/kcu105_system_bd.tcl +++ b/projects/common/kcu105/kcu105_system_bd.tcl @@ -92,9 +92,11 @@ set axi_ddr_cntrl_rstgen [create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_r set axi_cpu_aux_interconnect [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_cpu_aux_interconnect] set_property -dict [list CONFIG.NUM_MI {8}] $axi_cpu_aux_interconnect +set_property -dict [list CONFIG.STRATEGY {1}] $axi_cpu_aux_interconnect set axi_cpu_interconnect [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_cpu_interconnect] set_property -dict [list CONFIG.NUM_MI {7}] $axi_cpu_interconnect +set_property -dict [list CONFIG.STRATEGY {1}] $axi_cpu_interconnect # instance: axi interconnect diff --git a/projects/common/mitx045/mitx045_system_bd.tcl b/projects/common/mitx045/mitx045_system_bd.tcl index 5248ccd2c..6754c29dd 100755 --- a/projects/common/mitx045/mitx045_system_bd.tcl +++ b/projects/common/mitx045/mitx045_system_bd.tcl @@ -56,6 +56,7 @@ set_property -dict [list CONFIG.NUM_PORTS {5}] $sys_concat_intc set axi_cpu_interconnect [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_cpu_interconnect] set_property -dict [list CONFIG.NUM_MI {7}] $axi_cpu_interconnect +set_property -dict [list CONFIG.STRATEGY {1}] $axi_cpu_interconnect set sys_rstgen [create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 sys_rstgen] set_property -dict [list CONFIG.C_EXT_RST_WIDTH {1}] $sys_rstgen diff --git a/projects/common/vc707/vc707_system_bd.tcl b/projects/common/vc707/vc707_system_bd.tcl index 93843ec47..a141bc0f0 100644 --- a/projects/common/vc707/vc707_system_bd.tcl +++ b/projects/common/vc707/vc707_system_bd.tcl @@ -98,9 +98,11 @@ set_property -dict [list CONFIG.RESET_BOARD_INTERFACE {Custom}] $axi_ddr_cntrl # instance: axi interconnect (lite) set axi_cpu_aux_interconnect [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_cpu_aux_interconnect] set_property -dict [list CONFIG.NUM_MI {8}] $axi_cpu_aux_interconnect +set_property -dict [list CONFIG.STRATEGY {1}] $axi_cpu_aux_interconnect set axi_cpu_interconnect [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_cpu_interconnect] set_property -dict [list CONFIG.NUM_MI {7}] $axi_cpu_interconnect +set_property -dict [list CONFIG.STRATEGY {1}] $axi_cpu_interconnect # instance: axi interconnect diff --git a/projects/common/zc702/zc702_system_bd.tcl b/projects/common/zc702/zc702_system_bd.tcl index 316d4a483..d191f17bb 100644 --- a/projects/common/zc702/zc702_system_bd.tcl +++ b/projects/common/zc702/zc702_system_bd.tcl @@ -46,6 +46,7 @@ set_property -dict [list CONFIG.NUM_PORTS {5}] $sys_concat_intc set axi_cpu_interconnect [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_cpu_interconnect] set_property -dict [list CONFIG.NUM_MI {7}] $axi_cpu_interconnect +set_property -dict [list CONFIG.STRATEGY {1}] $axi_cpu_interconnect set sys_rstgen [create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 sys_rstgen] set_property -dict [list CONFIG.C_EXT_RST_WIDTH {1}] $sys_rstgen diff --git a/projects/common/zc706/zc706_system_bd.tcl b/projects/common/zc706/zc706_system_bd.tcl index 63d8f7706..84d1cca7f 100644 --- a/projects/common/zc706/zc706_system_bd.tcl +++ b/projects/common/zc706/zc706_system_bd.tcl @@ -46,6 +46,7 @@ set_property -dict [list CONFIG.NUM_PORTS {5}] $sys_concat_intc set axi_cpu_interconnect [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_cpu_interconnect] set_property -dict [list CONFIG.NUM_MI {7}] $axi_cpu_interconnect +set_property -dict [list CONFIG.STRATEGY {1}] $axi_cpu_interconnect set sys_rstgen [create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 sys_rstgen] set_property -dict [list CONFIG.C_EXT_RST_WIDTH {1}] $sys_rstgen diff --git a/projects/common/zed/zed_system_bd.tcl b/projects/common/zed/zed_system_bd.tcl index 433944696..014758e27 100644 --- a/projects/common/zed/zed_system_bd.tcl +++ b/projects/common/zed/zed_system_bd.tcl @@ -69,6 +69,7 @@ set_property -dict [list CONFIG.NUM_PORTS {5}] $sys_concat_intc set axi_cpu_interconnect [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_cpu_interconnect] set_property -dict [list CONFIG.NUM_MI {7}] $axi_cpu_interconnect +set_property -dict [list CONFIG.STRATEGY {1}] $axi_cpu_interconnect set sys_rstgen [create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 sys_rstgen] set_property -dict [list CONFIG.C_EXT_RST_WIDTH {1}] $sys_rstgen From b029d07adf1b7bee3542d4a5bf6093ce363a63fd Mon Sep 17 00:00:00 2001 From: Lars-Peter Clausen Date: Thu, 2 Oct 2014 13:30:30 +0200 Subject: [PATCH 34/42] common: Connect audio clkgen reset While we are at it also hide the unused locked pin. Signed-off-by: Lars-Peter Clausen --- projects/common/ac701/ac701_system_bd.tcl | 3 +++ projects/common/kc705/kc705_system_bd.tcl | 3 +++ projects/common/kcu105/kcu105_system_bd.tcl | 3 +++ projects/common/mitx045/mitx045_system_bd.tcl | 3 +++ projects/common/vc707/vc707_system_bd.tcl | 6 +++--- projects/common/zc702/zc702_system_bd.tcl | 3 +++ projects/common/zc706/zc706_system_bd.tcl | 3 +++ projects/common/zed/zed_system_bd.tcl | 3 +++ 8 files changed, 24 insertions(+), 3 deletions(-) diff --git a/projects/common/ac701/ac701_system_bd.tcl b/projects/common/ac701/ac701_system_bd.tcl index 6579ec9d2..4592c11a7 100755 --- a/projects/common/ac701/ac701_system_bd.tcl +++ b/projects/common/ac701/ac701_system_bd.tcl @@ -167,6 +167,8 @@ set_property -dict [list CONFIG.c_include_s2mm {0}] $axi_hdmi_dma set sys_audio_clkgen [create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:5.1 sys_audio_clkgen] set_property -dict [list CONFIG.PRIM_IN_FREQ {200.000}] $sys_audio_clkgen set_property -dict [list CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {12.288}] $sys_audio_clkgen +set_property -dict [list CONFIG.USE_LOCKED {false}] $sys_audio_clkgen +set_property -dict [list CONFIG.USE_RESET {true} CONFIG.RESET_TYPE {ACTIVE_LOW}] $sys_audio_clkgen set axi_spdif_tx_core [create_bd_cell -type ip -vlnv analog.com:user:axi_spdif_tx:1.0 axi_spdif_tx_core] set_property -dict [list CONFIG.C_DMA_TYPE {0}] $axi_spdif_tx_core @@ -451,6 +453,7 @@ connect_bd_net -net axi_spdif_tx_dma_mm2s_ready [get_bd_pins axi_spdif_tx_core/S connect_bd_net -net sys_200m_clk [get_bd_pins sys_audio_clkgen/clk_in1] +connect_bd_net -net sys_100m_resetn [get_bd_pins sys_audio_clkgen/resetn] $sys_100m_resetn_source connect_bd_net -net sys_audio_clkgen_clk [get_bd_pins sys_audio_clkgen/clk_out1] [get_bd_pins axi_spdif_tx_core/spdif_data_clk] connect_bd_net -net spdif_s [get_bd_ports spdif] [get_bd_pins axi_spdif_tx_core/spdif_tx_o] diff --git a/projects/common/kc705/kc705_system_bd.tcl b/projects/common/kc705/kc705_system_bd.tcl index 4f8055fe9..359a0b347 100644 --- a/projects/common/kc705/kc705_system_bd.tcl +++ b/projects/common/kc705/kc705_system_bd.tcl @@ -173,6 +173,8 @@ set_property -dict [list CONFIG.c_include_s2mm {0}] $axi_hdmi_dma set sys_audio_clkgen [create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:5.1 sys_audio_clkgen] set_property -dict [list CONFIG.PRIM_IN_FREQ {200.000}] $sys_audio_clkgen set_property -dict [list CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {12.288}] $sys_audio_clkgen +set_property -dict [list CONFIG.USE_LOCKED {false}] $sys_audio_clkgen +set_property -dict [list CONFIG.USE_RESET {true} CONFIG.RESET_TYPE {ACTIVE_LOW}] $sys_audio_clkgen set axi_spdif_tx_core [create_bd_cell -type ip -vlnv analog.com:user:axi_spdif_tx:1.0 axi_spdif_tx_core] set_property -dict [list CONFIG.C_DMA_TYPE {0}] $axi_spdif_tx_core @@ -430,6 +432,7 @@ connect_bd_net -net axi_spdif_tx_dma_mm2s_last [get_bd_pins axi_spdif_tx_core/S connect_bd_net -net axi_spdif_tx_dma_mm2s_ready [get_bd_pins axi_spdif_tx_core/S_AXIS_TREADY] [get_bd_pins axi_spdif_tx_dma/m_axis_mm2s_tready] connect_bd_net -net sys_200m_clk [get_bd_pins sys_audio_clkgen/clk_in1] +connect_bd_net -net sys_100m_resetn [get_bd_pins sys_audio_clkgen/resetn] $sys_100m_resetn_source connect_bd_net -net sys_audio_clkgen_clk [get_bd_pins sys_audio_clkgen/clk_out1] [get_bd_pins axi_spdif_tx_core/spdif_data_clk] connect_bd_net -net spdif_s [get_bd_ports spdif] [get_bd_pins axi_spdif_tx_core/spdif_tx_o] diff --git a/projects/common/kcu105/kcu105_system_bd.tcl b/projects/common/kcu105/kcu105_system_bd.tcl index 3e8f7621c..6da19db95 100644 --- a/projects/common/kcu105/kcu105_system_bd.tcl +++ b/projects/common/kcu105/kcu105_system_bd.tcl @@ -200,6 +200,8 @@ set_property -dict [list CONFIG.c_include_s2mm {0}] $axi_hdmi_dma set sys_audio_clkgen [create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:5.1 sys_audio_clkgen] set_property -dict [list CONFIG.PRIM_IN_FREQ {200.000}] $sys_audio_clkgen set_property -dict [list CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {12.288}] $sys_audio_clkgen +set_property -dict [list CONFIG.USE_LOCKED {false}] $sys_audio_clkgen +set_property -dict [list CONFIG.USE_RESET {true} CONFIG.RESET_TYPE {ACTIVE_LOW}] $sys_audio_clkgen set axi_spdif_tx_core [create_bd_cell -type ip -vlnv analog.com:user:axi_spdif_tx:1.0 axi_spdif_tx_core] set_property -dict [list CONFIG.C_DMA_TYPE {0}] $axi_spdif_tx_core @@ -499,6 +501,7 @@ connect_bd_net -net axi_spdif_tx_dma_mm2s_last [get_bd_pins axi_spdif_tx_core/S connect_bd_net -net axi_spdif_tx_dma_mm2s_ready [get_bd_pins axi_spdif_tx_core/S_AXIS_TREADY] [get_bd_pins axi_spdif_tx_dma/m_axis_mm2s_tready] connect_bd_net -net sys_200m_clk [get_bd_pins sys_audio_clkgen/clk_in1] +connect_bd_net -net sys_100m_resetn [get_bd_pins sys_audio_clkgen/resetn] $sys_100m_resetn_source connect_bd_net -net sys_audio_clkgen_clk [get_bd_pins sys_audio_clkgen/clk_out1] [get_bd_pins axi_spdif_tx_core/spdif_data_clk] connect_bd_net -net spdif_s [get_bd_ports spdif] [get_bd_pins axi_spdif_tx_core/spdif_tx_o] diff --git a/projects/common/mitx045/mitx045_system_bd.tcl b/projects/common/mitx045/mitx045_system_bd.tcl index 6754c29dd..8be688117 100755 --- a/projects/common/mitx045/mitx045_system_bd.tcl +++ b/projects/common/mitx045/mitx045_system_bd.tcl @@ -79,6 +79,8 @@ set_property -dict [list CONFIG.NUM_MI {1}] $axi_hdmi_interconnect set sys_audio_clkgen [create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:5.1 sys_audio_clkgen] set_property -dict [list CONFIG.PRIM_IN_FREQ {200.000}] $sys_audio_clkgen set_property -dict [list CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {12.288}] $sys_audio_clkgen +set_property -dict [list CONFIG.USE_LOCKED {false}] $sys_audio_clkgen +set_property -dict [list CONFIG.USE_RESET {true} CONFIG.RESET_TYPE {ACTIVE_LOW}] $sys_audio_clkgen set axi_spdif_tx_core [create_bd_cell -type ip -vlnv analog.com:user:axi_spdif_tx:1.0 axi_spdif_tx_core] set_property -dict [list CONFIG.C_DMA_TYPE {1}] $axi_spdif_tx_core @@ -197,6 +199,7 @@ connect_bd_intf_net -intf_net axi_spdif_dma_req_tx [get_bd_intf_pins sys_ps7/DMA connect_bd_intf_net -intf_net axi_spdif_dma_ack_tx [get_bd_intf_pins sys_ps7/DMA0_ACK] [get_bd_intf_pins axi_spdif_tx_core/DMA_ACK] connect_bd_net -net sys_200m_clk [get_bd_pins sys_audio_clkgen/clk_in1] +connect_bd_net -net sys_100m_resetn [get_bd_pins sys_audio_clkgen/resetn] $sys_100m_resetn_source connect_bd_net -net sys_audio_clkgen_clk [get_bd_pins sys_audio_clkgen/clk_out1] [get_bd_pins axi_spdif_tx_core/spdif_data_clk] connect_bd_net -net spdif_s [get_bd_ports spdif] [get_bd_pins axi_spdif_tx_core/spdif_tx_o] diff --git a/projects/common/vc707/vc707_system_bd.tcl b/projects/common/vc707/vc707_system_bd.tcl index a141bc0f0..c9a5fa9a0 100644 --- a/projects/common/vc707/vc707_system_bd.tcl +++ b/projects/common/vc707/vc707_system_bd.tcl @@ -172,6 +172,8 @@ set_property -dict [list CONFIG.c_include_s2mm {0}] $axi_hdmi_dma set sys_audio_clkgen [create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:5.1 sys_audio_clkgen] set_property -dict [list CONFIG.PRIM_IN_FREQ {200.000}] $sys_audio_clkgen set_property -dict [list CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {12.288}] $sys_audio_clkgen +set_property -dict [list CONFIG.USE_LOCKED {false}] $sys_audio_clkgen +set_property -dict [list CONFIG.USE_RESET {true} CONFIG.RESET_TYPE {ACTIVE_LOW}] $sys_audio_clkgen set axi_spdif_tx_core [create_bd_cell -type ip -vlnv analog.com:user:axi_spdif_tx:1.0 axi_spdif_tx_core] set_property -dict [list CONFIG.C_DMA_TYPE {0}] $axi_spdif_tx_core @@ -216,13 +218,11 @@ connect_bd_net -net sys_concat_intc_intr [get_bd_pins sys_concat_intc/dout] [get connect_bd_net -net axi_ddr_cntrl_mmcm_locked [get_bd_pins axi_ddr_cntrl/mmcm_locked] [get_bd_pins sys_rstgen/dcm_locked] set sys_100m_resetn_source [get_bd_pins sys_rstgen/peripheral_aresetn] -set sys_100m_reset_source [get_bd_pins sys_rstgen/peripheral_reset] set sys_200m_resetn_source [get_bd_pins sys_rstgen/interconnect_aresetn] set sys_100m_clk_source [get_bd_pins axi_ddr_cntrl/ui_clk] set sys_200m_clk_source [get_bd_pins axi_ddr_cntrl/ui_addn_clk_0] connect_bd_net -net sys_100m_resetn $sys_100m_resetn_source -connect_bd_net -net sys_100m_reset $sys_100m_reset_source connect_bd_net -net sys_200m_resetn $sys_200m_resetn_source connect_bd_net -net sys_100m_clk $sys_100m_clk_source connect_bd_net -net sys_200m_clk $sys_200m_clk_source @@ -455,7 +455,7 @@ connect_bd_net -net axi_spdif_tx_dma_mm2s_last [get_bd_pins axi_spdif_tx_core/S connect_bd_net -net axi_spdif_tx_dma_mm2s_ready [get_bd_pins axi_spdif_tx_core/S_AXIS_TREADY] [get_bd_pins axi_spdif_tx_dma/m_axis_mm2s_tready] connect_bd_net -net sys_200m_clk [get_bd_pins sys_audio_clkgen/clk_in1] $sys_200m_clk_source -connect_bd_net -net sys_100m_reset [get_bd_pins sys_audio_clkgen/reset] $sys_100m_reset_source +connect_bd_net -net sys_100m_reset [get_bd_pins sys_audio_clkgen/resetn] $sys_100m_resetn_source connect_bd_net -net sys_audio_clkgen_clk [get_bd_pins sys_audio_clkgen/clk_out1] [get_bd_pins axi_spdif_tx_core/spdif_data_clk] connect_bd_net -net spdif_s [get_bd_ports spdif] [get_bd_pins axi_spdif_tx_core/spdif_tx_o] diff --git a/projects/common/zc702/zc702_system_bd.tcl b/projects/common/zc702/zc702_system_bd.tcl index d191f17bb..2cb3664be 100644 --- a/projects/common/zc702/zc702_system_bd.tcl +++ b/projects/common/zc702/zc702_system_bd.tcl @@ -69,6 +69,8 @@ set_property -dict [list CONFIG.NUM_MI {1}] $axi_hdmi_interconnect set sys_audio_clkgen [create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:5.1 sys_audio_clkgen] set_property -dict [list CONFIG.PRIM_IN_FREQ {200.000}] $sys_audio_clkgen set_property -dict [list CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {12.288}] $sys_audio_clkgen +set_property -dict [list CONFIG.USE_LOCKED {false}] $sys_audio_clkgen +set_property -dict [list CONFIG.USE_RESET {true} CONFIG.RESET_TYPE {ACTIVE_LOW}] $sys_audio_clkgen set axi_spdif_tx_core [create_bd_cell -type ip -vlnv analog.com:user:axi_spdif_tx:1.0 axi_spdif_tx_core] set_property -dict [list CONFIG.C_DMA_TYPE {1}] $axi_spdif_tx_core @@ -182,6 +184,7 @@ connect_bd_intf_net -intf_net axi_spdif_dma_req_tx [get_bd_intf_pins sys_ps7/DMA connect_bd_intf_net -intf_net axi_spdif_dma_ack_tx [get_bd_intf_pins sys_ps7/DMA0_ACK] [get_bd_intf_pins axi_spdif_tx_core/DMA_ACK] connect_bd_net -net sys_200m_clk [get_bd_pins sys_audio_clkgen/clk_in1] +connect_bd_net -net sys_100m_resetn [get_bd_pins sys_audio_clkgen/resetn] $sys_100m_resetn_source connect_bd_net -net sys_audio_clkgen_clk [get_bd_pins sys_audio_clkgen/clk_out1] [get_bd_pins axi_spdif_tx_core/spdif_data_clk] connect_bd_net -net spdif_s [get_bd_ports spdif] [get_bd_pins axi_spdif_tx_core/spdif_tx_o] diff --git a/projects/common/zc706/zc706_system_bd.tcl b/projects/common/zc706/zc706_system_bd.tcl index 84d1cca7f..1807c0fb4 100644 --- a/projects/common/zc706/zc706_system_bd.tcl +++ b/projects/common/zc706/zc706_system_bd.tcl @@ -69,6 +69,8 @@ set_property -dict [list CONFIG.NUM_MI {1}] $axi_hdmi_interconnect set sys_audio_clkgen [create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:5.1 sys_audio_clkgen] set_property -dict [list CONFIG.PRIM_IN_FREQ {200.000}] $sys_audio_clkgen set_property -dict [list CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {12.288}] $sys_audio_clkgen +set_property -dict [list CONFIG.USE_LOCKED {false}] $sys_audio_clkgen +set_property -dict [list CONFIG.USE_RESET {true} CONFIG.RESET_TYPE {ACTIVE_LOW}] $sys_audio_clkgen set axi_spdif_tx_core [create_bd_cell -type ip -vlnv analog.com:user:axi_spdif_tx:1.0 axi_spdif_tx_core] set_property -dict [list CONFIG.C_DMA_TYPE {1}] $axi_spdif_tx_core @@ -183,6 +185,7 @@ connect_bd_intf_net -intf_net axi_spdif_dma_req_tx [get_bd_intf_pins sys_ps7/DMA connect_bd_intf_net -intf_net axi_spdif_dma_ack_tx [get_bd_intf_pins sys_ps7/DMA0_ACK] [get_bd_intf_pins axi_spdif_tx_core/DMA_ACK] connect_bd_net -net sys_200m_clk [get_bd_pins sys_audio_clkgen/clk_in1] +connect_bd_net -net sys_100m_resetn [get_bd_pins sys_audio_clkgen/resetn] $sys_100m_resetn_source connect_bd_net -net sys_audio_clkgen_clk [get_bd_pins sys_audio_clkgen/clk_out1] [get_bd_pins axi_spdif_tx_core/spdif_data_clk] connect_bd_net -net spdif_s [get_bd_ports spdif] [get_bd_pins axi_spdif_tx_core/spdif_tx_o] diff --git a/projects/common/zed/zed_system_bd.tcl b/projects/common/zed/zed_system_bd.tcl index 014758e27..e303e5bb4 100644 --- a/projects/common/zed/zed_system_bd.tcl +++ b/projects/common/zed/zed_system_bd.tcl @@ -96,6 +96,8 @@ set_property -dict [list CONFIG.NUM_MI {1}] $axi_hdmi_interconnect set sys_audio_clkgen [create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:5.1 sys_audio_clkgen] set_property -dict [list CONFIG.PRIM_IN_FREQ {200.000}] $sys_audio_clkgen set_property -dict [list CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {12.288}] $sys_audio_clkgen +set_property -dict [list CONFIG.USE_LOCKED {false}] $sys_audio_clkgen +set_property -dict [list CONFIG.USE_RESET {true} CONFIG.RESET_TYPE {ACTIVE_LOW}] $sys_audio_clkgen set axi_spdif_tx_core [create_bd_cell -type ip -vlnv analog.com:user:axi_spdif_tx:1.0 axi_spdif_tx_core] set_property -dict [list CONFIG.C_DMA_TYPE {1}] $axi_spdif_tx_core @@ -234,6 +236,7 @@ connect_bd_intf_net -intf_net axi_spdif_dma_req_tx [get_bd_intf_pins sys_ps7/DMA connect_bd_intf_net -intf_net axi_spdif_dma_ack_tx [get_bd_intf_pins sys_ps7/DMA0_ACK] [get_bd_intf_pins axi_spdif_tx_core/DMA_ACK] connect_bd_net -net sys_200m_clk [get_bd_pins sys_audio_clkgen/clk_in1] +connect_bd_net -net sys_100m_resetn [get_bd_pins sys_audio_clkgen/resetn] $sys_100m_resetn_source connect_bd_net -net sys_audio_clkgen_clk [get_bd_pins sys_audio_clkgen/clk_out1] [get_bd_pins axi_spdif_tx_core/spdif_data_clk] connect_bd_net -net spdif_s [get_bd_ports spdif] [get_bd_pins axi_spdif_tx_core/spdif_tx_o] From 0539bc36c8715b2f1600ecfdeee23791194703a5 Mon Sep 17 00:00:00 2001 From: Lars-Peter Clausen Date: Mon, 6 Oct 2014 16:15:25 +0200 Subject: [PATCH 35/42] axi_ad9467: Fix PN sequence checker Make sure that the reference PN sequence is only incremented every two clock cycles to make sure that it matches the rate of the ADC PN sequence. Signed-off-by: Lars-Peter Clausen --- library/axi_ad9467/axi_ad9467_pnmon.v | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/library/axi_ad9467/axi_ad9467_pnmon.v b/library/axi_ad9467/axi_ad9467_pnmon.v index 81d189555..9cb9c99c6 100644 --- a/library/axi_ad9467/axi_ad9467_pnmon.v +++ b/library/axi_ad9467/axi_ad9467_pnmon.v @@ -165,10 +165,12 @@ module axi_ad9467_pnmon ( always @(posedge adc_clk) begin adc_valid_in <= ~adc_valid_in; adc_pn_data_in <= {adc_pn_data_in[15:0], ~adc_data[15], adc_data[14:0]}; - if (adc_pnseq_sel == 4'd0) begin - adc_pn_data_pn <= pn9(adc_pn_data_pn_s); - end else begin - adc_pn_data_pn <= pn23(adc_pn_data_pn_s); + if (adc_valid_in == 1'b1) begin + if (adc_pnseq_sel == 4'd0) begin + adc_pn_data_pn <= pn9(adc_pn_data_pn_s); + end else begin + adc_pn_data_pn <= pn23(adc_pn_data_pn_s); + end end end From af618073a64b1630b21f11be6c74cbf253ec6447 Mon Sep 17 00:00:00 2001 From: Michael Hennerich Date: Tue, 7 Oct 2014 09:17:24 +0200 Subject: [PATCH 36/42] projects/common/xxx/xxx_system_bd.tcl: 'Update microblaze defaults Signed-off-by: Michael Hennerich --- projects/common/ac701/ac701_system_bd.tcl | 3 ++- projects/common/kc705/kc705_system_bd.tcl | 3 ++- projects/common/kcu105/kcu105_system_bd.tcl | 7 ++++++- 3 files changed, 10 insertions(+), 3 deletions(-) mode change 100755 => 100644 projects/common/ac701/ac701_system_bd.tcl diff --git a/projects/common/ac701/ac701_system_bd.tcl b/projects/common/ac701/ac701_system_bd.tcl old mode 100755 new mode 100644 index 4592c11a7..2fcc64a70 --- a/projects/common/ac701/ac701_system_bd.tcl +++ b/projects/common/ac701/ac701_system_bd.tcl @@ -51,13 +51,14 @@ set_property -dict [list CONFIG.C_ICACHE_LINE_LEN {8}] $sys_mb set_property -dict [list CONFIG.C_ICACHE_ALWAYS_USED {1}] $sys_mb set_property -dict [list CONFIG.C_ICACHE_FORCE_TAG_LUTRAM {1}] $sys_mb set_property -dict [list CONFIG.C_USE_DCACHE {1}] $sys_mb -set_property -dict [list CONFIG.C_DCACHE_LINE_LEN {8}] $sys_mb +set_property -dict [list CONFIG.C_DCACHE_LINE_LEN {4}] $sys_mb set_property -dict [list CONFIG.C_DCACHE_ALWAYS_USED {1}] $sys_mb set_property -dict [list CONFIG.C_DCACHE_FORCE_TAG_LUTRAM {1}] $sys_mb set_property -dict [list CONFIG.C_ICACHE_HIGHADDR {0xBFFFFFFF}] $sys_mb set_property -dict [list CONFIG.C_ICACHE_BASEADDR {0x80000000}] $sys_mb set_property -dict [list CONFIG.C_DCACHE_HIGHADDR {0xBFFFFFFF}] $sys_mb set_property -dict [list CONFIG.C_DCACHE_BASEADDR {0x80000000}] $sys_mb +set_property -dict [list CONFIG.G_TEMPLATE_LIST {4}] $sys_mb # instance: microblaze - local memory & bus diff --git a/projects/common/kc705/kc705_system_bd.tcl b/projects/common/kc705/kc705_system_bd.tcl index 359a0b347..453722fe3 100644 --- a/projects/common/kc705/kc705_system_bd.tcl +++ b/projects/common/kc705/kc705_system_bd.tcl @@ -55,13 +55,14 @@ set_property -dict [list CONFIG.C_ICACHE_LINE_LEN {8}] $sys_mb set_property -dict [list CONFIG.C_ICACHE_ALWAYS_USED {1}] $sys_mb set_property -dict [list CONFIG.C_ICACHE_FORCE_TAG_LUTRAM {1}] $sys_mb set_property -dict [list CONFIG.C_USE_DCACHE {1}] $sys_mb -set_property -dict [list CONFIG.C_DCACHE_LINE_LEN {8}] $sys_mb +set_property -dict [list CONFIG.C_DCACHE_LINE_LEN {4}] $sys_mb set_property -dict [list CONFIG.C_DCACHE_ALWAYS_USED {1}] $sys_mb set_property -dict [list CONFIG.C_DCACHE_FORCE_TAG_LUTRAM {1}] $sys_mb set_property -dict [list CONFIG.C_ICACHE_HIGHADDR {0xBFFFFFFF}] $sys_mb set_property -dict [list CONFIG.C_ICACHE_BASEADDR {0x80000000}] $sys_mb set_property -dict [list CONFIG.C_DCACHE_HIGHADDR {0xBFFFFFFF}] $sys_mb set_property -dict [list CONFIG.C_DCACHE_BASEADDR {0x80000000}] $sys_mb +set_property -dict [list CONFIG.G_TEMPLATE_LIST {4}] $sys_mb # instance: microblaze - local memory & bus diff --git a/projects/common/kcu105/kcu105_system_bd.tcl b/projects/common/kcu105/kcu105_system_bd.tcl index 6da19db95..19e1747fa 100644 --- a/projects/common/kcu105/kcu105_system_bd.tcl +++ b/projects/common/kcu105/kcu105_system_bd.tcl @@ -54,9 +54,14 @@ set_property -dict [list CONFIG.C_ICACHE_LINE_LEN {8}] $sys_mb set_property -dict [list CONFIG.C_ICACHE_ALWAYS_USED {1}] $sys_mb set_property -dict [list CONFIG.C_ICACHE_FORCE_TAG_LUTRAM {1}] $sys_mb set_property -dict [list CONFIG.C_USE_DCACHE {1}] $sys_mb -set_property -dict [list CONFIG.C_DCACHE_LINE_LEN {8}] $sys_mb +set_property -dict [list CONFIG.C_DCACHE_LINE_LEN {4}] $sys_mb set_property -dict [list CONFIG.C_DCACHE_ALWAYS_USED {1}] $sys_mb set_property -dict [list CONFIG.C_DCACHE_FORCE_TAG_LUTRAM {1}] $sys_mb +set_property -dict [list CONFIG.C_ICACHE_HIGHADDR {0xBFFFFFFF}] $sys_mb +set_property -dict [list CONFIG.C_ICACHE_BASEADDR {0x80000000}] $sys_mb +set_property -dict [list CONFIG.C_DCACHE_HIGHADDR {0xBFFFFFFF}] $sys_mb +set_property -dict [list CONFIG.C_DCACHE_BASEADDR {0x80000000}] $sys_mb +set_property -dict [list CONFIG.G_TEMPLATE_LIST {4}] $sys_mb # instance: microblaze - local memory & bus From 94e93965572f8701f3717ac0a8d71f1f45eb7c00 Mon Sep 17 00:00:00 2001 From: Paul Cercueil Date: Wed, 8 Oct 2014 10:45:32 +0200 Subject: [PATCH 37/42] AD9467: Fixup swapped net names Signed-off-by: Paul Cercueil --- projects/ad9467_fmc/common/ad9467_bd.tcl | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/projects/ad9467_fmc/common/ad9467_bd.tcl b/projects/ad9467_fmc/common/ad9467_bd.tcl index 2953d038e..f51ca1bb3 100644 --- a/projects/ad9467_fmc/common/ad9467_bd.tcl +++ b/projects/ad9467_fmc/common/ad9467_bd.tcl @@ -121,8 +121,8 @@ connect_bd_net -net axi_ad9467_adc_clk_in_n [get_bd_ports adc_clk_in_p] connect_bd_net -net axi_ad9467_adc_clk_in_p [get_bd_ports adc_clk_in_n] [get_bd_pins axi_ad9467/adc_clk_in_n] connect_bd_net -net axi_ad9467_adc_data_in_n [get_bd_ports adc_data_in_n] [get_bd_pins axi_ad9467/adc_data_in_n] connect_bd_net -net axi_ad9467_adc_data_in_p [get_bd_ports adc_data_in_p] [get_bd_pins axi_ad9467/adc_data_in_p] -connect_bd_net -net axi_ad9467_adc_data_or_n [get_bd_ports adc_data_or_p] [get_bd_pins axi_ad9467/adc_or_in_p] -connect_bd_net -net axi_ad9467_adc_data_or_p [get_bd_ports adc_data_or_n] [get_bd_pins axi_ad9467/adc_or_in_n] +connect_bd_net -net axi_ad9467_adc_data_or_p [get_bd_ports adc_data_or_p] [get_bd_pins axi_ad9467/adc_or_in_p] +connect_bd_net -net axi_ad9467_adc_data_or_n [get_bd_ports adc_data_or_n] [get_bd_pins axi_ad9467/adc_or_in_n] set adc_250m_clk_source [get_bd_pins axi_ad9467/adc_clk] From 9798704cc4a047656550e2b7aeb0ed922fb71375 Mon Sep 17 00:00:00 2001 From: Paul Cercueil Date: Wed, 8 Oct 2014 10:50:09 +0200 Subject: [PATCH 38/42] DAQ1: Add missing clock line for the AD9250 ADC Signed-off-by: Paul Cercueil --- projects/daq1/common/daq1_bd.tcl | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/projects/daq1/common/daq1_bd.tcl b/projects/daq1/common/daq1_bd.tcl index 86bc6de06..704813c12 100644 --- a/projects/daq1/common/daq1_bd.tcl +++ b/projects/daq1/common/daq1_bd.tcl @@ -153,7 +153,7 @@ connect_bd_net -net axi_daq1_gt_rx_ip_sync [get_bd_pins axi_daq1_gt/rx_ip connect_bd_net -net axi_daq1_gt_rx_ip_sof [get_bd_pins axi_daq1_gt/rx_ip_sof] [get_bd_pins axi_ad9250_jesd/rx_start_of_frame] connect_bd_net -net axi_daq1_gt_rx_ip_data [get_bd_pins axi_daq1_gt/rx_ip_data] [get_bd_pins axi_ad9250_jesd/rx_tdata] connect_bd_net -net axi_daq1_gt_rx_data [get_bd_pins axi_daq1_gt/rx_data] [get_bd_pins axi_ad9250_core/rx_data] -connect_bd_net -net axi_ad9250_adc_clk [get_bd_pins axi_ad9250_core/adc_clk] [get_bd_pins axi_ad9250_dma/fifo_wr_clk] +connect_bd_net -net axi_ad9250_adc_clk [get_bd_pins axi_ad9250_core/adc_clk] [get_bd_pins axi_ad9250_dma/fifo_wr_clk] [get_bd_ports adc_clk] connect_bd_net -net axi_ad9250_adc_enable_a [get_bd_pins axi_ad9250_core/adc_enable_a] [get_bd_ports adc_enable_a] connect_bd_net -net axi_ad9250_adc_valid_a [get_bd_pins axi_ad9250_core/adc_valid_a] [get_bd_ports adc_valid_a] connect_bd_net -net axi_ad9250_adc_data_a [get_bd_pins axi_ad9250_core/adc_data_a] [get_bd_ports adc_data_a] From 8964fd33e33b1d15c1418d8eba15e93d76df1cfd Mon Sep 17 00:00:00 2001 From: Rejeesh Kutty Date: Tue, 23 Sep 2014 14:23:19 -0400 Subject: [PATCH 39/42] daq1: Clean up dma interface --- projects/daq1/common/daq1_bd.tcl | 40 ++++++++--- projects/daq1/zc706/system_top.v | 118 +++++++++++++++++++++---------- 2 files changed, 113 insertions(+), 45 deletions(-) diff --git a/projects/daq1/common/daq1_bd.tcl b/projects/daq1/common/daq1_bd.tcl index 704813c12..757783157 100644 --- a/projects/daq1/common/daq1_bd.tcl +++ b/projects/daq1/common/daq1_bd.tcl @@ -15,6 +15,16 @@ set rx_sysref [create_bd_port -dir I rx_sysref] set rx_data_p [create_bd_port -dir I -from 1 -to 0 rx_data_p] set rx_data_n [create_bd_port -dir I -from 1 -to 0 rx_data_n] +set dac_clk [create_bd_port -dir O dac_clk] +set dac_valid_0 [create_bd_port -dir O dac_valid_0] +set dac_enable_0 [create_bd_port -dir O dac_enable_0] +set dac_ddata_0 [create_bd_port -dir I -from 63 -to 0 dac_ddata_0] +set dac_valid_1 [create_bd_port -dir O dac_valid_1] +set dac_enable_1 [create_bd_port -dir O dac_enable_1] +set dac_ddata_1 [create_bd_port -dir I -from 63 -to 0 dac_ddata_1] +set dac_drd [create_bd_port -dir I dac_drd] +set dac_ddata [create_bd_port -dir O -from 127 -to 0 dac_ddata] + set adc_clk [create_bd_port -dir O adc_clk] set adc_enable_a [create_bd_port -dir O adc_enable_a] set adc_valid_a [create_bd_port -dir O adc_valid_a] @@ -22,9 +32,9 @@ set adc_data_a [create_bd_port -dir O -from 31 -to 0 adc_data_a] set adc_enable_b [create_bd_port -dir O adc_enable_b] set adc_valid_b [create_bd_port -dir O adc_valid_b] set adc_data_b [create_bd_port -dir O -from 31 -to 0 adc_data_b] -set dma_wr [create_bd_port -dir I dma_wr] -set dma_sync [create_bd_port -dir I dma_sync] -set dma_data [create_bd_port -dir I -from 63 -to 0 dma_data] +set adc_dwr [create_bd_port -dir I adc_dwr] +set adc_dsync [create_bd_port -dir I adc_dsync] +set adc_ddata [create_bd_port -dir I -from 63 -to 0 adc_ddata] set tx_ref_clk_p [create_bd_port -dir I tx_ref_clk_p] set tx_ref_clk_n [create_bd_port -dir I tx_ref_clk_n] @@ -136,6 +146,7 @@ connect_bd_net -net axi_daq1_gt_rx_sync [get_bd_pins axi_daq1_gt/rx_sy connect_bd_net -net axi_daq1_gt_rx_ext_sysref [get_bd_pins axi_daq1_gt/rx_ext_sysref] [get_bd_ports rx_sysref] # connections (adc) + connect_bd_net -net axi_daq1_gt_rx_clk [get_bd_pins axi_daq1_gt/rx_clk_g] connect_bd_net -net axi_daq1_gt_rx_clk [get_bd_pins axi_daq1_gt/rx_clk] connect_bd_net -net axi_daq1_gt_rx_clk [get_bd_pins axi_ad9250_core/rx_clk] @@ -153,18 +164,21 @@ connect_bd_net -net axi_daq1_gt_rx_ip_sync [get_bd_pins axi_daq1_gt/rx_ip connect_bd_net -net axi_daq1_gt_rx_ip_sof [get_bd_pins axi_daq1_gt/rx_ip_sof] [get_bd_pins axi_ad9250_jesd/rx_start_of_frame] connect_bd_net -net axi_daq1_gt_rx_ip_data [get_bd_pins axi_daq1_gt/rx_ip_data] [get_bd_pins axi_ad9250_jesd/rx_tdata] connect_bd_net -net axi_daq1_gt_rx_data [get_bd_pins axi_daq1_gt/rx_data] [get_bd_pins axi_ad9250_core/rx_data] -connect_bd_net -net axi_ad9250_adc_clk [get_bd_pins axi_ad9250_core/adc_clk] [get_bd_pins axi_ad9250_dma/fifo_wr_clk] [get_bd_ports adc_clk] +connect_bd_net -net axi_ad9250_adc_clk [get_bd_pins axi_ad9250_core/adc_clk] [get_bd_pins axi_ad9250_dma/fifo_wr_clk] connect_bd_net -net axi_ad9250_adc_enable_a [get_bd_pins axi_ad9250_core/adc_enable_a] [get_bd_ports adc_enable_a] connect_bd_net -net axi_ad9250_adc_valid_a [get_bd_pins axi_ad9250_core/adc_valid_a] [get_bd_ports adc_valid_a] connect_bd_net -net axi_ad9250_adc_data_a [get_bd_pins axi_ad9250_core/adc_data_a] [get_bd_ports adc_data_a] connect_bd_net -net axi_ad9250_adc_enable_b [get_bd_pins axi_ad9250_core/adc_enable_b] [get_bd_ports adc_enable_b] connect_bd_net -net axi_ad9250_adc_valid_b [get_bd_pins axi_ad9250_core/adc_valid_b] [get_bd_ports adc_valid_b] connect_bd_net -net axi_ad9250_adc_data_b [get_bd_pins axi_ad9250_core/adc_data_b] [get_bd_ports adc_data_b] -connect_bd_net -net axi_ad9250_dma_wr [get_bd_pins axi_ad9250_dma/fifo_wr_en] [get_bd_ports dma_wr] -connect_bd_net -net axi_ad9250_dma_sync [get_bd_pins axi_ad9250_dma/fifo_wr_sync] [get_bd_ports dma_sync] -connect_bd_net -net axi_ad9250_dma_data [get_bd_pins axi_ad9250_dma/fifo_wr_din] [get_bd_ports dma_data] +connect_bd_net -net axi_ad9250_adc_dovf [get_bd_pins axi_ad9250_core/adc_dovf] [get_bd_pins axi_ad9250_dma/fifo_wr_overflow] +connect_bd_net -net axi_ad9250_dma_wr [get_bd_pins axi_ad9250_dma/fifo_wr_en] [get_bd_ports adc_dwr] +connect_bd_net -net axi_ad9250_dma_sync [get_bd_pins axi_ad9250_dma/fifo_wr_sync] [get_bd_ports adc_dsync] +connect_bd_net -net axi_ad9250_dma_data [get_bd_pins axi_ad9250_dma/fifo_wr_din] [get_bd_ports adc_ddata] connect_bd_net -net axi_ad9250_dma_irq [get_bd_pins axi_ad9250_dma/irq] [get_bd_pins sys_concat_intc/In2] +connect_bd_net -net axi_ad9250_adc_clk [get_bd_ports adc_clk] + # connections (dac) connect_bd_net -net axi_ad9122_dac_clk_in_p [get_bd_pins axi_ad9122_core/dac_clk_in_p] [get_bd_ports tx_ref_clk_p] @@ -176,11 +190,19 @@ connect_bd_net -net axi_ad9122_dac_frame_out_n [get_bd_pins axi_ad9122_core/d connect_bd_net -net axi_ad9122_dac_data_out_p [get_bd_pins axi_ad9122_core/dac_data_out_p] [get_bd_ports tx_data_p] connect_bd_net -net axi_ad9122_dac_data_out_n [get_bd_pins axi_ad9122_core/dac_data_out_n] [get_bd_ports tx_data_n] connect_bd_net -net axi_ad9122_dac_div_clk [get_bd_pins axi_ad9122_core/dac_div_clk] [get_bd_pins axi_ad9122_dma/fifo_rd_clk] -connect_bd_net -net axi_ad9122_dac_drd [get_bd_pins axi_ad9122_core/dac_drd] [get_bd_pins axi_ad9122_dma/fifo_rd_en] -connect_bd_net -net axi_ad9122_dac_ddata [get_bd_pins axi_ad9122_core/dac_ddata] [get_bd_pins axi_ad9122_dma/fifo_rd_dout] +connect_bd_net -net axi_ad9122_dac_valid_0 [get_bd_pins axi_ad9122_core/dac_valid_0] [get_bd_ports dac_valid_0] +connect_bd_net -net axi_ad9122_dac_enable_0 [get_bd_pins axi_ad9122_core/dac_enable_0] [get_bd_ports dac_enable_0] +connect_bd_net -net axi_ad9122_dac_ddata_0 [get_bd_pins axi_ad9122_core/dac_ddata_0] [get_bd_ports dac_ddata_0] +connect_bd_net -net axi_ad9122_dac_valid_1 [get_bd_pins axi_ad9122_core/dac_valid_1] [get_bd_ports dac_valid_1] +connect_bd_net -net axi_ad9122_dac_enable_1 [get_bd_pins axi_ad9122_core/dac_enable_1] [get_bd_ports dac_enable_1] +connect_bd_net -net axi_ad9122_dac_ddata_1 [get_bd_pins axi_ad9122_core/dac_ddata_1] [get_bd_ports dac_ddata_1] +connect_bd_net -net axi_ad9122_dma_drd [get_bd_pins axi_ad9122_dma/fifo_rd_en] [get_bd_ports dac_drd] +connect_bd_net -net axi_ad9122_dma_ddata [get_bd_pins axi_ad9122_dma/fifo_rd_dout] [get_bd_ports dac_ddata] connect_bd_net -net axi_ad9122_dac_dunf [get_bd_pins axi_ad9122_core/dac_dunf] [get_bd_pins axi_ad9122_dma/fifo_rd_underflow] connect_bd_net -net axi_ad9122_dma_irq [get_bd_pins axi_ad9122_dma/irq] [get_bd_pins sys_concat_intc/In3] +connect_bd_net -net axi_ad9122_dac_div_clk [get_bd_ports dac_clk] + # interconnect (cpu) connect_bd_intf_net -intf_net axi_cpu_interconnect_m07_axi [get_bd_intf_pins axi_cpu_interconnect/M07_AXI] [get_bd_intf_pins axi_ad9122_dma/s_axi] diff --git a/projects/daq1/zc706/system_top.v b/projects/daq1/zc706/system_top.v index 50d3ba9fe..c5e0a20cf 100644 --- a/projects/daq1/zc706/system_top.v +++ b/projects/daq1/zc706/system_top.v @@ -180,57 +180,94 @@ module system_top ( inout spi_sdio; // internal registers - reg dma_wr = 'd0; - reg [63:0] dma_data = 'd0; + + reg dac_drd = 'd0; + reg [63:0] dac_ddata_0 = 'd0; + reg [63:0] dac_ddata_1 = 'd0; + reg adc_dwr = 'd0; + reg [63:0] adc_ddata = 'd0; // internal signals wire [39:0] gpio_i; wire [39:0] gpio_o; wire [39:0] gpio_t; - wire rx_ref_clk; wire rx_sysref; wire rx_sync; wire [ 2:0] spi_csn; - wire adc_clk; - wire adc_enable_a; wire [31:0] adc_data_a; - wire adc_enable_b; wire [31:0] adc_data_b; + wire adc_enable_a; + wire adc_enable_b; + wire dac_clk; + wire [127:0] dac_ddata; + wire dac_enable_0; + wire dac_enable_1; // pack & unpack data + always @(posedge dac_clk) begin + case ({dac_enable_1, dac_enable_0}) + 2'b11: begin + dac_drd <= 1'b1; + dac_ddata_1[63:48] <= dac_ddata[127:112]; + dac_ddata_1[47:32] <= dac_ddata[ 95: 80]; + dac_ddata_1[31:16] <= dac_ddata[ 63: 48]; + dac_ddata_1[15: 0] <= dac_ddata[ 31: 16]; + dac_ddata_0[63:48] <= dac_ddata[111: 96]; + dac_ddata_0[47:32] <= dac_ddata[ 79: 64]; + dac_ddata_0[31:16] <= dac_ddata[ 47: 32]; + dac_ddata_0[15: 0] <= dac_ddata[ 15: 0]; + end + 2'b01: begin + dac_drd <= ~dac_drd; + dac_ddata_1 <= 64'd0; + dac_ddata_0 <= (dac_drd == 1'b1) ? dac_ddata[127:64] : dac_ddata[63:0]; + end + 2'b10: begin + dac_drd <= ~dac_drd; + dac_ddata_1 <= (dac_drd == 1'b1) ? dac_ddata[127:64] : dac_ddata[63:0]; + dac_ddata_0 <= 64'd0; + end + default: begin + dac_drd <= 1'b0; + dac_ddata_1 <= 64'd0; + dac_ddata_0 <= 64'd0; + end + endcase + end + always @(posedge adc_clk) begin case ({adc_enable_b, adc_enable_a}) 2'b11: begin - dma_wr <= 1'b1; - dma_data[63:48] <= adc_data_b[31:16]; - dma_data[47:32] <= adc_data_a[31:16]; - dma_data[31:16] <= adc_data_b[15: 0]; - dma_data[15: 0] <= adc_data_a[15: 0]; + adc_dwr <= 1'b1; + adc_ddata[63:48] <= adc_data_b[31:16]; + adc_ddata[47:32] <= adc_data_a[31:16]; + adc_ddata[31:16] <= adc_data_b[15: 0]; + adc_ddata[15: 0] <= adc_data_a[15: 0]; end 2'b10: begin - dma_wr <= ~dma_wr; - dma_data[63:48] <= adc_data_b[31:16]; - dma_data[47:32] <= adc_data_b[15: 0]; - dma_data[31:16] <= dma_data[63:48]; - dma_data[15: 0] <= dma_data[47:32]; + adc_dwr <= ~adc_dwr; + adc_ddata[63:48] <= adc_data_b[31:16]; + adc_ddata[47:32] <= adc_data_b[15: 0]; + adc_ddata[31:16] <= adc_ddata[63:48]; + adc_ddata[15: 0] <= adc_ddata[47:32]; end 2'b01: begin - dma_wr <= ~dma_wr; - dma_data[63:48] <= adc_data_a[31:16]; - dma_data[47:32] <= adc_data_a[15: 0]; - dma_data[31:16] <= dma_data[63:48]; - dma_data[15: 0] <= dma_data[47:32]; + adc_dwr <= ~adc_dwr; + adc_ddata[63:48] <= adc_data_a[31:16]; + adc_ddata[47:32] <= adc_data_a[15: 0]; + adc_ddata[31:16] <= adc_ddata[63:48]; + adc_ddata[15: 0] <= adc_ddata[47:32]; end default: begin - dma_wr <= 1'b0; - dma_data[63:48] <= 16'd0; - dma_data[47:32] <= 16'd0; - dma_data[31:16] <= 16'd0; - dma_data[15: 0] <= 16'd0; + adc_dwr <= 1'b0; + adc_ddata[63:48] <= 16'd0; + adc_ddata[47:32] <= 16'd0; + adc_ddata[31:16] <= 16'd0; + adc_ddata[15: 0] <= 16'd0; end endcase end @@ -305,6 +342,25 @@ module system_top ( .GPIO_I (gpio_i), .GPIO_O (gpio_o), .GPIO_T (gpio_t), + .adc_clk (adc_clk), + .adc_data_a (adc_data_a), + .adc_data_b (adc_data_b), + .adc_ddata (adc_ddata), + .adc_dsync (1'b1), + .adc_dwr (adc_dwr), + .adc_enable_a (adc_enable_a), + .adc_enable_b (adc_enable_b), + .adc_valid_a (), + .adc_valid_b (), + .dac_clk (dac_clk), + .dac_ddata (dac_ddata), + .dac_ddata_0 (dac_ddata_0), + .dac_ddata_1 (dac_ddata_1), + .dac_drd (dac_drd), + .dac_enable_0 (dac_enable_0), + .dac_enable_1 (dac_enable_1), + .dac_valid_0 (), + .dac_valid_1 (), .hdmi_data (hdmi_data), .hdmi_data_e (hdmi_data_e), .hdmi_hsync (hdmi_hsync), @@ -317,16 +373,6 @@ module system_top ( .rx_ref_clk (rx_ref_clk), .rx_sync (rx_sync), .rx_sysref (rx_sysref), - .adc_clk (adc_clk), - .adc_data_a (adc_data_a), - .adc_data_b (adc_data_b), - .adc_enable_a (adc_enable_a), - .adc_enable_b (adc_enable_b), - .adc_valid_a (), - .adc_valid_b (), - .dma_data (dma_data), - .dma_sync (1'b1), - .dma_wr (dma_wr), .spdif (spdif), .spi_clk_i (spi_clk), .spi_clk_o (spi_clk), From cccef98e2b19b7bd6828a507c73c0f3f10053b78 Mon Sep 17 00:00:00 2001 From: Adrian Costina Date: Fri, 17 Oct 2014 15:40:16 +0300 Subject: [PATCH 40/42] util_adc_pack: removed latches --- library/util_adc_pack/util_adc_pack.v | 164 ++++++++++++-------------- 1 file changed, 78 insertions(+), 86 deletions(-) diff --git a/library/util_adc_pack/util_adc_pack.v b/library/util_adc_pack/util_adc_pack.v index 633a20727..61a3ec783 100644 --- a/library/util_adc_pack/util_adc_pack.v +++ b/library/util_adc_pack/util_adc_pack.v @@ -123,13 +123,15 @@ module util_adc_pack ( output dvalid; output dsync; + reg [(DATA_WIDTH*CHANNELS-1):0] packed_data = 0; + reg [(DATA_WIDTH*CHANNELS-1):0] temp_data_0 = 0; + reg [(DATA_WIDTH*CHANNELS-1):0] temp_data_1 = 0; + reg [3:0] enable_cnt; reg [2:0] enable_cnt_0; reg [2:0] enable_cnt_1; - reg [255:0] packed_data = 0; - reg [127:0] temp_data_0 = 0; - reg [127:0] temp_data_1 = 0; + reg [7:0] path_enabled = 0; reg [7:0] path_enabled_d1 = 0; reg [6:0] counter_0 = 0; @@ -137,7 +139,6 @@ module util_adc_pack ( reg [7:0] en2 = 0; reg [7:0] en4 = 0; reg dvalid = 0; - reg chan_valid = 0; reg [(DATA_WIDTH*CHANNELS-1):0] ddata = 0; reg [(DATA_WIDTH-1):0] chan_data_0_r; @@ -149,7 +150,10 @@ module util_adc_pack ( reg [(DATA_WIDTH-1):0] chan_data_6_r; reg [(DATA_WIDTH-1):0] chan_data_7_r; + wire chan_valid; + assign dsync = dvalid; + assign chan_valid = chan_valid_0 | chan_valid_1 | chan_valid_2 | chan_valid_3 | chan_valid_4 | chan_valid_5 | chan_valid_6 | chan_valid_7 ; always @(posedge clk) begin @@ -166,98 +170,86 @@ module util_adc_pack ( end always @(posedge clk) - begin - chan_valid <= chan_valid_0 | chan_valid_1 | chan_valid_2 | chan_valid_3 | chan_valid_4 | chan_valid_5 | chan_valid_6 | chan_valid_7 ; - chan_data_0_r <= chan_data_0; - chan_data_1_r <= chan_data_1; - chan_data_2_r <= chan_data_2; - chan_data_3_r <= chan_data_3; - chan_data_4_r <= chan_data_4; - chan_data_5_r <= chan_data_5; - chan_data_6_r <= chan_data_6; - chan_data_7_r <= chan_data_7; - end - - always @(chan_data_0_r, chan_data_1_r, chan_data_2_r, chan_data_3_r, chan_enable_0, chan_enable_1, chan_enable_2, chan_enable_3, chan_valid) begin if(chan_valid == 1'b1) begin - casex ({chan_enable_3,chan_enable_2,chan_enable_1,chan_enable_0}) - 4'bxxx1: temp_data_0[(DATA_WIDTH-1):0] = chan_data_0_r; - 4'bxx10: temp_data_0[(DATA_WIDTH-1):0] = chan_data_1_r; - 4'bx100: temp_data_0[(DATA_WIDTH-1):0] = chan_data_2_r; - 4'b1000: temp_data_0[(DATA_WIDTH-1):0] = chan_data_3_r; - default: temp_data_0 [(DATA_WIDTH-1):0] = 0; - endcase - - casex ({chan_enable_3,chan_enable_2,chan_enable_1,chan_enable_0}) - 4'bxx11: temp_data_0[2*DATA_WIDTH-1:DATA_WIDTH] = chan_data_1_r; - 4'bx110: temp_data_0[2*DATA_WIDTH-1:DATA_WIDTH] = chan_data_2_r; - 4'bx101: temp_data_0[2*DATA_WIDTH-1:DATA_WIDTH] = chan_data_2_r; - 4'b1001: temp_data_0[2*DATA_WIDTH-1:DATA_WIDTH] = chan_data_3_r; - 4'b1010: temp_data_0[2*DATA_WIDTH-1:DATA_WIDTH] = chan_data_3_r; - 4'b1100: temp_data_0[2*DATA_WIDTH-1:DATA_WIDTH] = chan_data_3_r; - default: temp_data_0[2*DATA_WIDTH-1:DATA_WIDTH] = 0; - endcase - - casex ({chan_enable_3,chan_enable_2,chan_enable_1,chan_enable_0}) - 4'bx111: temp_data_0[3*DATA_WIDTH-1:2*DATA_WIDTH] = chan_data_2_r; - 4'b1011: temp_data_0[3*DATA_WIDTH-1:2*DATA_WIDTH] = chan_data_3_r; - 4'b1101: temp_data_0[3*DATA_WIDTH-1:2*DATA_WIDTH] = chan_data_3_r; - 4'b1110: temp_data_0[3*DATA_WIDTH-1:2*DATA_WIDTH] = chan_data_3_r; - default: temp_data_0[3*DATA_WIDTH-1:2*DATA_WIDTH] = 0; - endcase - - case ({chan_enable_3,chan_enable_2,chan_enable_1,chan_enable_0}) - 4'b1111: temp_data_0[4*DATA_WIDTH-1:3*DATA_WIDTH] = chan_data_3_r; - default: temp_data_0[4*DATA_WIDTH-1:3*DATA_WIDTH] = 0; - endcase - end - else - begin - temp_data_0 = 0; + chan_data_0_r <= chan_data_0; + chan_data_1_r <= chan_data_1; + chan_data_2_r <= chan_data_2; + chan_data_3_r <= chan_data_3; + chan_data_4_r <= chan_data_4; + chan_data_5_r <= chan_data_5; + chan_data_6_r <= chan_data_6; + chan_data_7_r <= chan_data_7; end end - always @(chan_data_4_r, chan_data_5_r, chan_data_6_r, chan_data_7_r, chan_enable_4, chan_enable_5, chan_enable_6, chan_enable_7, chan_valid) + always @(chan_data_0_r, chan_data_1_r, chan_data_2_r, chan_data_3_r, chan_enable_0, chan_enable_1, chan_enable_2, chan_enable_3 ) begin - if(chan_valid == 1'b1) - begin - casex ({chan_enable_7,chan_enable_6,chan_enable_5,chan_enable_4}) - 4'bxxx1: temp_data_1[(DATA_WIDTH-1):0] = chan_data_4_r; - 4'bxx10: temp_data_1[(DATA_WIDTH-1):0] = chan_data_5_r; - 4'bx100: temp_data_1[(DATA_WIDTH-1):0] = chan_data_6_r; - 4'b1000: temp_data_1[(DATA_WIDTH-1):0] = chan_data_7_r; - default: temp_data_1[(DATA_WIDTH-1):0] = 0; - endcase + casex ({chan_enable_3,chan_enable_2,chan_enable_1,chan_enable_0}) + 4'bxxx1: temp_data_0[(DATA_WIDTH-1):0] = chan_data_0_r; + 4'bxx10: temp_data_0[(DATA_WIDTH-1):0] = chan_data_1_r; + 4'bx100: temp_data_0[(DATA_WIDTH-1):0] = chan_data_2_r; + 4'b1000: temp_data_0[(DATA_WIDTH-1):0] = chan_data_3_r; + default: temp_data_0 [(DATA_WIDTH-1):0] = 0; + endcase - casex ({chan_enable_7,chan_enable_6,chan_enable_5,chan_enable_4}) - 4'bxx11: temp_data_1[2*DATA_WIDTH-1:DATA_WIDTH] = chan_data_5_r; - 4'bx110: temp_data_1[2*DATA_WIDTH-1:DATA_WIDTH] = chan_data_6_r; - 4'bx101: temp_data_1[2*DATA_WIDTH-1:DATA_WIDTH] = chan_data_6_r; - 4'b1001: temp_data_1[2*DATA_WIDTH-1:DATA_WIDTH] = chan_data_7_r; - 4'b1010: temp_data_1[2*DATA_WIDTH-1:DATA_WIDTH] = chan_data_7_r; - 4'b1100: temp_data_1[2*DATA_WIDTH-1:DATA_WIDTH] = chan_data_7_r; - default: temp_data_1[2*DATA_WIDTH-1:DATA_WIDTH] = 0; - endcase + casex ({chan_enable_3,chan_enable_2,chan_enable_1,chan_enable_0}) + 4'bxx11: temp_data_0[2*DATA_WIDTH-1:DATA_WIDTH] = chan_data_1_r; + 4'bx110: temp_data_0[2*DATA_WIDTH-1:DATA_WIDTH] = chan_data_2_r; + 4'bx101: temp_data_0[2*DATA_WIDTH-1:DATA_WIDTH] = chan_data_2_r; + 4'b1001: temp_data_0[2*DATA_WIDTH-1:DATA_WIDTH] = chan_data_3_r; + 4'b1010: temp_data_0[2*DATA_WIDTH-1:DATA_WIDTH] = chan_data_3_r; + 4'b1100: temp_data_0[2*DATA_WIDTH-1:DATA_WIDTH] = chan_data_3_r; + default: temp_data_0[2*DATA_WIDTH-1:DATA_WIDTH] = 0; + endcase - casex ({chan_enable_7,chan_enable_6,chan_enable_5,chan_enable_4}) - 4'bx111: temp_data_1[3*DATA_WIDTH-1:2*DATA_WIDTH] = chan_data_6_r; - 4'b1011: temp_data_1[3*DATA_WIDTH-1:2*DATA_WIDTH] = chan_data_7_r; - 4'b1101: temp_data_1[3*DATA_WIDTH-1:2*DATA_WIDTH] = chan_data_7_r; - 4'b1110: temp_data_1[3*DATA_WIDTH-1:2*DATA_WIDTH] = chan_data_7_r; - default: temp_data_1[3*DATA_WIDTH-1:2*DATA_WIDTH] = 0; - endcase + casex ({chan_enable_3,chan_enable_2,chan_enable_1,chan_enable_0}) + 4'bx111: temp_data_0[3*DATA_WIDTH-1:2*DATA_WIDTH] = chan_data_2_r; + 4'b1011: temp_data_0[3*DATA_WIDTH-1:2*DATA_WIDTH] = chan_data_3_r; + 4'b1101: temp_data_0[3*DATA_WIDTH-1:2*DATA_WIDTH] = chan_data_3_r; + 4'b1110: temp_data_0[3*DATA_WIDTH-1:2*DATA_WIDTH] = chan_data_3_r; + default: temp_data_0[3*DATA_WIDTH-1:2*DATA_WIDTH] = 0; + endcase - case ({chan_enable_7,chan_enable_6,chan_enable_5,chan_enable_4}) - 4'b1111: temp_data_1[4*DATA_WIDTH-1:3*DATA_WIDTH] = chan_data_7_r; - default: temp_data_1[4*DATA_WIDTH-1:3*DATA_WIDTH] = 0; - endcase - end - else - begin - temp_data_1 = 0; - end + case ({chan_enable_3,chan_enable_2,chan_enable_1,chan_enable_0}) + 4'b1111: temp_data_0[4*DATA_WIDTH-1:3*DATA_WIDTH] = chan_data_3_r; + default: temp_data_0[4*DATA_WIDTH-1:3*DATA_WIDTH] = 0; + endcase + end + + always @(chan_data_4_r, chan_data_5_r, chan_data_6_r, chan_data_7_r, chan_enable_4, chan_enable_5, chan_enable_6, chan_enable_7) + begin + casex ({chan_enable_7,chan_enable_6,chan_enable_5,chan_enable_4}) + 4'bxxx1: temp_data_1[(DATA_WIDTH-1):0] = chan_data_4_r; + 4'bxx10: temp_data_1[(DATA_WIDTH-1):0] = chan_data_5_r; + 4'bx100: temp_data_1[(DATA_WIDTH-1):0] = chan_data_6_r; + 4'b1000: temp_data_1[(DATA_WIDTH-1):0] = chan_data_7_r; + default: temp_data_1[(DATA_WIDTH-1):0] = 0; + endcase + + casex ({chan_enable_7,chan_enable_6,chan_enable_5,chan_enable_4}) + 4'bxx11: temp_data_1[2*DATA_WIDTH-1:DATA_WIDTH] = chan_data_5_r; + 4'bx110: temp_data_1[2*DATA_WIDTH-1:DATA_WIDTH] = chan_data_6_r; + 4'bx101: temp_data_1[2*DATA_WIDTH-1:DATA_WIDTH] = chan_data_6_r; + 4'b1001: temp_data_1[2*DATA_WIDTH-1:DATA_WIDTH] = chan_data_7_r; + 4'b1010: temp_data_1[2*DATA_WIDTH-1:DATA_WIDTH] = chan_data_7_r; + 4'b1100: temp_data_1[2*DATA_WIDTH-1:DATA_WIDTH] = chan_data_7_r; + default: temp_data_1[2*DATA_WIDTH-1:DATA_WIDTH] = 0; + endcase + + casex ({chan_enable_7,chan_enable_6,chan_enable_5,chan_enable_4}) + 4'bx111: temp_data_1[3*DATA_WIDTH-1:2*DATA_WIDTH] = chan_data_6_r; + 4'b1011: temp_data_1[3*DATA_WIDTH-1:2*DATA_WIDTH] = chan_data_7_r; + 4'b1101: temp_data_1[3*DATA_WIDTH-1:2*DATA_WIDTH] = chan_data_7_r; + 4'b1110: temp_data_1[3*DATA_WIDTH-1:2*DATA_WIDTH] = chan_data_7_r; + default: temp_data_1[3*DATA_WIDTH-1:2*DATA_WIDTH] = 0; + endcase + + case ({chan_enable_7,chan_enable_6,chan_enable_5,chan_enable_4}) + 4'b1111: temp_data_1[4*DATA_WIDTH-1:3*DATA_WIDTH] = chan_data_7_r; + default: temp_data_1[4*DATA_WIDTH-1:3*DATA_WIDTH] = 0; + endcase end always @(enable_cnt) From c54fc0758f56b6b309a8b1d3303ef6907b89102a Mon Sep 17 00:00:00 2001 From: Istvan Csomortani Date: Thu, 23 Oct 2014 13:36:15 +0300 Subject: [PATCH 41/42] ad9434_fmc: Initial commit of ad9434 Picked ad9434 library and project for ZC706 from hdl/dev branch. --- library/axi_ad9434/axi_ad9434.v | 285 ++++++++++++++ library/axi_ad9434/axi_ad9434_core.v | 296 ++++++++++++++ library/axi_ad9434/axi_ad9434_if.v | 306 +++++++++++++++ library/axi_ad9434/axi_ad9434_ip.tcl | 30 ++ library/axi_ad9434/axi_ad9434_pnmon.v | 206 ++++++++++ library/common/ad_serdes_in.v | 391 +++++++++++++++++++ projects/ad9434_fmc/common/ad9434_bd.tcl | 126 ++++++ projects/ad9434_fmc/common/ad9434_spi.v | 107 +++++ projects/ad9434_fmc/zc706/system_bd.tcl | 4 + projects/ad9434_fmc/zc706/system_constr.xdc | 47 +++ projects/ad9434_fmc/zc706/system_project.tcl | 14 + projects/ad9434_fmc/zc706/system_top.v | 221 +++++++++++ 12 files changed, 2033 insertions(+) create mode 100644 library/axi_ad9434/axi_ad9434.v create mode 100644 library/axi_ad9434/axi_ad9434_core.v create mode 100644 library/axi_ad9434/axi_ad9434_if.v create mode 100644 library/axi_ad9434/axi_ad9434_ip.tcl create mode 100644 library/axi_ad9434/axi_ad9434_pnmon.v create mode 100644 library/common/ad_serdes_in.v create mode 100644 projects/ad9434_fmc/common/ad9434_bd.tcl create mode 100644 projects/ad9434_fmc/common/ad9434_spi.v create mode 100644 projects/ad9434_fmc/zc706/system_bd.tcl create mode 100644 projects/ad9434_fmc/zc706/system_constr.xdc create mode 100644 projects/ad9434_fmc/zc706/system_project.tcl create mode 100644 projects/ad9434_fmc/zc706/system_top.v diff --git a/library/axi_ad9434/axi_ad9434.v b/library/axi_ad9434/axi_ad9434.v new file mode 100644 index 000000000..9c84e0690 --- /dev/null +++ b/library/axi_ad9434/axi_ad9434.v @@ -0,0 +1,285 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2011(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR +// IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, +// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR +// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE +// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module axi_ad9434 ( + + // physical interface + adc_clk_in_p, + adc_clk_in_n, + adc_data_in_p, + adc_data_in_n, + adc_or_in_p, + adc_or_in_n, + + // delay interface + delay_clk, + + // dma interface + adc_clk, + adc_enable, + adc_valid, + adc_data, + adc_dovf, + + // axi interface + s_axi_aclk, + s_axi_aresetn, + s_axi_awvalid, + s_axi_awaddr, + s_axi_awready, + s_axi_wvalid, + s_axi_wdata, + s_axi_wstrb, + s_axi_wready, + s_axi_bvalid, + s_axi_bresp, + s_axi_bready, + s_axi_arvalid, + s_axi_araddr, + s_axi_arready, + s_axi_rvalid, + s_axi_rresp, + s_axi_rdata, + s_axi_rready); + + + // parameters + localparam SERIES7 = 0; + localparam SERIES6 = 1; + + parameter PCORE_ID = 0; + parameter PCORE_DEVTYPE = SERIES7; + parameter PCORE_IODELAY_GROUP = "dev_if_delay_group"; + parameter C_S_AXI_MIN_SIZE = 32'hffff; + + // physical interface + input adc_clk_in_p; + input adc_clk_in_n; + input [11:0] adc_data_in_p; + input [11:0] adc_data_in_n; + input adc_or_in_p; + input adc_or_in_n; + + // delay interface + input delay_clk; + + // dma interface + output adc_clk; + output adc_valid; + output adc_enable; + output [63:0] adc_data; + input adc_dovf; + + // axi interface + input s_axi_aclk; + input s_axi_aresetn; + input s_axi_awvalid; + input [31:0] s_axi_awaddr; + output s_axi_awready; + input s_axi_wvalid; + input [31:0] s_axi_wdata; + input [ 3:0] s_axi_wstrb; + output s_axi_wready; + output s_axi_bvalid; + output [ 1:0] s_axi_bresp; + input s_axi_bready; + input s_axi_arvalid; + input [31:0] s_axi_araddr; + output s_axi_arready; + output s_axi_rvalid; + output [ 1:0] s_axi_rresp; + output [31:0] s_axi_rdata; + input s_axi_rready; + + // internal clocks & resets + wire adc_rst; + wire up_rstn; + wire mmcm_rst; + wire up_clk; + wire adc_clk; + wire drp_clk; + + // internal signals + wire up_sel_s; + wire up_wr_s; + wire [13:0] up_addr_s; + wire [31:0] up_wdata_s; + wire [31:0] up_rdata_s; + wire up_ack_s; + + wire [ 1:0] up_status_pn_err_s; + wire [ 1:0] up_status_pn_oos_s; + wire [ 1:0] up_status_or_s; + wire adc_status_s; + + wire delay_rst_s; + wire delay_sel_s; + wire delay_rwn_s; + wire [ 7:0] delay_addr_s; + wire [ 4:0] delay_wdata_s; + wire [ 4:0] delay_rdata_s; + wire delay_ack_t_s; + wire delay_locked_s; + + wire drp_sel_s; + wire drp_rst_s; + wire drp_wr_s; + wire [11:0] drp_addr_s; + wire [15:0] drp_wdata_s; + wire [15:0] drp_rdata_s; + wire drp_ready_s; + wire drp_locked_s; + + wire [47:0] adc_data_if_s; + wire adc_or_if_s; + + // clock/reset assignments + assign up_clk = s_axi_aclk; + assign up_rstn = s_axi_aresetn; + assign drp_clk = up_clk; + + // single channel always enable + assign adc_enable = 1'b1; + + axi_ad9434_if #( + .PCORE_DEVTYPE(PCORE_DEVTYPE), + .PCORE_IODELAY_GROUP(PCORE_IODELAY_GROUP)) + i_if( + .adc_clk_in_p(adc_clk_in_p), + .adc_clk_in_n(adc_clk_in_n), + .adc_data_in_p(adc_data_in_p), + .adc_data_in_n(adc_data_in_n), + .adc_or_in_p(adc_or_in_p), + .adc_or_in_n(adc_or_in_n), + .adc_data(adc_data_if_s), + .adc_or(adc_or_if_s), + .adc_clk(adc_clk), + .adc_rst(adc_rst), + .adc_status(adc_status_s), + .delay_clk(delay_clk), + .delay_rst(delay_rst_s), + .delay_sel(delay_sel_s), + .delay_rwn(delay_rwn_s), + .delay_addr(delay_addr_s), + .delay_wdata(delay_wdata_s), + .delay_rdata(delay_rdata_s), + .delay_ack_t(delay_ack_t_s), + .delay_locked(delay_locked_s), + .mmcm_rst(mmcm_rst), + .drp_clk(drp_clk), + .drp_rst(drp_rst_s), + .drp_sel(drp_sel_s), + .drp_wr(drp_wr_s), + .drp_addr(drp_addr_s), + .drp_wdata(drp_wdata_s), + .drp_rdata(drp_rdata_s), + .drp_ready(drp_ready_s), + .drp_locked(drp_locked_s)); + + // common processor control + axi_ad9434_core #(.PCORE_ID(PCORE_ID)) + i_core ( + .adc_clk(adc_clk), + .adc_data(adc_data_if_s), + .adc_or(adc_or_if_s), + .mmcm_rst (mmcm_rst), + .adc_rst (adc_rst), + .adc_status (adc_status_s), + .dma_dvalid (adc_valid), + .dma_data (adc_data), + .dma_dovf (adc_dovf), + .delay_clk (delay_clk), + .delay_rst (delay_rst_s), + .delay_sel (delay_sel_s), + .delay_rwn (delay_rwn_s), + .delay_addr (delay_addr_s), + .delay_wdata (delay_wdata_s), + .delay_rdata (delay_rdata_s), + .delay_ack_t (delay_ack_t_s), + .delay_locked (delay_locked_s), + .drp_clk (drp_clk), + .drp_rst (drp_rst_s), + .drp_sel (drp_sel_s), + .drp_wr (drp_wr_s), + .drp_addr (drp_addr_s), + .drp_wdata (drp_wdata_s), + .drp_rdata (drp_rdata_s), + .drp_ready (drp_ready_s), + .drp_locked (drp_locked_s), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_sel (up_sel_s), + .up_wr (up_wr_s), + .up_addr (up_addr_s), + .up_wdata (up_wdata_s), + .up_rdata (up_rdata_s), + .up_ack (up_ack_s)); + + // up bus interface + up_axi i_up_axi ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_axi_awvalid (s_axi_awvalid), + .up_axi_awaddr (s_axi_awaddr), + .up_axi_awready (s_axi_awready), + .up_axi_wvalid (s_axi_wvalid), + .up_axi_wdata (s_axi_wdata), + .up_axi_wstrb (s_axi_wstrb), + .up_axi_wready (s_axi_wready), + .up_axi_bvalid (s_axi_bvalid), + .up_axi_bresp (s_axi_bresp), + .up_axi_bready (s_axi_bready), + .up_axi_arvalid (s_axi_arvalid), + .up_axi_araddr (s_axi_araddr), + .up_axi_arready (s_axi_arready), + .up_axi_rvalid (s_axi_rvalid), + .up_axi_rresp (s_axi_rresp), + .up_axi_rdata (s_axi_rdata), + .up_axi_rready (s_axi_rready), + .up_sel (up_sel_s), + .up_wr (up_wr_s), + .up_addr (up_addr_s), + .up_wdata (up_wdata_s), + .up_rdata (up_rdata_s), + .up_ack (up_ack_s)); + +endmodule diff --git a/library/axi_ad9434/axi_ad9434_core.v b/library/axi_ad9434/axi_ad9434_core.v new file mode 100644 index 000000000..bbe2d16f4 --- /dev/null +++ b/library/axi_ad9434/axi_ad9434_core.v @@ -0,0 +1,296 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2011(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR +// IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, +// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR +// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE +// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module axi_ad9434_core ( + + // device interface + + adc_clk, + adc_data, + adc_or, + + // dma interface + + dma_dvalid, + dma_data, + dma_dovf, + + // drp interface + + drp_clk, + drp_rst, + drp_sel, + drp_wr, + drp_addr, + drp_wdata, + drp_rdata, + drp_ready, + drp_locked, + + // delay interface + + delay_clk, + delay_rst, + delay_sel, + delay_rwn, + delay_addr, + delay_wdata, + delay_rdata, + delay_ack_t, + delay_locked, + + // processor interface + + up_rstn, + up_clk, + up_sel, + up_wr, + up_addr, + up_wdata, + up_rdata, + up_ack, + + // status and control signals + + mmcm_rst, + adc_rst, + adc_status); + + // parameters + parameter PCORE_ID = 0; + + // device interface + input adc_clk; + input [47:0] adc_data; + input adc_or; + + // dma interface + output dma_dvalid; + output [63:0] dma_data; + input dma_dovf; + + // drp interface + input drp_clk; + output drp_rst; + output drp_sel; + output drp_wr; + output [11:0] drp_addr; + output [15:0] drp_wdata; + input [15:0] drp_rdata; + input drp_ready; + input drp_locked; + + // delay interface + input delay_clk; + output delay_rst; + output delay_sel; + output delay_rwn; + output [ 7:0] delay_addr; + output [ 4:0] delay_wdata; + input [ 4:0] delay_rdata; + input delay_ack_t; + input delay_locked; + + // processor interface + input up_clk; + input up_rstn; + input up_sel; + input up_wr; + input [13:0] up_addr; + input [31:0] up_wdata; + output [31:0] up_rdata; + output up_ack; + + output mmcm_rst; + output adc_rst; + input adc_status; + + reg [31:0] up_rdata; + reg up_ack; + + // internal signals + wire up_status_pn_err_s; + wire up_status_pn_oos_s; + wire up_status_or_s; + + wire adc_dfmt_se_s; + wire adc_dfmt_type_s; + wire adc_dfmt_enable_s; + + wire [ 3:0] adc_pnseq_sel_s; + wire adc_pn_err_s; + wire adc_pn_oos_s; + + wire [31:0] up_rdata_s[0:1]; + wire up_ack_s[0:1]; + + // instantiations + axi_ad9434_pnmon i_pnmon ( + .adc_clk(adc_clk), + .adc_data(adc_data), + .adc_pnseq_sel(adc_pnseq_sel_s), + .adc_pn_err(adc_pn_err_s), + .adc_pn_oos(adc_pn_oos_s)); + + genvar n; + generate + for (n = 0; n < 4; n = n + 1) begin: g_ad_dfmt + ad_datafmt # ( + .DATA_WIDTH(12)) + i_datafmt ( + .clk(adc_clk), + .valid(1'b1), + .data(adc_data[n*12+11:n*12]), + .valid_out(dma_dvalid), + .data_out(dma_data[n*16+15:n*16]), + .dfmt_enable(adc_dfmt_enable_s), + .dfmt_type(adc_dfmt_type_s), + .dfmt_se(adc_dfmt_se_s)); + end + endgenerate + + // processor read interface + + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 0) begin + up_rdata <= 'd0; + up_ack <= 'd0; + end else begin + up_rdata <= up_rdata_s[0] | up_rdata_s[1]; + up_ack <= up_ack_s[0] | up_ack_s[1]; + end + end + + up_adc_common #( + .PCORE_ID(PCORE_ID)) + i_adc_common( + .mmcm_rst(mmcm_rst), + .adc_clk(adc_clk), + .adc_rst(adc_rst), + .adc_r1_mode(), + .adc_ddr_edgesel(), + .adc_pin_mode(), + .adc_status(adc_status), + .adc_status_ovf(dma_dovf), + .adc_status_unf(1'b0), + .adc_clk_ratio(32'd4), + .up_status_pn_err(up_status_pn_err_s), + .up_status_pn_oos(up_status_pn_oos_s), + .up_status_or(up_status_or_s), + .delay_clk(delay_clk), + .delay_rst(delay_rst), + .delay_sel(delay_sel), + .delay_rwn(delay_rwn), + .delay_addr(delay_addr), + .delay_wdata(delay_wdata), + .delay_rdata(delay_rdata), + .delay_ack_t(delay_ack_t), + .delay_locked(delay_locked), + .drp_clk(drp_clk), + .drp_rst(drp_rst), + .drp_sel(drp_sel), + .drp_wr(drp_wr), + .drp_addr(drp_addr), + .drp_wdata(drp_wdata), + .drp_rdata(drp_rdata), + .drp_ready(drp_ready), + .drp_locked(drp_locked), + .up_usr_chanmax(), + .adc_usr_chanmax(), + .up_adc_gpio_in(), + .up_adc_gpio_out(), + .up_rstn(up_rstn), + .up_clk(up_clk), + .up_sel(up_sel), + .up_wr(up_wr), + .up_addr(up_addr), + .up_wdata(up_wdata), + .up_rdata(up_rdata_s[0]), + .up_ack(up_ack_s[0])); + + up_adc_channel #( + .PCORE_ADC_CHID(0)) + i_adc_channel( + .adc_clk(adc_clk), + .adc_rst(adc_rst), + .adc_enable(), + .adc_iqcor_enb(), + .adc_dcfilt_enb(), + .adc_dfmt_se(adc_dfmt_se_s), + .adc_dfmt_type(adc_dfmt_type_s), + .adc_dfmt_enable(adc_dfmt_enable_s), + .adc_dcfilt_offset(), + .adc_dcfilt_coeff(), + .adc_iqcor_coeff_1(), + .adc_iqcor_coeff_2(), + .adc_pnseq_sel(adc_pnseq_sel_s), + .adc_data_sel(), + .adc_pn_err(adc_pn_err_s), + .adc_pn_oos(adc_pn_oos_s), + .adc_or(adc_or), + .up_adc_pn_err(up_status_pn_err_s), + .up_adc_pn_oos(up_status_pn_oos_s), + .up_adc_or(up_status_or_s), + .up_usr_datatype_be(), + .up_usr_datatype_signed(), + .up_usr_datatype_shift(), + .up_usr_datatype_total_bits(), + .up_usr_datatype_bits(), + .up_usr_decimation_m(), + .up_usr_decimation_n(), + .adc_usr_datatype_be(1'b0), + .adc_usr_datatype_signed(1'b1), + .adc_usr_datatype_shift(8'd0), + .adc_usr_datatype_total_bits(8'd16), + .adc_usr_datatype_bits(8'd16), + .adc_usr_decimation_m(16'd1), + .adc_usr_decimation_n(16'd1), + .up_rstn(up_rstn), + .up_clk(up_clk), + .up_sel(up_sel), + .up_wr(up_wr), + .up_addr(up_addr), + .up_wdata(up_wdata), + .up_rdata(up_rdata_s[1]), + .up_ack(up_ack_s[1])); + +endmodule diff --git a/library/axi_ad9434/axi_ad9434_if.v b/library/axi_ad9434/axi_ad9434_if.v new file mode 100644 index 000000000..2f77282bb --- /dev/null +++ b/library/axi_ad9434/axi_ad9434_if.v @@ -0,0 +1,306 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2011(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR +// IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, +// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR +// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE +// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module axi_ad9434_if ( + + // device interface + adc_clk_in_p, + adc_clk_in_n, + adc_data_in_p, + adc_data_in_n, + adc_or_in_p, + adc_or_in_n, + + // interface outputs + adc_data, + adc_or, + + // internl reset and clocks + adc_clk, + adc_rst, + adc_status, + + // delay interface (for IDELAY macros) + delay_clk, + delay_rst, + delay_sel, + delay_rwn, + delay_addr, + delay_wdata, + delay_rdata, + delay_ack_t, + delay_locked, + + // mmcm reset + mmcm_rst, + + // drp interface for MMCM + drp_clk, + drp_rst, + drp_sel, + drp_wr, + drp_addr, + drp_wdata, + drp_rdata, + drp_ready, + drp_locked); + + // parameters + parameter PCORE_DEVTYPE = 0; // 0 - 7Series / 1 - 6Series + parameter PCORE_IODELAY_GROUP = "dev_if_delay_group"; + + // buffer type based on the target device. + localparam PCORE_BUFTYPE = PCORE_DEVTYPE; + localparam SDR = 0; + + // adc interface (clk, data, over-range) + input adc_clk_in_p; + input adc_clk_in_n; + input [11:0] adc_data_in_p; + input [11:0] adc_data_in_n; + input adc_or_in_p; + input adc_or_in_n; + + // interface outputs + output [47:0] adc_data; + output adc_or; + + // internal reset and clocks + + output adc_clk; + input adc_rst; + output adc_status; + + // delay control signals + input delay_clk; + input delay_rst; + input delay_sel; + input delay_rwn; + input [ 7:0] delay_addr; + input [ 4:0] delay_wdata; + output [ 4:0] delay_rdata; + output delay_ack_t; + output delay_locked; + + // mmcm reset + input mmcm_rst; + + // drp interface + input drp_clk; + input drp_rst; + input drp_sel; + input drp_wr; + input [11:0] drp_addr; + input [15:0] drp_wdata; + output [15:0] drp_rdata; + output drp_ready; + output drp_locked; + + // output registers + reg [ 4:0] delay_rdata = 'b0; + reg delay_ack_t = 'b0; + + // internal registers + reg [12:0] delay_ld = 'd0; + reg adc_status = 'd0; + reg adc_status_m1 = 'd0; + + // internal signals + wire [ 4:0] delay_rdata_s[12:0]; + + wire [3:0] adc_or_s; + + wire adc_clk_in; + wire adc_div_clk; + + genvar l_inst; + + // output assignment for adc clock (1:4 of the sampling clock) + assign adc_clk = adc_div_clk; + + // delay write interface, each delay element can be individually + // addressed, and a delay value can be directly loaded (no inc/dec stuff) + always @(posedge delay_clk) begin + if ((delay_sel == 1'b1) && (delay_rwn == 1'b0)) begin + case (delay_addr) + 8'd12 : delay_ld <= 13'h1000; + 8'd11 : delay_ld <= 13'h0800; + 8'd10 : delay_ld <= 13'h0400; + 8'd9 : delay_ld <= 13'h0200; + 8'd8 : delay_ld <= 13'h0100; + 8'd7 : delay_ld <= 13'h0080; + 8'd6 : delay_ld <= 13'h0040; + 8'd5 : delay_ld <= 13'h0020; + 8'd4 : delay_ld <= 13'h0010; + 8'd3 : delay_ld <= 13'h0008; + 8'd2 : delay_ld <= 13'h0004; + 8'd1 : delay_ld <= 13'h0002; + 8'd0 : delay_ld <= 13'h0001; + default : delay_ld <= 13'h0000; + endcase + end else begin + delay_ld <= 13'h000; + end + end + + // delay read interface, a delay ack toggle is used to transfer data to the + // processor side- delay locked is independently transferred + always @(posedge delay_clk) begin + case (delay_addr) + 8'd12 : delay_rdata <= delay_rdata_s[12]; + 8'd11 : delay_rdata <= delay_rdata_s[11]; + 8'd10 : delay_rdata <= delay_rdata_s[10]; + 8'd9 : delay_rdata <= delay_rdata_s[9]; + 8'd8 : delay_rdata <= delay_rdata_s[8]; + 8'd7 : delay_rdata <= delay_rdata_s[7]; + 8'd6 : delay_rdata <= delay_rdata_s[6]; + 8'd5 : delay_rdata <= delay_rdata_s[5]; + 8'd4 : delay_rdata <= delay_rdata_s[4]; + 8'd3 : delay_rdata <= delay_rdata_s[3]; + 8'd2 : delay_rdata <= delay_rdata_s[2]; + 8'd1 : delay_rdata <= delay_rdata_s[1]; + 8'd0 : delay_rdata <= delay_rdata_s[0]; + default: delay_rdata <= 5'd0; + endcase + if (delay_sel == 1'b1) begin + delay_ack_t <= ~delay_ack_t; + end + end + + // data interface + generate + for (l_inst = 0; l_inst <= 11; l_inst = l_inst + 1) begin : g_adc_if + ad_serdes_in #( + .DEVICE_TYPE(PCORE_DEVTYPE), + .IODELAY_CTRL(0), + .IODELAY_GROUP(PCORE_IODELAY_GROUP), + .IF_TYPE(SDR), + .PARALLEL_WIDTH(4)) + i_adc_data ( + .rst(adc_rst), + .clk(adc_clk_in), + .div_clk(adc_div_clk), + .data_s0(adc_data[(3*12)+l_inst]), + .data_s1(adc_data[(2*12)+l_inst]), + .data_s2(adc_data[(1*12)+l_inst]), + .data_s3(adc_data[(0*12)+l_inst]), + .data_s4(), + .data_s5(), + .data_s6(), + .data_s7(), + .data_in_p(adc_data_in_p[l_inst]), + .data_in_n(adc_data_in_n[l_inst]), + .delay_clk(delay_clk), + .delay_rst(delay_rst), + .delay_ld(delay_ld[l_inst]), + .delay_wdata(delay_wdata), + .delay_rdata(delay_rdata_s[l_inst]), + .delay_locked()); + end + endgenerate + + // over-range interface + ad_serdes_in #( + .DEVICE_TYPE(PCORE_DEVTYPE), + .IODELAY_CTRL(1), + .IODELAY_GROUP(PCORE_IODELAY_GROUP), + .IF_TYPE(SDR), + .PARALLEL_WIDTH(4)) + i_adc_data ( + .rst(adc_rst), + .clk(adc_clk_in), + .div_clk(adc_div_clk), + .data_s0(adc_or_s[0]), + .data_s1(adc_or_s[1]), + .data_s2(adc_or_s[2]), + .data_s3(adc_or_s[3]), + .data_s4(), + .data_s5(), + .data_s6(), + .data_s7(), + .data_in_p(adc_or_in_p), + .data_in_n(adc_or_in_n), + .delay_clk(delay_clk), + .delay_rst(delay_rst), + .delay_ld(delay_ld[12]), + .delay_wdata(delay_wdata), + .delay_rdata(delay_rdata_s[12]), + .delay_locked(delay_locked)); + + // clock input buffers and MMCM + ad_serdes_clk #( + .MMCM_DEVICE_TYPE (PCORE_DEVTYPE), + .MMCM_CLKIN_PERIOD (2), + .MMCM_VCO_DIV (6), + .MMCM_VCO_MUL (12), + .MMCM_CLK0_DIV (2), + .MMCM_CLK1_DIV (8)) + i_serdes_clk ( + .mmcm_rst (mmcm_rst), + .clk_in_p (adc_clk_in_p), + .clk_in_n (adc_clk_in_n), + .clk (adc_clk_in), + .div_clk (adc_div_clk), + .drp_clk (drp_clk), + .drp_rst (drp_rst), + .drp_sel (drp_sel), + .drp_wr (drp_wr), + .drp_addr (drp_addr), + .drp_wdata (drp_wdata), + .drp_rdata (drp_rdata), + .drp_ready (drp_ready), + .drp_locked (drp_locked)); + + // adc overange + assign adc_or = adc_or_s[0] | adc_or_s[1] | adc_or_s[2] | adc_or_s[3]; + + // adc status: adc is up, if both the MMCM and DELAY blocks are up + always @(posedge adc_div_clk) begin + if(adc_rst == 1'b1) begin + adc_status_m1 <= 1'b0; + adc_status <= 1'b0; + end else begin + adc_status_m1 <= drp_locked & delay_locked; + end + end + +endmodule diff --git a/library/axi_ad9434/axi_ad9434_ip.tcl b/library/axi_ad9434/axi_ad9434_ip.tcl new file mode 100644 index 000000000..64de1d4e8 --- /dev/null +++ b/library/axi_ad9434/axi_ad9434_ip.tcl @@ -0,0 +1,30 @@ +# ip + +source ../scripts/adi_env.tcl +source $ad_hdl_dir/library/scripts/adi_ip.tcl + +adi_ip_create axi_ad9434 +adi_ip_files axi_ad9434 [list \ + "$ad_hdl_dir/library/common/ad_serdes_clk.v" \ + "$ad_hdl_dir/library/common/ad_mmcm_drp.v" \ + "$ad_hdl_dir/library/common/ad_serdes_in.v" \ + "$ad_hdl_dir/library/common/ad_datafmt.v" \ + "$ad_hdl_dir/library/common/ad_rst.v" \ + "$ad_hdl_dir/library/common/up_xfer_cntrl.v" \ + "$ad_hdl_dir/library/common/up_xfer_status.v" \ + "$ad_hdl_dir/library/common/up_clock_mon.v" \ + "$ad_hdl_dir/library/common/up_delay_cntrl.v" \ + "$ad_hdl_dir/library/common/up_drp_cntrl.v" \ + "$ad_hdl_dir/library/common/up_adc_common.v" \ + "$ad_hdl_dir/library/common/up_adc_channel.v" \ + "$ad_hdl_dir/library/common/ad_pnmon.v" \ + "$ad_hdl_dir/library/common/up_axi.v" \ + "axi_ad9434_if.v" \ + "axi_ad9434_pnmon.v" \ + "axi_ad9434_core.v" \ + "axi_ad9434.v" ] + +adi_ip_properties axi_ad9434 + +ipx::save_core [ipx::current_core] + diff --git a/library/axi_ad9434/axi_ad9434_pnmon.v b/library/axi_ad9434/axi_ad9434_pnmon.v new file mode 100644 index 000000000..a29d7c4ed --- /dev/null +++ b/library/axi_ad9434/axi_ad9434_pnmon.v @@ -0,0 +1,206 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2011(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR +// IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, +// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR +// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE +// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/1ps + +module axi_ad9434_pnmon ( + + // adc interface + adc_clk, + adc_data, + + // pn interface + adc_pnseq_sel, + adc_pn_err, + adc_pn_oos); + + // adc interface + input adc_clk; + input [47:0] adc_data; + + // pn out sync and error + input [ 3:0] adc_pnseq_sel; + output adc_pn_err; + output adc_pn_oos; + + // internal registers + reg [47:0] adc_pn_data_pn = 'd0; + + // internal signals + wire [47:0] adc_pn_data_pn_s; + + wire [47:0] adc_data_inv_s; + + // prbs pn9 function + function [47:0] pn9; + input [47:0] din; + reg [47:0] dout; + begin + dout[47] = din[8] ^ din[4]; + dout[46] = din[7] ^ din[3]; + dout[45] = din[6] ^ din[2]; + dout[44] = din[5] ^ din[1]; + dout[43] = din[4] ^ din[0]; + dout[42] = din[3] ^ din[8] ^ din[4]; + dout[41] = din[2] ^ din[7] ^ din[3]; + dout[40] = din[1] ^ din[6] ^ din[2]; + dout[39] = din[0] ^ din[5] ^ din[1]; + dout[38] = din[8] ^ din[0]; + dout[37] = din[7] ^ din[8] ^ din[4]; + dout[36] = din[6] ^ din[7] ^ din[3]; + dout[35] = din[5] ^ din[6] ^ din[2]; + dout[34] = din[4] ^ din[5] ^ din[1]; + dout[33] = din[3] ^ din[4] ^ din[0]; + dout[32] = din[2] ^ din[3] ^ din[8] ^ din[4]; + dout[31] = din[1] ^ din[2] ^ din[7] ^ din[3]; + dout[30] = din[0] ^ din[1] ^ din[6] ^ din[2]; + dout[29] = din[8] ^ din[0] ^ din[4] ^ din[5] ^ din[1]; + dout[28] = din[7] ^ din[8] ^ din[3] ^ din[0]; + dout[27] = din[6] ^ din[7] ^ din[2] ^ din[8] ^ din[4]; + dout[26] = din[5] ^ din[6] ^ din[1] ^ din[7] ^ din[3]; + dout[25] = din[4] ^ din[5] ^ din[0] ^ din[6] ^ din[2]; + dout[24] = din[3] ^ din[8] ^ din[5] ^ din[1]; + dout[23] = din[2] ^ din[4] ^ din[7] ^ din[0]; + dout[22] = din[1] ^ din[3] ^ din[6] ^ din[8] ^ din[4]; + dout[21] = din[0] ^ din[2] ^ din[5] ^ din[7] ^ din[3]; + dout[20] = din[8] ^ din[1] ^ din[6] ^ din[2]; + dout[19] = din[7] ^ din[0] ^ din[5] ^ din[1]; + dout[18] = din[6] ^ din[8] ^ din[0]; + dout[17] = din[5] ^ din[7] ^ din[8] ^ din[4]; + dout[16] = din[4] ^ din[6] ^ din[7] ^ din[3]; + dout[15] = din[3] ^ din[5] ^ din[6] ^ din[2]; + dout[14] = din[2] ^ din[4] ^ din[5] ^ din[1]; + dout[13] = din[1] ^ din[3] ^ din[4] ^ din[0]; + dout[12] = din[0] ^ din[2] ^ din[3] ^ din[8] ^ din[4]; + dout[11] = din[8] ^ din[1] ^ din[2] ^ din[4] ^ din[7] ^ din[3]; + dout[10] = din[7] ^ din[0] ^ din[1] ^ din[3] ^ din[6] ^ din[2]; + dout[9] = din[6] ^ din[8] ^ din[0] ^ din[2] ^ din[4] ^ din[5] ^ din[1]; + dout[8] = din[5] ^ din[7] ^ din[8] ^ din[1] ^ din[3] ^ din[0]; + dout[7] = din[6] ^ din[7] ^ din[0] ^ din[2] ^ din[8]; + dout[6] = din[5] ^ din[6] ^ din[8] ^ din[1] ^ din[4] ^ din[7]; + dout[5] = din[4] ^ din[5] ^ din[7] ^ din[0] ^ din[3] ^ din[6]; + dout[4] = din[3] ^ din[6] ^ din[8] ^ din[2] ^ din[5]; + dout[3] = din[2] ^ din[4] ^ din[5] ^ din[7] ^ din[1]; + dout[2] = din[1] ^ din[4] ^ din[3] ^ din[6] ^ din[0]; + dout[1] = din[0] ^ din[3] ^ din[2] ^ din[5] ^ din[8] ^ din[4]; + dout[0] = din[8] ^ din[2] ^ din[1] ^ din[7] ^ din[3]; + pn9 = dout; + end + endfunction + + // prbs pn23 function + function [47:0] pn23; + input [47:0] din; + reg [47:0] dout; + begin + dout[47] = din[22] ^ din[17]; + dout[46] = din[21] ^ din[16]; + dout[45] = din[20] ^ din[15]; + dout[44] = din[19] ^ din[14]; + dout[43] = din[18] ^ din[13]; + dout[42] = din[17] ^ din[12]; + dout[41] = din[16] ^ din[11]; + dout[40] = din[15] ^ din[10]; + dout[39] = din[14] ^ din[9]; + dout[38] = din[13] ^ din[8]; + dout[37] = din[12] ^ din[7]; + dout[36] = din[11] ^ din[6]; + dout[35] = din[10] ^ din[5]; + dout[34] = din[9] ^ din[4]; + dout[33] = din[8] ^ din[3]; + dout[32] = din[7] ^ din[2]; + dout[31] = din[6] ^ din[1]; + dout[30] = din[5] ^ din[0]; + dout[29] = din[4] ^ din[22] ^ din[17]; + dout[28] = din[3] ^ din[21] ^ din[16]; + dout[27] = din[2] ^ din[20] ^ din[15]; + dout[26] = din[1] ^ din[19] ^ din[14]; + dout[25] = din[0] ^ din[18] ^ din[13]; + dout[24] = din[22] ^ din[12]; + dout[23] = din[21] ^ din[11]; + dout[22] = din[20] ^ din[10]; + dout[21] = din[19] ^ din[9]; + dout[20] = din[18] ^ din[8]; + dout[19] = din[17] ^ din[7]; + dout[18] = din[16] ^ din[6]; + dout[17] = din[15] ^ din[5]; + dout[16] = din[14] ^ din[4]; + dout[15] = din[13] ^ din[3]; + dout[14] = din[12] ^ din[2]; + dout[13] = din[11] ^ din[1]; + dout[12] = din[10] ^ din[0]; + dout[11] = din[9] ^ din[22] ^ din[17]; + dout[10] = din[8] ^ din[21] ^ din[16]; + dout[9] = din[7] ^ din[20] ^ din[15]; + dout[8] = din[6] ^ din[19] ^ din[14]; + dout[7] = din[5] ^ din[18] ^ din[13]; + dout[6] = din[4] ^ din[17] ^ din[12]; + dout[5] = din[3] ^ din[16] ^ din[11]; + dout[4] = din[2] ^ din[15] ^ din[10]; + dout[3] = din[1] ^ din[14] ^ din[9]; + dout[2] = din[0] ^ din[13] ^ din[8]; + dout[1] = din[22] ^ din[12] ^ din[17] ^ din[7]; + dout[0] = din[21] ^ din[11] ^ din[16] ^ din[6]; + pn23 = dout; + end + endfunction + + // pn sequence selection + assign adc_data_inv_s = {adc_data[11:0], adc_data[23:12], adc_data[35:24], adc_data[47:36]}; + assign adc_pn_data_pn_s = (adc_pn_oos == 1'b1) ? adc_data_inv_s : adc_pn_data_pn; + + always @(posedge adc_clk) begin + if(adc_pnseq_sel == 4'b0) begin + adc_pn_data_pn <= pn9(adc_pn_data_pn_s); + end else begin + adc_pn_data_pn <= pn23(adc_pn_data_pn_s); + end + end + + // pn oos & pn err + ad_pnmon #(.DATA_WIDTH(48)) i_pnmon ( + .adc_clk (adc_clk), + .adc_valid_in (1'b1), + .adc_data_in (adc_data_inv_s), + .adc_data_pn (adc_pn_data_pn), + .adc_pn_oos (adc_pn_oos), + .adc_pn_err (adc_pn_err)); + +endmodule diff --git a/library/common/ad_serdes_in.v b/library/common/ad_serdes_in.v new file mode 100644 index 000000000..dc6ec6113 --- /dev/null +++ b/library/common/ad_serdes_in.v @@ -0,0 +1,391 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2011(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR +// IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, +// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, +// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR +// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE +// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** +// *************************************************************************** +// *************************************************************************** +`timescale 1ps/1ps + +module ad_serdes_in ( + + // reset and clocks + + rst, + clk, + div_clk, + + // data interface + + data_s0, + data_s1, + data_s2, + data_s3, + data_s4, + data_s5, + data_s6, + data_s7, + data_in_p, + data_in_n, + + // delay interface + + delay_clk, + delay_rst, + delay_ld, + delay_wdata, + delay_rdata, + delay_locked); + + // parameters + + parameter DEVICE_TYPE = 0; + parameter IODELAY_CTRL = 0; + parameter IODELAY_GROUP = "dev_if_delay_group"; + // SDR = 0 / DDR = 1 + parameter IF_TYPE = 0; + // serialization factor + parameter PARALLEL_WIDTH = 8; + + localparam DEVICE_6SERIES = 1; + localparam DEVICE_7SERIES = 0; + localparam SDR = 0; + localparam DDR = 1; + + // reset and clocks + + input rst; + input clk; + input div_clk; + + // data interface + + output data_s0; + output data_s1; + output data_s2; + output data_s3; + output data_s4; + output data_s5; + output data_s6; + output data_s7; + input data_in_p; + input data_in_n; + + // delay interface + + input delay_clk; + input delay_rst; + input delay_ld; + input [ 4:0] delay_wdata; + output [ 4:0] delay_rdata; + output delay_locked; + + // internal signals + + wire data_in_ibuf_s; + wire data_in_idelay_s; + wire data_shift1_s; + wire data_shift2_s; + + // delay controller + + generate + if (IODELAY_CTRL == 1) begin + (* IODELAY_GROUP = IODELAY_GROUP *) + IDELAYCTRL i_delay_ctrl ( + .RST (delay_rst), + .REFCLK (delay_clk), + .RDY (delay_locked)); + end else begin + assign delay_locked = 1'b1; + end + endgenerate + + // received data interface: ibuf -> idelay -> iserdes + + IBUFDS i_ibuf ( + .O(data_in_ibuf_s), + .I(data_in_p), + .IB(data_in_n) + ); + + if(DEVICE_TYPE == DEVICE_7SERIES) begin + (* IODELAY_GROUP = IODELAY_GROUP *) + + IDELAYE2 #( + .CINVCTRL_SEL ("FALSE"), + .DELAY_SRC ("IDATAIN"), + .HIGH_PERFORMANCE_MODE ("FALSE"), + .IDELAY_TYPE ("VAR_LOAD"), + .IDELAY_VALUE (0), + .REFCLK_FREQUENCY (200.0), + .PIPE_SEL ("FALSE"), + .SIGNAL_PATTERN ("DATA")) + i_rx_data_idelay ( + .CE (1'b0), + .INC (1'b0), + .DATAIN (1'b0), + .LDPIPEEN (1'b0), + .CINVCTRL (1'b0), + .REGRST (1'b0), + .C (delay_clk), + .IDATAIN (data_in_ibuf_s), + .DATAOUT (data_in_idelay_s), + .LD (delay_ld), + .CNTVALUEIN (delay_wdata), + .CNTVALUEOUT (delay_rdata)); + + // Note: The first sample in time will be data_s7, the last data_s0! + if(IF_TYPE == SDR) begin + ISERDESE2 #( + .DATA_RATE("SDR"), + .DATA_WIDTH(PARALLEL_WIDTH), + .DYN_CLKDIV_INV_EN("FALSE"), + .DYN_CLK_INV_EN("FALSE"), + .INIT_Q1(1'b0), + .INIT_Q2(1'b0), + .INIT_Q3(1'b0), + .INIT_Q4(1'b0), + .INTERFACE_TYPE("NETWORKING"), + .IOBDELAY("IFD"), + .NUM_CE(2), + .OFB_USED("FALSE"), + .SERDES_MODE("MASTER"), + .SRVAL_Q1(1'b0), + .SRVAL_Q2(1'b0), + .SRVAL_Q3(1'b0), + .SRVAL_Q4(1'b0)) + ISERDESE2_inst ( + .O(), + .Q1(data_s0), + .Q2(data_s1), + .Q3(data_s2), + .Q4(data_s3), + .Q5(data_s4), + .Q6(data_s5), + .Q7(data_s6), + .Q8(data_s7), + .SHIFTOUT1(), + .SHIFTOUT2(), + .BITSLIP(1'b0), + .CE1(1'b1), + .CE2(1'b1), + .CLKDIVP(1'b0), + .CLK(clk), + .CLKB(~clk), + .CLKDIV(div_clk), + .OCLK(1'b0), + .DYNCLKDIVSEL(1'b0), + .DYNCLKSEL(1'b0), + .D(1'b0), + .DDLY(data_in_idelay_s), + .OFB(1'b0), + .OCLKB(1'b0), + .RST(rst), + .SHIFTIN1(1'b0), + .SHIFTIN2(1'b0) + ); + end else begin + + ISERDESE2 #( + .DATA_RATE("DDR"), + .DATA_WIDTH(PARALLEL_WIDTH), + .DYN_CLKDIV_INV_EN("FALSE"), + .DYN_CLK_INV_EN("FALSE"), + .INIT_Q1(1'b0), + .INIT_Q2(1'b0), + .INIT_Q3(1'b0), + .INIT_Q4(1'b0), + .INTERFACE_TYPE("NETWORKING"), + .IOBDELAY("IFD"), + .NUM_CE(2), + .OFB_USED("FALSE"), + .SERDES_MODE("MASTER"), + .SRVAL_Q1(1'b0), + .SRVAL_Q2(1'b0), + .SRVAL_Q3(1'b0), + .SRVAL_Q4(1'b0)) + ISERDESE2_inst ( + .O(), + .Q1(data_s0), + .Q2(data_s1), + .Q3(data_s2), + .Q4(data_s3), + .Q5(data_s4), + .Q6(data_s5), + .Q7(data_s6), + .Q8(data_s7), + .SHIFTOUT1(), + .SHIFTOUT2(), + .BITSLIP(1'b0), + .CE1(1'b1), + .CE2(1'b1), + .CLKDIVP(1'b0), + .CLK(clk), + .CLKB(~clk), + .CLKDIV(div_clk), + .OCLK(1'b0), + .DYNCLKDIVSEL(1'b0), + .DYNCLKSEL(1'b0), + .D(1'b0), + .DDLY(data_in_idelay_s), + .OFB(1'b0), + .OCLKB(1'b0), + .RST(rst), + .SHIFTIN1(1'b0), + .SHIFTIN2(1'b0) + ); + end + end + + if(DEVICE_TYPE == DEVICE_6SERIES) begin + (* IODELAY_GROUP = IODELAY_GROUP *) + IODELAYE1 #( + .CINVCTRL_SEL ("FALSE"), + .DELAY_SRC ("I"), + .HIGH_PERFORMANCE_MODE ("TRUE"), + .IDELAY_TYPE ("VAR_LOADABLE"), + .IDELAY_VALUE (0), + .ODELAY_TYPE ("FIXED"), + .ODELAY_VALUE (0), + .REFCLK_FREQUENCY (200.0), + .SIGNAL_PATTERN ("DATA")) + i_rx_data_idelay ( + .T (1'b1), + .CE (1'b0), + .INC (1'b0), + .CLKIN (1'b0), + .DATAIN (1'b0), + .ODATAIN (1'b0), + .CINVCTRL (1'b0), + .C (delay_clk), + .IDATAIN (data_in_ibuf_s), + .DATAOUT (data_in_idelay_s), + .RST (delay_ld), + .CNTVALUEIN (delay_wdata), + .CNTVALUEOUT (delay_rdata)); + + ISERDESE1 #( + .DATA_RATE("DDR"), + .DATA_WIDTH(PARALLEL_WIDTH), + .DYN_CLKDIV_INV_EN("FALSE"), + .DYN_CLK_INV_EN("FALSE"), + .INIT_Q1(1'b0), + .INIT_Q2(1'b0), + .INIT_Q3(1'b0), + .INIT_Q4(1'b0), + .INTERFACE_TYPE("NETWORKING"), + .IOBDELAY("NONE"), + .NUM_CE(1), + .OFB_USED("FALSE"), + .SERDES_MODE("MASTER"), + .SRVAL_Q1(1'b0), + .SRVAL_Q2(1'b0), + .SRVAL_Q3(1'b0), + .SRVAL_Q4(1'b0)) + i_serdes_m ( + .O(), + .Q1(data_s0), + .Q2(data_s1), + .Q3(data_s2), + .Q4(data_s3), + .Q5(data_s4), + .Q6(data_s5), + .SHIFTOUT1(data_shift1_s), + .SHIFTOUT2(data_shift2_s), + .BITSLIP(1'b0), + .CE1(1'b1), + .CE2(1'b1), + .CLK(clk), + .CLKB(1'b0), + .CLKDIV(div_clk), + .OCLK(1'b0), + .DYNCLKDIVSEL(1'b0), + .DYNCLKSEL(1'b0), + .D(data_in_idelay_s), + .DDLY(1'b0), + .OFB(1'b0), + .RST(rst), + .SHIFTIN1(1'b0), + .SHIFTIN2(1'b0) + ); + + ISERDESE1 #( + .DATA_RATE("DDR"), + .DATA_WIDTH(PARALLEL_WIDTH), + .DYN_CLKDIV_INV_EN("FALSE"), + .DYN_CLK_INV_EN("FALSE"), + .INIT_Q1(1'b0), + .INIT_Q2(1'b0), + .INIT_Q3(1'b0), + .INIT_Q4(1'b0), + .INTERFACE_TYPE("NETWORKING"), + .IOBDELAY("NONE"), + .NUM_CE(1), + .OFB_USED("FALSE"), + .SERDES_MODE("SLAVE"), + .SRVAL_Q1(1'b0), + .SRVAL_Q2(1'b0), + .SRVAL_Q3(1'b0), + .SRVAL_Q4(1'b0)) + i_serdes_s ( + .O(), + .Q1(), + .Q2(), + .Q3(data_s6), + .Q4(data_s7), + .Q5(), + .Q6(), + .SHIFTOUT1(), + .SHIFTOUT2(), + .BITSLIP(1'b0), + .CE1(1'b1), + .CE2(1'b1), + .CLK(clk), + .CLKB(1'b0), + .CLKDIV(div_clk), + .OCLK(1'b0), + .DYNCLKDIVSEL(1'b0), + .DYNCLKSEL(1'b0), + .D(1'b0), + .DDLY(1'b0), + .OFB(1'b0), + .RST(rst), + .SHIFTIN1(data_shift1_s), + .SHIFTIN2(data_shift2_s)); + end + +endmodule + diff --git a/projects/ad9434_fmc/common/ad9434_bd.tcl b/projects/ad9434_fmc/common/ad9434_bd.tcl new file mode 100644 index 000000000..9940eca4d --- /dev/null +++ b/projects/ad9434_fmc/common/ad9434_bd.tcl @@ -0,0 +1,126 @@ +# ad9434 interface + +set adc_clk_p [create_bd_port -dir I adc_clk_p] +set adc_clk_n [create_bd_port -dir I adc_clk_n] +set adc_data_p [create_bd_port -dir I -from 11 -to 0 adc_data_p] +set adc_data_n [create_bd_port -dir I -from 11 -to 0 adc_data_n] +set adc_or_p [create_bd_port -dir I adc_or_p] +set adc_or_n [create_bd_port -dir I adc_or_n] + +# spi interface + +set spi_clk_i [create_bd_port -dir I spi_clk_i] +set spi_clk_o [create_bd_port -dir O spi_clk_o] +set spi_csn_i [create_bd_port -dir I spi_csn_i] +set spi_csn_adc_o [create_bd_port -dir O spi_csn_adc_o] +set spi_csn_clk_o [create_bd_port -dir O spi_csn_clk_o] +set spi_mosi_i [create_bd_port -dir I spi_mosi_i] +set spi_mosi_o [create_bd_port -dir O spi_mosi_o] +set spi_miso_i [create_bd_port -dir I spi_miso_i] + +# ad9434 + +set axi_ad9434 [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9434:1.0 axi_ad9434] + +# dma for ad9434 + +set axi_ad9434_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad9434_dma] +set_property -dict [list CONFIG.C_DMA_TYPE_SRC {2}] $axi_ad9434_dma +set_property -dict [list CONFIG.C_DMA_TYPE_DEST {0}] $axi_ad9434_dma +set_property -dict [list CONFIG.C_CYCLIC {0}] $axi_ad9434_dma +set_property -dict [list CONFIG.C_SYNC_TRANSFER_START {0}] $axi_ad9434_dma +set_property -dict [list CONFIG.C_AXI_SLICE_SRC {0}] $axi_ad9434_dma +set_property -dict [list CONFIG.C_AXI_SLICE_DEST {0}] $axi_ad9434_dma +set_property -dict [list CONFIG.C_CLKS_ASYNC_DEST_REQ {1}] $axi_ad9434_dma +set_property -dict [list CONFIG.C_CLKS_ASYNC_SRC_DEST {1}] $axi_ad9434_dma +set_property -dict [list CONFIG.C_CLKS_ASYNC_REQ_SRC {1}] $axi_ad9434_dma +set_property -dict [list CONFIG.C_2D_TRANSFER {0}] $axi_ad9434_dma +set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_SRC {64}] $axi_ad9434_dma + +# dma interconnect + +set axi_ad9434_dma_interconnect [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_ad9434_dma_interconnect] +set_property -dict [list CONFIG.NUM_MI {1}] $axi_ad9434_dma_interconnect + +# additions to default configuration + +set_property -dict [list CONFIG.NUM_MI {9}] $axi_cpu_interconnect + +set_property -dict [list CONFIG.PCW_USE_S_AXI_HP1 {1}] $sys_ps7 +set_property -dict [list CONFIG.PCW_EN_CLK2_PORT {1}] $sys_ps7 +set_property -dict [list CONFIG.PCW_EN_RST2_PORT {1}] $sys_ps7 +set_property -dict [list CONFIG.PCW_FPGA2_PERIPHERAL_FREQMHZ {200.0}] $sys_ps7 +set_property -dict [list CONFIG.PCW_SPI0_PERIPHERAL_ENABLE {1}] $sys_ps7 +set_property -dict [list CONFIG.PCW_SPI0_SPI0_IO {EMIO}] $sys_ps7 +set_property -dict [list CONFIG.PCW_GPIO_EMIO_GPIO_IO {15}] $sys_ps7 + +set_property LEFT 14 [get_bd_ports GPIO_I] +set_property LEFT 14 [get_bd_ports GPIO_O] +set_property LEFT 14 [get_bd_ports GPIO_T] + +# spi connections + +connect_bd_net -net spi_csn_i [get_bd_ports spi_csn_i] [get_bd_pins sys_ps7/SPI0_SS_I] +connect_bd_net -net spi_csn_adc_o [get_bd_ports spi_csn_adc_o] [get_bd_pins sys_ps7/SPI0_SS_O] +connect_bd_net -net spi_csn_clk_o [get_bd_ports spi_csn_clk_o] [get_bd_pins sys_ps7/SPI0_SS1_O] +connect_bd_net -net spi_clk_i [get_bd_ports spi_clk_i] [get_bd_pins sys_ps7/SPI0_SCLK_I] +connect_bd_net -net spi_clk_o [get_bd_ports spi_clk_o] [get_bd_pins sys_ps7/SPI0_SCLK_O] +connect_bd_net -net spi_mosi_i [get_bd_ports spi_mosi_i] [get_bd_pins sys_ps7/SPI0_MOSI_I] +connect_bd_net -net spi_mosi_o [get_bd_ports spi_mosi_o] [get_bd_pins sys_ps7/SPI0_MOSI_O] +connect_bd_net -net spi_miso_i [get_bd_ports spi_miso_i] [get_bd_pins sys_ps7/SPI0_MISO_I] + +# ad9434 connections + +connect_bd_net -net sys_200m_clk [get_bd_pins axi_ad9434/delay_clk] +connect_bd_net -net axi_ad9434_clk [get_bd_pins axi_ad9434/adc_clk] +connect_bd_net -net axi_ad9434_clk [get_bd_pins axi_ad9434_dma/fifo_wr_clk] + +connect_bd_net -net axi_ad9434_clk_in_p [get_bd_ports adc_clk_p] [get_bd_pins axi_ad9434/adc_clk_in_p] +connect_bd_net -net axi_ad9434_clk_in_n [get_bd_ports adc_clk_n] [get_bd_pins axi_ad9434/adc_clk_in_n] +connect_bd_net -net axi_ad9434_data_in_p [get_bd_ports adc_data_p] [get_bd_pins axi_ad9434/adc_data_in_p] +connect_bd_net -net axi_ad9434_data_in_n [get_bd_ports adc_data_n] [get_bd_pins axi_ad9434/adc_data_in_n] +connect_bd_net -net axi_ad9434_or_in_p [get_bd_ports adc_or_p] [get_bd_pins axi_ad9434/adc_or_in_p] +connect_bd_net -net axi_ad9434_or_in_n [get_bd_ports adc_or_n] [get_bd_pins axi_ad9434/adc_or_in_n] + +connect_bd_net -net axi_ad9434_denable [get_bd_pins axi_ad9434/adc_valid] [get_bd_pins axi_ad9434_dma/fifo_wr_en] +connect_bd_net -net axi_ad9434_data [get_bd_pins axi_ad9434/adc_data] [get_bd_pins axi_ad9434_dma/fifo_wr_din] +connect_bd_net -net axi_ad9434_ovf [get_bd_pins axi_ad9434/adc_dovf] [get_bd_pins axi_ad9434_dma/fifo_wr_overflow] + +connect_bd_net -net axi_ad9434_dma_irq [get_bd_pins axi_ad9434_dma/irq] [get_bd_pins sys_concat_intc/In2] + +# cpu interconnect + +connect_bd_intf_net -intf_net axi_cpu_interconnect_m07_axi [get_bd_intf_pins axi_cpu_interconnect/M07_AXI] [get_bd_intf_pins axi_ad9434/s_axi] +connect_bd_intf_net -intf_net axi_cpu_interconnect_m08_axi [get_bd_intf_pins axi_cpu_interconnect/M08_AXI] [get_bd_intf_pins axi_ad9434_dma/s_axi] +connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M07_ACLK] $sys_100m_clk_source +connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M08_ACLK] $sys_100m_clk_source +connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9434/s_axi_aclk] +connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9434_dma/s_axi_aclk] +connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M07_ARESETN] $sys_100m_resetn_source +connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M08_ARESETN] $sys_100m_resetn_source +connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9434/s_axi_aresetn] +connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9434_dma/s_axi_aresetn] + +# memory inteconnect + +set dma_clk_source [get_bd_pins sys_ps7/FCLK_CLK2] +connect_bd_net -net dma_clk $dma_clk_source + +connect_bd_intf_net -intf_net axi_ad9434_dma_interconnect_s00_axi [get_bd_intf_pins axi_ad9434_dma_interconnect/S00_AXI] [get_bd_intf_pins axi_ad9434_dma/m_dest_axi] +connect_bd_intf_net -intf_net axi_ad9434_dma_interconnect_m00_axi [get_bd_intf_pins axi_ad9434_dma_interconnect/M00_AXI] [get_bd_intf_pins sys_ps7/S_AXI_HP1] +connect_bd_net -net dma_clk [get_bd_pins axi_ad9434_dma_interconnect/ACLK] $dma_clk_source +connect_bd_net -net dma_clk [get_bd_pins axi_ad9434_dma_interconnect/M00_ACLK] $dma_clk_source +connect_bd_net -net dma_clk [get_bd_pins axi_ad9434_dma_interconnect/S00_ACLK] $dma_clk_source +connect_bd_net -net dma_clk [get_bd_pins axi_ad9434_dma/m_dest_axi_aclk] +connect_bd_net -net dma_clk [get_bd_pins sys_ps7/S_AXI_HP1_ACLK] +connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9434_dma_interconnect/ARESETN] $sys_100m_resetn_source +connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9434_dma_interconnect/M00_ARESETN] $sys_100m_resetn_source +connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9434_dma_interconnect/S00_ARESETN] $sys_100m_resetn_source +connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9434_dma/m_dest_axi_aresetn] $sys_100m_resetn_source + +# address map + +create_bd_addr_seg -range 0x00010000 -offset 0x44A00000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad9434/s_axi/axi_lite] SEG_data_ad9434_core +create_bd_addr_seg -range 0x00010000 -offset 0x44A30000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad9434_dma/s_axi/axi_lite] SEG_data_ad9434_dma +create_bd_addr_seg -range $sys_mem_size -offset 0x00000000 [get_bd_addr_spaces axi_ad9434_dma/m_dest_axi] [get_bd_addr_segs sys_ps7/S_AXI_HP1/HP1_DDR_LOWOCM] SEG_sys_ps7_hp1_ddr_lowocm + diff --git a/projects/ad9434_fmc/common/ad9434_spi.v b/projects/ad9434_fmc/common/ad9434_spi.v new file mode 100644 index 000000000..9b419b4b6 --- /dev/null +++ b/projects/ad9434_fmc/common/ad9434_spi.v @@ -0,0 +1,107 @@ + +// *************************************************************************** +// *************************************************************************** +// Copyright 2011(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module ad9434_spi ( + + spi_csn, + spi_clk, + spi_mosi, + spi_miso, + + spi_sdio); + + // 4 wire + + input [ 1:0] spi_csn; + input spi_clk; + input spi_mosi; + output spi_miso; + + // 3 wire + + inout spi_sdio; + + // internal registers + + reg [ 5:0] spi_count = 'd0; + reg spi_rd_wr_n = 'd0; + reg spi_enable = 'd0; + + // internal signals + + wire spi_csn_s; + wire spi_enable_s; + + // check on rising edge and change on falling edge + + assign spi_csn_s = & spi_csn; + assign spi_enable_s = spi_enable & ~spi_csn_s; + + always @(posedge spi_clk or posedge spi_csn_s) begin + if (spi_csn_s == 1'b1) begin + spi_count <= 6'd0; + spi_rd_wr_n <= 1'd0; + end else begin + spi_count <= spi_count + 1'b1; + if (spi_count == 6'd0) begin + spi_rd_wr_n <= spi_mosi; + end + end + end + + always @(negedge spi_clk or posedge spi_csn_s) begin + if (spi_csn_s == 1'b1) begin + spi_enable <= 1'b0; + end else begin + if (spi_count == 6'd16) begin + spi_enable <= spi_rd_wr_n; + end + end + end + + // io butter + + IOBUF i_iobuf_sdio ( + .T (spi_enable_s), + .I (spi_mosi), + .O (spi_miso), + .IO (spi_sdio)); + +endmodule diff --git a/projects/ad9434_fmc/zc706/system_bd.tcl b/projects/ad9434_fmc/zc706/system_bd.tcl new file mode 100644 index 000000000..a09718d62 --- /dev/null +++ b/projects/ad9434_fmc/zc706/system_bd.tcl @@ -0,0 +1,4 @@ + +source $ad_hdl_dir/projects/common/zc706/zc706_system_bd.tcl +source ../common/ad9434_bd.tcl + diff --git a/projects/ad9434_fmc/zc706/system_constr.xdc b/projects/ad9434_fmc/zc706/system_constr.xdc new file mode 100644 index 000000000..c8b7fe26a --- /dev/null +++ b/projects/ad9434_fmc/zc706/system_constr.xdc @@ -0,0 +1,47 @@ +# ad9434 + +set_property -dict {PACKAGE_PIN AE13 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_clk_p] ; ## G6 FMC_LPC_LA00_CC_P +set_property -dict {PACKAGE_PIN AF13 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_clk_n] ; ## G7 FMC_LPC_LA00_CC_N + +set_property -dict {PACKAGE_PIN AH17 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_p[0]] ; ## D17 FMC_LPC_LA13_P +set_property -dict {PACKAGE_PIN AH16 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_n[0]] ; ## D18 FMC_LPC_LA13_N +set_property -dict {PACKAGE_PIN AJ16 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_p[1]] ; ## H16 FMC_LPC_LA11_P +set_property -dict {PACKAGE_PIN AK16 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_n[1]] ; ## H17 FMC_LPC_LA11_N +set_property -dict {PACKAGE_PIN AD16 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_p[2]] ; ## G15 FMC_LPC_LA12_P +set_property -dict {PACKAGE_PIN AD15 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_n[2]] ; ## G16 FMC_LPC_LA12_N +set_property -dict {PACKAGE_PIN AH14 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_p[3]] ; ## D14 FMC_LPC_LA09_P +set_property -dict {PACKAGE_PIN AH13 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_n[3]] ; ## D15 FMC_LPC_LA09_N +set_property -dict {PACKAGE_PIN AC14 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_p[4]] ; ## C14 FMC_LPC_LA10_P +set_property -dict {PACKAGE_PIN AC13 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_n[4]] ; ## C15 FMC_LPC_LA10_N +set_property -dict {PACKAGE_PIN AA15 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_p[5]] ; ## H13 FMC_LPC_LA07_P +set_property -dict {PACKAGE_PIN AA14 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_n[5]] ; ## H14 FMC_LPC_LA07_N +set_property -dict {PACKAGE_PIN AD14 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_p[6]] ; ## G12 FMC_LPC_LA08_P +set_property -dict {PACKAGE_PIN AD13 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_n[6]] ; ## G13 FMC_LPC_LA08_N +set_property -dict {PACKAGE_PIN AE16 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_p[7]] ; ## D11 FMC_LPC_LA05_P +set_property -dict {PACKAGE_PIN AE15 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_n[7]] ; ## D12 FMC_LPC_LA05_N +set_property -dict {PACKAGE_PIN AB12 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_p[8]] ; ## C10 FMC_LPC_LA06_P +set_property -dict {PACKAGE_PIN AC12 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_n[8]] ; ## C11 FMC_LPC_LA06_N +set_property -dict {PACKAGE_PIN AJ15 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_p[9]] ; ## H10 FMC_LPC_LA04_P +set_property -dict {PACKAGE_PIN AK15 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_n[9]] ; ## H11 FMC_LPC_LA04_N +set_property -dict {PACKAGE_PIN AG12 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_p[10]] ; ## G09 FMC_LPC_LA03_P +set_property -dict {PACKAGE_PIN AH12 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_n[10]] ; ## G10 FMC_LPC_LA03_N +set_property -dict {PACKAGE_PIN AF15 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_p[11]] ; ## D08 FMC_LPC_LA01_CC_P +set_property -dict {PACKAGE_PIN AG15 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_n[11]] ; ## D09 FMC_LPC_LA01_CC_N + +set_property -dict {PACKAGE_PIN AE12 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_or_p] ; ## H07 FMC_LPC_LA02_P +set_property -dict {PACKAGE_PIN AF12 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_or_n] ; ## H08 FMC_LPC_LA02_N + +# spi + +set_property -dict {PACKAGE_PIN Y30 IOSTANDARD LVCMOS25} [get_ports spi_csn_clk] ; ## G36 FMC_LPC_LA33_P +set_property -dict {PACKAGE_PIN AA30 IOSTANDARD LVCMOS25} [get_ports spi_csn_adc] ; ## G37 FMC_LPC_LA33_N +set_property -dict {PACKAGE_PIN Y27 IOSTANDARD LVCMOS25} [get_ports spi_sclk] ; ## H38 FMC_LPC_LA32_N +set_property -dict {PACKAGE_PIN Y26 IOSTANDARD LVCMOS25} [get_ports spi_dio] ; ## H37 FMC_LPC_LA32_P + +# clocks +create_clock -name adc_clk -period 2.00 [get_ports adc_clk_p] +create_clock -name adc_core_clk -period 8.00 [get_pins i_system_wrapper/system_i/axi_ad9434/adc_clk] + +set_clock_groups -asynchronous -group [get_clocks adc_clk] +set_clock_groups -asynchronous -group [get_clocks adc_core_clk] + diff --git a/projects/ad9434_fmc/zc706/system_project.tcl b/projects/ad9434_fmc/zc706/system_project.tcl new file mode 100644 index 000000000..43f5ee5b8 --- /dev/null +++ b/projects/ad9434_fmc/zc706/system_project.tcl @@ -0,0 +1,14 @@ + +source ../../scripts/adi_env.tcl +source $ad_hdl_dir/projects/scripts/adi_project.tcl + +set project_name ad9434_fmc_zc706 + +adi_project_create $project_name + +adi_project_files $project_name [list "../common/ad9434_spi.v" \ + "system_top.v" \ + "system_constr.xdc" \ + "$ad_hdl_dir/projects/common/zc706/zc706_system_constr.xdc"] + +adi_project_run $project_name diff --git a/projects/ad9434_fmc/zc706/system_top.v b/projects/ad9434_fmc/zc706/system_top.v new file mode 100644 index 000000000..fde94b8a6 --- /dev/null +++ b/projects/ad9434_fmc/zc706/system_top.v @@ -0,0 +1,221 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2011(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module system_top ( + + DDR_addr, + DDR_ba, + DDR_cas_n, + DDR_ck_n, + DDR_ck_p, + DDR_cke, + DDR_cs_n, + DDR_dm, + DDR_dq, + DDR_dqs_n, + DDR_dqs_p, + DDR_odt, + DDR_ras_n, + DDR_reset_n, + DDR_we_n, + + FIXED_IO_ddr_vrn, + FIXED_IO_ddr_vrp, + FIXED_IO_mio, + FIXED_IO_ps_clk, + FIXED_IO_ps_porb, + FIXED_IO_ps_srstb, + + gpio_bd, + + hdmi_out_clk, + hdmi_vsync, + hdmi_hsync, + hdmi_data_e, + hdmi_data, + + spdif, + + iic_scl, + iic_sda, + + adc_clk_p, + adc_clk_n, + adc_data_p, + adc_data_n, + adc_or_p, + adc_or_n, + + spi_csn_clk, + spi_csn_adc, + spi_sclk, + spi_dio); + + inout [14:0] DDR_addr; + inout [ 2:0] DDR_ba; + inout DDR_cas_n; + inout DDR_ck_n; + inout DDR_ck_p; + inout DDR_cke; + inout DDR_cs_n; + inout [ 3:0] DDR_dm; + inout [31:0] DDR_dq; + inout [ 3:0] DDR_dqs_n; + inout [ 3:0] DDR_dqs_p; + inout DDR_odt; + inout DDR_ras_n; + inout DDR_reset_n; + inout DDR_we_n; + + inout FIXED_IO_ddr_vrn; + inout FIXED_IO_ddr_vrp; + inout [53:0] FIXED_IO_mio; + inout FIXED_IO_ps_clk; + inout FIXED_IO_ps_porb; + inout FIXED_IO_ps_srstb; + + inout [14:0] gpio_bd; + + output hdmi_out_clk; + output hdmi_vsync; + output hdmi_hsync; + output hdmi_data_e; + output [23:0] hdmi_data; + + output spdif; + + inout iic_scl; + inout iic_sda; + + input adc_clk_p; + input adc_clk_n; + input [11:0] adc_data_p; + input [11:0] adc_data_n; + input adc_or_p; + input adc_or_n; + + output spi_csn_clk; + output spi_csn_adc; + output spi_sclk; + inout spi_dio; + + // internal signals + + wire [14:0] gpio_i; + wire [14:0] gpio_o; + wire [14:0] gpio_t; + wire spi_miso; + wire spi_mosi; + + wire spi_csn_adc; + wire spi_csn_clk; + + // instantiations + + genvar n; + generate + for (n = 0; n <= 14; n = n + 1) begin: g_iobuf_gpio_bd + IOBUF i_iobuf_gpio_bd ( + .I (gpio_o[n]), + .O (gpio_i[n]), + .T (gpio_t[n]), + .IO (gpio_bd[n])); + end + endgenerate + + ad9434_spi i_spi ( + .spi_csn({spi_csn_clk, spi_csn_adc}), + .spi_clk(spi_sclk), + .spi_mosi(spi_mosi), + .spi_miso(spi_miso), + .spi_sdio(spi_dio) + ); + + system_wrapper i_system_wrapper ( + .DDR_addr (DDR_addr), + .DDR_ba (DDR_ba), + .DDR_cas_n (DDR_cas_n), + .DDR_ck_n (DDR_ck_n), + .DDR_ck_p (DDR_ck_p), + .DDR_cke (DDR_cke), + .DDR_cs_n (DDR_cs_n), + .DDR_dm (DDR_dm), + .DDR_dq (DDR_dq), + .DDR_dqs_n (DDR_dqs_n), + .DDR_dqs_p (DDR_dqs_p), + .DDR_odt (DDR_odt), + .DDR_ras_n (DDR_ras_n), + .DDR_reset_n (DDR_reset_n), + .DDR_we_n (DDR_we_n), + .FIXED_IO_ddr_vrn (FIXED_IO_ddr_vrn), + .FIXED_IO_ddr_vrp (FIXED_IO_ddr_vrp), + .FIXED_IO_mio (FIXED_IO_mio), + .FIXED_IO_ps_clk (FIXED_IO_ps_clk), + .FIXED_IO_ps_porb (FIXED_IO_ps_porb), + .FIXED_IO_ps_srstb (FIXED_IO_ps_srstb), + .GPIO_I (gpio_i), + .GPIO_O (gpio_o), + .GPIO_T (gpio_t), + .hdmi_data (hdmi_data), + .hdmi_data_e (hdmi_data_e), + .hdmi_hsync (hdmi_hsync), + .hdmi_out_clk (hdmi_out_clk), + .hdmi_vsync (hdmi_vsync), + .iic_main_scl_io (iic_scl), + .iic_main_sda_io (iic_sda), + .spdif (spdif), + .adc_clk_p(adc_clk_p), + .adc_clk_n(adc_clk_n), + .adc_data_p(adc_data_p), + .adc_data_n(adc_data_n), + .adc_or_p(adc_or_p), + .adc_or_n(adc_or_n), + .spi_clk_i(1'b0), + .spi_clk_o(spi_sclk), + .spi_csn_i(1'b1), + .spi_csn_adc_o(spi_csn_adc), + .spi_csn_clk_o(spi_csn_clk), + .spi_mosi_i(spi_mosi), + .spi_mosi_o(spi_mosi), + .spi_miso_i(spi_miso)); + +endmodule + From 40287f4d978ee2ac546372d14ca514eee49b2812 Mon Sep 17 00:00:00 2001 From: Rejeesh Kutty Date: Mon, 8 Dec 2014 14:39:43 -0500 Subject: [PATCH 42/42] remove fmcadc3 --- projects/fmcadc3/common/fmcadc3_bd.tcl | 399 ------------------ projects/fmcadc3/common/fmcadc3_spi.v | 113 ----- projects/fmcadc3/zc706/system_bd.tcl | 57 --- projects/fmcadc3/zc706/system_constr.xdc | 58 --- projects/fmcadc3/zc706/system_project.tcl | 17 - projects/fmcadc3/zc706/system_top.v | 492 ---------------------- 6 files changed, 1136 deletions(-) delete mode 100644 projects/fmcadc3/common/fmcadc3_bd.tcl delete mode 100644 projects/fmcadc3/common/fmcadc3_spi.v delete mode 100644 projects/fmcadc3/zc706/system_bd.tcl delete mode 100644 projects/fmcadc3/zc706/system_constr.xdc delete mode 100644 projects/fmcadc3/zc706/system_project.tcl delete mode 100644 projects/fmcadc3/zc706/system_top.v diff --git a/projects/fmcadc3/common/fmcadc3_bd.tcl b/projects/fmcadc3/common/fmcadc3_bd.tcl deleted file mode 100644 index aa5c9c71e..000000000 --- a/projects/fmcadc3/common/fmcadc3_bd.tcl +++ /dev/null @@ -1,399 +0,0 @@ - - # fmcadc3 - -if {$sys_zynq == 0} { - - set spi_csn_i [create_bd_port -dir I -from 2 -to 0 spi_csn_i] - set spi_csn_o [create_bd_port -dir O -from 2 -to 0 spi_csn_o] - -} else { - - set spi_csn_0 [create_bd_port -dir O spi_csn_0] - set spi_csn_1 [create_bd_port -dir O spi_csn_1] - set spi_csn_2 [create_bd_port -dir O spi_csn_2] - set spi_csn_i [create_bd_port -dir I spi_csn_i] -} - - set spi_clk_i [create_bd_port -dir I spi_clk_i] - set spi_clk_o [create_bd_port -dir O spi_clk_o] - set spi_sdo_i [create_bd_port -dir I spi_sdo_i] - set spi_sdo_o [create_bd_port -dir O spi_sdo_o] - set spi_sdi_i [create_bd_port -dir I spi_sdi_i] - - set rx_ref_clk [create_bd_port -dir I rx_ref_clk] - set rx_sync [create_bd_port -dir O rx_sync] - set rx_sysref [create_bd_port -dir I rx_sysref] - set rx_data_p [create_bd_port -dir I -from 7 -to 0 rx_data_p] - set rx_data_n [create_bd_port -dir I -from 7 -to 0 rx_data_n] - -if {$sys_zynq == 0} { - - set gpio_ctl_i [create_bd_port -dir I gpio_ctl_i] - set gpio_ctl_o [create_bd_port -dir O gpio_ctl_o] - set gpio_ctl_t [create_bd_port -dir O gpio_ctl_t] - set gpio_status_i [create_bd_port -dir I -from 4 -to 0 gpio_status_i] - set gpio_status_o [create_bd_port -dir O -from 4 -to 0 gpio_status_o] - set gpio_status_t [create_bd_port -dir O -from 4 -to 0 gpio_status_t] -} - - set gt_data [create_bd_port -dir O -from 255 -to 0 gt_data] - set gt_data_0 [create_bd_port -dir I -from 127 -to 0 gt_data_0] - set gt_data_1 [create_bd_port -dir I -from 127 -to 0 gt_data_1] - set adc_clk [create_bd_port -dir O adc_clk] - set adc_enable_0 [create_bd_port -dir O adc_enable_0] - set adc_valid_0 [create_bd_port -dir O adc_valid_0] - set adc_data_0 [create_bd_port -dir O -from 63 -to 0 adc_data_0] - set adc_enable_1 [create_bd_port -dir O adc_enable_1] - set adc_valid_1 [create_bd_port -dir O adc_valid_1] - set adc_data_1 [create_bd_port -dir O -from 63 -to 0 adc_data_1] - set adc_enable_2 [create_bd_port -dir O adc_enable_2] - set adc_valid_2 [create_bd_port -dir O adc_valid_2] - set adc_data_2 [create_bd_port -dir O -from 63 -to 0 adc_data_2] - set adc_enable_3 [create_bd_port -dir O adc_enable_3] - set adc_valid_3 [create_bd_port -dir O adc_valid_3] - set adc_data_3 [create_bd_port -dir O -from 63 -to 0 adc_data_3] - set adc_dwr [create_bd_port -dir I adc_dwr] - set adc_dsync [create_bd_port -dir I adc_dsync] - set adc_ddata [create_bd_port -dir I -from 255 -to 0 adc_ddata] - - # adc peripherals - - set axi_ad9234_core_0 [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9234:1.0 axi_ad9234_core_0] - set axi_ad9234_core_1 [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9234:1.0 axi_ad9234_core_1] - - set axi_ad9234_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:5.2 axi_ad9234_jesd] - set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {0}] $axi_ad9234_jesd - set_property -dict [list CONFIG.C_LANES {8}] $axi_ad9234_jesd - - set axi_ad9234_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad9234_dma] - set_property -dict [list CONFIG.C_DMA_TYPE_SRC {2}] $axi_ad9234_dma - set_property -dict [list CONFIG.C_DMA_TYPE_DEST {0}] $axi_ad9234_dma - set_property -dict [list CONFIG.PCORE_ID {0}] $axi_ad9234_dma - set_property -dict [list CONFIG.C_AXI_SLICE_SRC {0}] $axi_ad9234_dma - set_property -dict [list CONFIG.C_AXI_SLICE_DEST {0}] $axi_ad9234_dma - set_property -dict [list CONFIG.C_CLKS_ASYNC_DEST_REQ {1}] $axi_ad9234_dma - set_property -dict [list CONFIG.C_SYNC_TRANSFER_START {1}] $axi_ad9234_dma - set_property -dict [list CONFIG.C_DMA_LENGTH_WIDTH {24}] $axi_ad9234_dma - set_property -dict [list CONFIG.C_2D_TRANSFER {0}] $axi_ad9234_dma - set_property -dict [list CONFIG.C_CYCLIC {0}] $axi_ad9234_dma - set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_SRC {256}] $axi_ad9234_dma - set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_DEST {256}] $axi_ad9234_dma - -if {$sys_zynq == 1} { - - set axi_ad9234_dma_interconnect [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_ad9234_dma_interconnect] - set_property -dict [list CONFIG.NUM_MI {1}] $axi_ad9234_dma_interconnect -} - - # dac/adc common gt/gpio - - set axi_fmcadc3_gt [create_bd_cell -type ip -vlnv analog.com:user:axi_jesd_gt:1.0 axi_fmcadc3_gt] - set_property -dict [list CONFIG.PCORE_NUM_OF_LANES {8}] $axi_fmcadc3_gt - -if {$sys_zynq == 1} { - - set axi_fmcadc3_gt_interconnect [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_fmcadc3_gt_interconnect] - set_property -dict [list CONFIG.NUM_MI {1}] $axi_fmcadc3_gt_interconnect -} - - # gpio and spi - -if {$sys_zynq == 0} { - - set axi_fmcadc3_spi [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_quad_spi:3.1 axi_fmcadc3_spi] - set_property -dict [list CONFIG.C_USE_STARTUP {0}] $axi_fmcadc3_spi - set_property -dict [list CONFIG.C_NUM_SS_BITS {3}] $axi_fmcadc3_spi - set_property -dict [list CONFIG.C_SCK_RATIO {8}] $axi_fmcadc3_spi - - set axi_fmcadc3_gpio [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_fmcadc3_gpio] - set_property -dict [list CONFIG.C_IS_DUAL {1}] $axi_fmcadc3_gpio - set_property -dict [list CONFIG.C_GPIO_WIDTH {5}] $axi_fmcadc3_gpio - set_property -dict [list CONFIG.C_GPIO2_WIDTH {1}] $axi_fmcadc3_gpio - set_property -dict [list CONFIG.C_INTERRUPT_PRESENT {1}] $axi_fmcadc3_gpio -} - - # additions to default configuration - -if {$sys_zynq == 0} { - - set_property -dict [list CONFIG.NUM_MI {14}] $axi_cpu_interconnect - -} else { - - set_property -dict [list CONFIG.NUM_MI {12}] $axi_cpu_interconnect -} - -if {$sys_zynq == 0} { - - set_property -dict [list CONFIG.NUM_SI {11}] $axi_mem_interconnect - set_property -dict [list CONFIG.NUM_PORTS {7}] $sys_concat_intc -} - -if {$sys_zynq == 1} { - - set_property -dict [list CONFIG.PCW_USE_S_AXI_HP2 {1}] $sys_ps7 - set_property -dict [list CONFIG.PCW_USE_S_AXI_HP3 {1}] $sys_ps7 - set_property -dict [list CONFIG.PCW_EN_CLK2_PORT {1}] $sys_ps7 - set_property -dict [list CONFIG.PCW_EN_RST2_PORT {1}] $sys_ps7 - set_property -dict [list CONFIG.PCW_FPGA2_PERIPHERAL_FREQMHZ {200.0}] $sys_ps7 - set_property -dict [list CONFIG.PCW_GPIO_EMIO_GPIO_IO {38}] $sys_ps7 - set_property -dict [list CONFIG.PCW_SPI0_PERIPHERAL_ENABLE {1}] $sys_ps7 - set_property -dict [list CONFIG.PCW_SPI0_SPI0_IO {EMIO}] $sys_ps7 - - set_property LEFT 37 [get_bd_ports GPIO_I] - set_property LEFT 37 [get_bd_ports GPIO_O] - set_property LEFT 37 [get_bd_ports GPIO_T] -} - - # connections (spi and gpio) - -if {$sys_zynq == 0} { - - connect_bd_net -net spi_csn_i [get_bd_ports spi_csn_i] [get_bd_pins axi_fmcadc3_spi/ss_i] - connect_bd_net -net spi_csn_o [get_bd_ports spi_csn_o] [get_bd_pins axi_fmcadc3_spi/ss_o] - connect_bd_net -net spi_clk_i [get_bd_ports spi_clk_i] [get_bd_pins axi_fmcadc3_spi/sck_i] - connect_bd_net -net spi_clk_o [get_bd_ports spi_clk_o] [get_bd_pins axi_fmcadc3_spi/sck_o] - connect_bd_net -net spi_sdo_i [get_bd_ports spi_sdo_i] [get_bd_pins axi_fmcadc3_spi/io0_i] - connect_bd_net -net spi_sdo_o [get_bd_ports spi_sdo_o] [get_bd_pins axi_fmcadc3_spi/io0_o] - connect_bd_net -net spi_sdi_i [get_bd_ports spi_sdi_i] [get_bd_pins axi_fmcadc3_spi/io1_i] - -} else { - - connect_bd_net -net spi_csn_0 [get_bd_ports spi_csn_0] [get_bd_pins sys_ps7/SPI0_SS_O] - connect_bd_net -net spi_csn_1 [get_bd_ports spi_csn_1] [get_bd_pins sys_ps7/SPI0_SS1_O] - connect_bd_net -net spi_csn_2 [get_bd_ports spi_csn_2] [get_bd_pins sys_ps7/SPI0_SS2_O] - connect_bd_net -net spi_csn_i [get_bd_ports spi_csn_i] [get_bd_pins sys_ps7/SPI0_SS_I] - connect_bd_net -net spi_clk_i [get_bd_ports spi_clk_i] [get_bd_pins sys_ps7/SPI0_SCLK_I] - connect_bd_net -net spi_clk_o [get_bd_ports spi_clk_o] [get_bd_pins sys_ps7/SPI0_SCLK_O] - connect_bd_net -net spi_sdo_i [get_bd_ports spi_sdo_i] [get_bd_pins sys_ps7/SPI0_MOSI_I] - connect_bd_net -net spi_sdo_o [get_bd_ports spi_sdo_o] [get_bd_pins sys_ps7/SPI0_MOSI_O] - connect_bd_net -net spi_sdi_i [get_bd_ports spi_sdi_i] [get_bd_pins sys_ps7/SPI0_MISO_I] -} - -if {$sys_zynq == 0} { - - connect_bd_net -net gpio_status_i [get_bd_ports gpio_status_i] [get_bd_pins axi_fmcadc3_gpio/gpio_io_i] - connect_bd_net -net gpio_status_o [get_bd_ports gpio_status_o] [get_bd_pins axi_fmcadc3_gpio/gpio_io_o] - connect_bd_net -net gpio_status_t [get_bd_ports gpio_status_t] [get_bd_pins axi_fmcadc3_gpio/gpio_io_t] - connect_bd_net -net gpio_ctl_i [get_bd_ports gpio_ctl_i] [get_bd_pins axi_fmcadc3_gpio/gpio2_io_i] - connect_bd_net -net gpio_ctl_o [get_bd_ports gpio_ctl_o] [get_bd_pins axi_fmcadc3_gpio/gpio2_io_o] - connect_bd_net -net gpio_ctl_t [get_bd_ports gpio_ctl_t] [get_bd_pins axi_fmcadc3_gpio/gpio2_io_t] -} - -if {$sys_zynq == 0} { - - delete_bd_objs [get_bd_nets sys_concat_intc_din_2] [get_bd_ports unc_int2] - delete_bd_objs [get_bd_nets sys_concat_intc_din_3] [get_bd_ports unc_int3] -} - - # connections (gt) - - connect_bd_net -net axi_fmcadc3_gt_ref_clk_q [get_bd_pins axi_fmcadc3_gt/ref_clk_q] [get_bd_ports rx_ref_clk] - connect_bd_net -net axi_fmcadc3_gt_rx_data_p [get_bd_pins axi_fmcadc3_gt/rx_data_p] [get_bd_ports rx_data_p] - connect_bd_net -net axi_fmcadc3_gt_rx_data_n [get_bd_pins axi_fmcadc3_gt/rx_data_n] [get_bd_ports rx_data_n] - connect_bd_net -net axi_fmcadc3_gt_rx_sync [get_bd_pins axi_fmcadc3_gt/rx_sync] [get_bd_ports rx_sync] - connect_bd_net -net axi_fmcadc3_gt_rx_ext_sysref [get_bd_pins axi_fmcadc3_gt/rx_ext_sysref] [get_bd_ports rx_sysref] - - # connections (adc) - - connect_bd_net -net axi_fmcadc3_gt_rx_clk [get_bd_pins axi_fmcadc3_gt/rx_clk_g] - connect_bd_net -net axi_fmcadc3_gt_rx_clk [get_bd_pins axi_fmcadc3_gt/rx_clk] - connect_bd_net -net axi_fmcadc3_gt_rx_clk [get_bd_pins axi_ad9234_core_0/rx_clk] - connect_bd_net -net axi_fmcadc3_gt_rx_clk [get_bd_pins axi_ad9234_core_1/rx_clk] - connect_bd_net -net axi_fmcadc3_gt_rx_clk [get_bd_pins axi_ad9234_jesd/rx_core_clk] - - connect_bd_net -net axi_fmcadc3_gt_rx_rst [get_bd_pins axi_fmcadc3_gt/rx_rst] [get_bd_pins axi_ad9234_jesd/rx_reset] - connect_bd_net -net axi_fmcadc3_gt_rx_sysref [get_bd_pins axi_fmcadc3_gt/rx_sysref] [get_bd_pins axi_ad9234_jesd/rx_sysref] - connect_bd_net -net axi_fmcadc3_gt_rx_gt_charisk [get_bd_pins axi_fmcadc3_gt/rx_gt_charisk] [get_bd_pins axi_ad9234_jesd/gt_rxcharisk_in] - connect_bd_net -net axi_fmcadc3_gt_rx_gt_disperr [get_bd_pins axi_fmcadc3_gt/rx_gt_disperr] [get_bd_pins axi_ad9234_jesd/gt_rxdisperr_in] - connect_bd_net -net axi_fmcadc3_gt_rx_gt_notintable [get_bd_pins axi_fmcadc3_gt/rx_gt_notintable] [get_bd_pins axi_ad9234_jesd/gt_rxnotintable_in] - connect_bd_net -net axi_fmcadc3_gt_rx_gt_data [get_bd_pins axi_fmcadc3_gt/rx_gt_data] [get_bd_pins axi_ad9234_jesd/gt_rxdata_in] - connect_bd_net -net axi_fmcadc3_gt_rx_rst_done [get_bd_pins axi_fmcadc3_gt/rx_rst_done] [get_bd_pins axi_ad9234_jesd/rx_reset_done] - connect_bd_net -net axi_fmcadc3_gt_rx_ip_comma_align [get_bd_pins axi_fmcadc3_gt/rx_ip_comma_align] [get_bd_pins axi_ad9234_jesd/rxencommaalign_out] - connect_bd_net -net axi_fmcadc3_gt_rx_ip_sync [get_bd_pins axi_fmcadc3_gt/rx_ip_sync] [get_bd_pins axi_ad9234_jesd/rx_sync] - connect_bd_net -net axi_fmcadc3_gt_rx_ip_sof [get_bd_pins axi_fmcadc3_gt/rx_ip_sof] [get_bd_pins axi_ad9234_jesd/rx_start_of_frame] - connect_bd_net -net axi_fmcadc3_gt_rx_ip_data [get_bd_pins axi_fmcadc3_gt/rx_ip_data] [get_bd_pins axi_ad9234_jesd/rx_tdata] - connect_bd_net -net axi_fmcadc3_gt_rx_data [get_bd_pins axi_fmcadc3_gt/rx_data] [get_bd_ports gt_data] - connect_bd_net -net axi_fmcadc3_gt_0_rx_data [get_bd_pins axi_ad9234_core_0/rx_data] [get_bd_ports gt_data_0] - connect_bd_net -net axi_fmcadc3_gt_1_rx_data [get_bd_pins axi_ad9234_core_1/rx_data] [get_bd_ports gt_data_1] - connect_bd_net -net axi_ad9234_adc_clk [get_bd_pins axi_ad9234_core_0/adc_clk] [get_bd_pins axi_ad9234_dma/fifo_wr_clk] - connect_bd_net -net axi_ad9234_0_adc_enable_0 [get_bd_pins axi_ad9234_core_0/adc_enable_0] [get_bd_ports adc_enable_0] - connect_bd_net -net axi_ad9234_0_adc_valid_0 [get_bd_pins axi_ad9234_core_0/adc_valid_0] [get_bd_ports adc_valid_0] - connect_bd_net -net axi_ad9234_0_adc_data_0 [get_bd_pins axi_ad9234_core_0/adc_data_0] [get_bd_ports adc_data_0] - connect_bd_net -net axi_ad9234_0_adc_enable_1 [get_bd_pins axi_ad9234_core_0/adc_enable_1] [get_bd_ports adc_enable_1] - connect_bd_net -net axi_ad9234_0_adc_valid_1 [get_bd_pins axi_ad9234_core_0/adc_valid_1] [get_bd_ports adc_valid_1] - connect_bd_net -net axi_ad9234_0_adc_data_1 [get_bd_pins axi_ad9234_core_0/adc_data_1] [get_bd_ports adc_data_1] - connect_bd_net -net axi_ad9234_1_adc_enable_0 [get_bd_pins axi_ad9234_core_1/adc_enable_0] [get_bd_ports adc_enable_2] - connect_bd_net -net axi_ad9234_1_adc_valid_0 [get_bd_pins axi_ad9234_core_1/adc_valid_0] [get_bd_ports adc_valid_2] - connect_bd_net -net axi_ad9234_1_adc_data_0 [get_bd_pins axi_ad9234_core_1/adc_data_0] [get_bd_ports adc_data_2] - connect_bd_net -net axi_ad9234_1_adc_enable_1 [get_bd_pins axi_ad9234_core_1/adc_enable_1] [get_bd_ports adc_enable_3] - connect_bd_net -net axi_ad9234_1_adc_valid_1 [get_bd_pins axi_ad9234_core_1/adc_valid_1] [get_bd_ports adc_valid_3] - connect_bd_net -net axi_ad9234_1_adc_data_1 [get_bd_pins axi_ad9234_core_1/adc_data_1] [get_bd_ports adc_data_3] - connect_bd_net -net axi_ad9234_adc_dwr [get_bd_ports adc_dwr] [get_bd_pins axi_ad9234_dma/fifo_wr_en] - connect_bd_net -net axi_ad9234_adc_dsync [get_bd_ports adc_dsync] [get_bd_pins axi_ad9234_dma/fifo_wr_sync] - connect_bd_net -net axi_ad9234_adc_ddata [get_bd_ports adc_ddata] [get_bd_pins axi_ad9234_dma/fifo_wr_din] - connect_bd_net -net axi_ad9234_adc_dovf [get_bd_pins axi_ad9234_core_0/adc_dovf] [get_bd_pins axi_ad9234_dma/fifo_wr_overflow] - connect_bd_net -net axi_ad9234_dma_irq [get_bd_pins axi_ad9234_dma/irq] [get_bd_pins sys_concat_intc/In2] - - # dac/adc clocks - - connect_bd_net -net axi_ad9234_adc_clk [get_bd_ports adc_clk] - - # interconnect (cpu) - - connect_bd_intf_net -intf_net axi_cpu_interconnect_m07_axi [get_bd_intf_pins axi_cpu_interconnect/M07_AXI] [get_bd_intf_pins axi_ad9234_dma/s_axi] - connect_bd_intf_net -intf_net axi_cpu_interconnect_m08_axi [get_bd_intf_pins axi_cpu_interconnect/M08_AXI] [get_bd_intf_pins axi_ad9234_core_0/s_axi] - connect_bd_intf_net -intf_net axi_cpu_interconnect_m09_axi [get_bd_intf_pins axi_cpu_interconnect/M09_AXI] [get_bd_intf_pins axi_ad9234_core_1/s_axi] - connect_bd_intf_net -intf_net axi_cpu_interconnect_m10_axi [get_bd_intf_pins axi_cpu_interconnect/M10_AXI] [get_bd_intf_pins axi_ad9234_jesd/s_axi] - connect_bd_intf_net -intf_net axi_cpu_interconnect_m11_axi [get_bd_intf_pins axi_cpu_interconnect/M11_AXI] [get_bd_intf_pins axi_fmcadc3_gt/s_axi] - connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M07_ACLK] $sys_100m_clk_source - connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M08_ACLK] $sys_100m_clk_source - connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M09_ACLK] $sys_100m_clk_source - connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M10_ACLK] $sys_100m_clk_source - connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M11_ACLK] $sys_100m_clk_source - connect_bd_net -net sys_100m_clk [get_bd_pins axi_fmcadc3_gt/s_axi_aclk] - connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9234_core_0/s_axi_aclk] - connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9234_core_1/s_axi_aclk] - connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9234_jesd/s_axi_aclk] - connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9234_dma/s_axi_aclk] - connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M07_ARESETN] $sys_100m_resetn_source - connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M08_ARESETN] $sys_100m_resetn_source - connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M09_ARESETN] $sys_100m_resetn_source - connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M10_ARESETN] $sys_100m_resetn_source - connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M11_ARESETN] $sys_100m_resetn_source - connect_bd_net -net sys_100m_resetn [get_bd_pins axi_fmcadc3_gt/s_axi_aresetn] - connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9234_core_0/s_axi_aresetn] - connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9234_core_1/s_axi_aresetn] - connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9234_jesd/s_axi_aresetn] - connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9234_dma/s_axi_aresetn] - -if {$sys_zynq == 0} { - - connect_bd_intf_net -intf_net axi_cpu_interconnect_m12_axi [get_bd_intf_pins axi_cpu_interconnect/M12_AXI] [get_bd_intf_pins axi_fmcadc3_spi/axi_lite] - connect_bd_intf_net -intf_net axi_cpu_interconnect_m13_axi [get_bd_intf_pins axi_cpu_interconnect/M13_AXI] [get_bd_intf_pins axi_fmcadc3_gpio/s_axi] - connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M12_ACLK] $sys_100m_clk_source - connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M13_ACLK] $sys_100m_clk_source - connect_bd_net -net sys_100m_clk [get_bd_pins axi_fmcadc3_spi/s_axi_aclk] - connect_bd_net -net sys_100m_clk [get_bd_pins axi_fmcadc3_spi/ext_spi_clk] - connect_bd_net -net sys_100m_clk [get_bd_pins axi_fmcadc3_gpio/s_axi_aclk] - connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M12_ARESETN] $sys_100m_resetn_source - connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M13_ARESETN] $sys_100m_resetn_source - connect_bd_net -net sys_100m_resetn [get_bd_pins axi_fmcadc3_spi/s_axi_aresetn] - connect_bd_net -net sys_100m_resetn [get_bd_pins axi_fmcadc3_gpio/s_axi_aresetn] - - connect_bd_net -net axi_fmcadc3_spi_irq [get_bd_pins axi_fmcadc3_spi/ip2intc_irpt] [get_bd_pins sys_concat_intc/In5] - connect_bd_net -net axi_fmcadc3_gpio_irq [get_bd_pins axi_fmcadc3_gpio/ip2intc_irpt] [get_bd_pins sys_concat_intc/In6] -} - - # gt uses hp3, and 100MHz clock for both DRP and AXI4 - -if {$sys_zynq == 0} { - - connect_bd_intf_net -intf_net axi_mem_interconnect_s08_axi [get_bd_intf_pins axi_mem_interconnect/S08_AXI] [get_bd_intf_pins axi_fmcadc3_gt/m_axi] - connect_bd_net -net sys_100m_clk [get_bd_pins axi_mem_interconnect/S08_ACLK] $sys_100m_clk_source - connect_bd_net -net sys_100m_clk [get_bd_pins axi_fmcadc3_gt/m_axi_aclk] - connect_bd_net -net sys_100m_clk [get_bd_pins axi_fmcadc3_gt/drp_clk] - connect_bd_net -net sys_100m_resetn [get_bd_pins axi_mem_interconnect/S08_ARESETN] $sys_100m_resetn_source - connect_bd_net -net sys_100m_resetn [get_bd_pins axi_fmcadc3_gt/m_axi_aresetn] - -} else { - - connect_bd_intf_net -intf_net axi_fmcadc3_gt_interconnect_m00_axi [get_bd_intf_pins axi_fmcadc3_gt_interconnect/M00_AXI] [get_bd_intf_pins sys_ps7/S_AXI_HP3] - connect_bd_intf_net -intf_net axi_fmcadc3_gt_interconnect_s00_axi [get_bd_intf_pins axi_fmcadc3_gt_interconnect/S00_AXI] [get_bd_intf_pins axi_fmcadc3_gt/m_axi] - connect_bd_net -net sys_100m_clk [get_bd_pins axi_fmcadc3_gt_interconnect/ACLK] $sys_100m_clk_source - connect_bd_net -net sys_100m_clk [get_bd_pins axi_fmcadc3_gt_interconnect/M00_ACLK] $sys_100m_clk_source - connect_bd_net -net sys_100m_clk [get_bd_pins axi_fmcadc3_gt_interconnect/S00_ACLK] $sys_100m_clk_source - connect_bd_net -net sys_100m_clk [get_bd_pins sys_ps7/S_AXI_HP3_ACLK] - connect_bd_net -net sys_100m_clk [get_bd_pins axi_fmcadc3_gt/m_axi_aclk] - connect_bd_net -net sys_100m_clk [get_bd_pins axi_fmcadc3_gt/drp_clk] - connect_bd_net -net sys_100m_resetn [get_bd_pins axi_fmcadc3_gt_interconnect/ARESETN] $sys_100m_resetn_source - connect_bd_net -net sys_100m_resetn [get_bd_pins axi_fmcadc3_gt_interconnect/M00_ARESETN] $sys_100m_resetn_source - connect_bd_net -net sys_100m_resetn [get_bd_pins axi_fmcadc3_gt_interconnect/S00_ARESETN] $sys_100m_resetn_source - connect_bd_net -net sys_100m_resetn [get_bd_pins axi_fmcadc3_gt/m_axi_aresetn] -} - - # memory interconnects share the same clock (fclk2) - -if {$sys_zynq == 1} { - set sys_fmc_dma_sync_reset [create_bd_cell -type ip -vlnv analog.com:user:util_sync_reset:1.0 sys_fmc_dma_sync_reset] - - set sys_fmc_dma_clk_source [get_bd_pins sys_ps7/FCLK_CLK2] - set sys_fmc_dma_resetn_source [get_bd_pins sys_fmc_dma_sync_reset/sync_resetn] - - connect_bd_net -net sys_fmc_dma_clk [get_bd_pins sys_fmc_dma_sync_reset/clk] - connect_bd_net -net sys_fmc_dma_async_reset \ - [get_bd_pins sys_fmc_dma_sync_reset/async_resetn] \ - [get_bd_pins sys_ps7/FCLK_RESET2_N] - - connect_bd_net -net sys_fmc_dma_clk $sys_fmc_dma_clk_source - connect_bd_net -net sys_fmc_dma_resetn $sys_fmc_dma_resetn_source -} - - # interconnect (mem/dac) - -if {$sys_zynq == 0} { - - connect_bd_intf_net -intf_net axi_mem_interconnect_s09_axi [get_bd_intf_pins axi_mem_interconnect/S09_AXI] [get_bd_intf_pins axi_ad9234_dma/m_dest_axi] - connect_bd_net -net sys_200m_clk [get_bd_pins axi_mem_interconnect/S09_ACLK] $sys_200m_clk_source - connect_bd_net -net sys_200m_clk [get_bd_pins axi_ad9234_dma/m_dest_axi_aclk] - connect_bd_net -net sys_200m_resetn [get_bd_pins axi_mem_interconnect/S09_ARESETN] $sys_200m_resetn_source - connect_bd_net -net sys_200m_resetn [get_bd_pins axi_ad9234_dma/m_dest_axi_aresetn] - -} else { - - connect_bd_intf_net -intf_net axi_ad9234_dma_interconnect_m00_axi [get_bd_intf_pins axi_ad9234_dma_interconnect/M00_AXI] [get_bd_intf_pins sys_ps7/S_AXI_HP2] - connect_bd_intf_net -intf_net axi_ad9234_dma_interconnect_s00_axi [get_bd_intf_pins axi_ad9234_dma_interconnect/S00_AXI] [get_bd_intf_pins axi_ad9234_dma/m_dest_axi] - connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_ad9234_dma_interconnect/ACLK] $sys_fmc_dma_clk_source - connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_ad9234_dma_interconnect/M00_ACLK] $sys_fmc_dma_clk_source - connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_ad9234_dma_interconnect/S00_ACLK] $sys_fmc_dma_clk_source - connect_bd_net -net sys_fmc_dma_clk [get_bd_pins sys_ps7/S_AXI_HP2_ACLK] - connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_ad9234_dma/m_dest_axi_aclk] - connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_ad9234_dma_interconnect/ARESETN] $sys_fmc_dma_resetn_source - connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_ad9234_dma_interconnect/M00_ARESETN] $sys_fmc_dma_resetn_source - connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_ad9234_dma_interconnect/S00_ARESETN] $sys_fmc_dma_resetn_source - connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_ad9234_dma/m_dest_axi_aresetn] -} - - # ila - - set ila_jesd_rx_mon [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:4.0 ila_jesd_rx_mon] - set_property -dict [list CONFIG.C_MONITOR_TYPE {Native}] $ila_jesd_rx_mon - set_property -dict [list CONFIG.C_NUM_OF_PROBES {4}] $ila_jesd_rx_mon - set_property -dict [list CONFIG.C_PROBE0_WIDTH {662}] $ila_jesd_rx_mon - set_property -dict [list CONFIG.C_PROBE1_WIDTH {10}] $ila_jesd_rx_mon - set_property -dict [list CONFIG.C_PROBE2_WIDTH {256}] $ila_jesd_rx_mon - set_property -dict [list CONFIG.C_PROBE3_WIDTH {256}] $ila_jesd_rx_mon - - connect_bd_net -net axi_fmcadc3_gt_rx_mon_data [get_bd_pins axi_fmcadc3_gt/rx_mon_data] - connect_bd_net -net axi_fmcadc3_gt_rx_mon_trigger [get_bd_pins axi_fmcadc3_gt/rx_mon_trigger] - connect_bd_net -net axi_fmcadc3_gt_rx_clk [get_bd_pins ila_jesd_rx_mon/CLK] - connect_bd_net -net axi_fmcadc3_gt_rx_mon_data [get_bd_pins ila_jesd_rx_mon/PROBE0] - connect_bd_net -net axi_fmcadc3_gt_rx_mon_trigger [get_bd_pins ila_jesd_rx_mon/PROBE1] - connect_bd_net -net axi_fmcadc3_gt_rx_data [get_bd_pins ila_jesd_rx_mon/PROBE2] - connect_bd_net -net axi_ad9234_adc_ddata [get_bd_pins ila_jesd_rx_mon/PROBE3] - - # address map - - create_bd_addr_seg -range 0x00010000 -offset 0x44A00000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad9234_core_0/s_axi/axi_lite] SEG_data_ad9234_0_core - create_bd_addr_seg -range 0x00010000 -offset 0x44A10000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad9234_core_1/s_axi/axi_lite] SEG_data_ad9234_1_core - create_bd_addr_seg -range 0x00010000 -offset 0x44A60000 $sys_addr_cntrl_space [get_bd_addr_segs axi_fmcadc3_gt/s_axi/axi_lite] SEG_data_fmcadc3_gt - create_bd_addr_seg -range 0x00001000 -offset 0x44A91000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad9234_jesd/s_axi/Reg] SEG_data_ad9234_jesd - create_bd_addr_seg -range 0x00010000 -offset 0x7c400000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad9234_dma/s_axi/axi_lite] SEG_data_ad9234_dma - -if {$sys_zynq == 0} { - - create_bd_addr_seg -range 0x00010000 -offset 0x40000000 $sys_addr_cntrl_space [get_bd_addr_segs axi_fmcadc3_gpio/S_AXI/Reg] SEG_data_fmcadc3_gpio - create_bd_addr_seg -range 0x00010000 -offset 0x44A70000 $sys_addr_cntrl_space [get_bd_addr_segs axi_fmcadc3_spi/axi_lite/Reg] SEG_data_fmcadc3_spi -} - -if {$sys_zynq == 0} { - - create_bd_addr_seg -range $sys_mem_size -offset 0x80000000 [get_bd_addr_spaces axi_ad9234_dma/m_dest_axi] [get_bd_addr_segs axi_ddr_cntrl/memmap/memaddr] SEG_axi_ddr_cntrl - create_bd_addr_seg -range $sys_mem_size -offset 0x80000000 [get_bd_addr_spaces axi_fmcadc3_gt/m_axi] [get_bd_addr_segs axi_ddr_cntrl/memmap/memaddr] SEG_axi_ddr_cntrl - -} else { - - create_bd_addr_seg -range $sys_mem_size -offset 0x00000000 [get_bd_addr_spaces axi_ad9234_dma/m_dest_axi] [get_bd_addr_segs sys_ps7/S_AXI_HP2/HP2_DDR_LOWOCM] SEG_sys_ps7_hp2_ddr_lowocm - create_bd_addr_seg -range $sys_mem_size -offset 0x00000000 [get_bd_addr_spaces axi_fmcadc3_gt/m_axi] [get_bd_addr_segs sys_ps7/S_AXI_HP3/HP3_DDR_LOWOCM] SEG_sys_ps7_hp3_ddr_lowocm -} - diff --git a/projects/fmcadc3/common/fmcadc3_spi.v b/projects/fmcadc3/common/fmcadc3_spi.v deleted file mode 100644 index a038044cf..000000000 --- a/projects/fmcadc3/common/fmcadc3_spi.v +++ /dev/null @@ -1,113 +0,0 @@ -// *************************************************************************** -// *************************************************************************** -// Copyright 2011(c) Analog Devices, Inc. -// -// All rights reserved. -// -// Redistribution and use in source and binary forms, with or without modification, -// are permitted provided that the following conditions are met: -// - Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// - Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in -// the documentation and/or other materials provided with the -// distribution. -// - Neither the name of Analog Devices, Inc. nor the names of its -// contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// - The use of this software may or may not infringe the patent rights -// of one or more patent holders. This license does not release you -// from the requirement that you obtain separate licenses from these -// patent holders to use this software. -// - Use of the software either in source or binary form, must be run -// on or directly connected to an Analog Devices Inc. component. -// -// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, -// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A -// PARTICULAR PURPOSE ARE DISCLAIMED. -// -// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, -// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY -// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR -// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, -// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF -// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// *************************************************************************** -// *************************************************************************** - -`timescale 1ns/100ps - -module daq2_spi ( - - ad9528_csn, - ad9234_1_csn, - ad9234_2_csn, - spi_clk, - spi_mosi, - spi_miso, - - spi_sdio); - - // 4 wire - - input ad9528_csn; - input ad9234_1_csn; - input ad9234_2_csn; - input spi_clk; - input spi_mosi; - output spi_miso; - - // 3 wire - - inout spi_sdio; - - // internal registers - - reg [ 5:0] spi_count = 'd0; - reg spi_rd_wr_n = 'd0; - reg spi_enable = 'd0; - - // internal signals - - wire spi_csn_s; - wire spi_enable_s; - - // check on rising edge and change on falling edge - - assign spi_csn_s = ad9528_csn & ad9234_1_csn & ad9234_2_csn; - assign spi_enable_s = spi_enable & ~spi_csn_s; - - always @(posedge spi_clk or posedge spi_csn_s) begin - if (spi_csn_s == 1'b1) begin - spi_count <= 6'd0; - spi_rd_wr_n <= 1'd0; - end else begin - spi_count <= spi_count + 1'b1; - if (spi_count == 6'd0) begin - spi_rd_wr_n <= spi_mosi; - end - end - end - - always @(negedge spi_clk or posedge spi_csn_s) begin - if (spi_csn_s == 1'b1) begin - spi_enable <= 1'b0; - end else begin - if (spi_count == 6'd16) begin - spi_enable <= spi_rd_wr_n; - end - end - end - - // io butter - - IOBUF i_iobuf_sdio ( - .T (spi_enable_s), - .I (spi_mosi), - .O (spi_miso), - .IO (spi_sdio)); - -endmodule - -// *************************************************************************** -// *************************************************************************** diff --git a/projects/fmcadc3/zc706/system_bd.tcl b/projects/fmcadc3/zc706/system_bd.tcl deleted file mode 100644 index 09cfe6587..000000000 --- a/projects/fmcadc3/zc706/system_bd.tcl +++ /dev/null @@ -1,57 +0,0 @@ - -source $ad_hdl_dir/projects/common/zc706/zc706_system_bd.tcl -source $ad_hdl_dir/projects/common/zc706/zc706_system_plddr3.tcl -source ../common/fmcadc3_bd.tcl - -set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_SRC {64}] $axi_ad9234_dma -set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_DEST {64}] $axi_ad9234_dma - -p_plddr3_fifo [current_bd_instance .] plddr3_fifo 256 - -set DDR3 [create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 DDR3] -set sys_clk [create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 sys_clk] - -connect_bd_intf_net -intf_net DDR3 [get_bd_intf_ports DDR3] [get_bd_intf_pins plddr3_fifo/DDR3] -connect_bd_intf_net -intf_net sys_clk [get_bd_intf_ports sys_clk] [get_bd_intf_pins plddr3_fifo/sys_clk] - -delete_bd_objs [get_bd_nets axi_ad9234_adc_clk] -delete_bd_objs [get_bd_nets axi_ad9234_adc_dwr] -delete_bd_objs [get_bd_nets axi_ad9234_adc_ddata] -delete_bd_objs [get_bd_nets axi_ad9234_adc_dsync] -delete_bd_objs [get_bd_nets axi_ad9234_adc_dovf] - -connect_bd_net -net [get_bd_nets axi_fmcadc3_gt_rx_rst] [get_bd_pins plddr3_fifo/adc_rst] [get_bd_pins axi_fmcadc3_gt/rx_rst] -connect_bd_net -net [get_bd_nets sys_fmc_dma_resetn] [get_bd_pins plddr3_fifo/dma_rstn] [get_bd_pins sys_fmc_dma_sync_reset/sync_resetn] -connect_bd_net -net axi_ad9234_dma_xfer_req [get_bd_pins axi_ad9234_dma/fifo_wr_xfer_req] [get_bd_pins plddr3_fifo/axi_xfer_req] - -connect_bd_net -net axi_ad9234_adc_clk [get_bd_pins axi_ad9234_core_0/adc_clk] [get_bd_pins plddr3_fifo/adc_clk] -connect_bd_net -net axi_ad9234_adc_dovf [get_bd_pins axi_ad9234_core_0/adc_dovf] [get_bd_pins plddr3_fifo/adc_wovf] -connect_bd_net -net axi_ad9234_adc_dwr [get_bd_ports adc_dwr] [get_bd_pins plddr3_fifo/adc_wr] -connect_bd_net -net axi_ad9234_adc_ddata [get_bd_ports adc_ddata] [get_bd_pins plddr3_fifo/adc_wdata] - -connect_bd_net -net axi_ad9234_dma_clk [get_bd_pins plddr3_fifo/dma_clk] [get_bd_pins axi_ad9234_dma/fifo_wr_clk] -connect_bd_net -net axi_ad9234_dma_dwr [get_bd_pins plddr3_fifo/dma_wr] [get_bd_pins axi_ad9234_dma/fifo_wr_en] -connect_bd_net -net axi_ad9234_dma_ddata [get_bd_pins plddr3_fifo/dma_wdata] [get_bd_pins axi_ad9234_dma/fifo_wr_din] -connect_bd_net -net axi_ad9234_dma_dovf [get_bd_pins plddr3_fifo/dma_wovf] [get_bd_pins axi_ad9234_dma/fifo_wr_overflow] -connect_bd_net -net axi_ad9234_adc_dsync [get_bd_ports adc_dsync] [get_bd_pins axi_ad9234_dma/fifo_wr_sync] - -connect_bd_net -net axi_ad9234_adc_clk [get_bd_ports adc_clk] -connect_bd_net -net axi_ad9234_adc_ddata [get_bd_pins ila_jesd_rx_mon/PROBE3] - -set ila_dma_mon [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:4.0 ila_dma_mon] -set_property -dict [list CONFIG.C_MONITOR_TYPE {Native}] $ila_dma_mon -set_property -dict [list CONFIG.C_NUM_OF_PROBES {4}] $ila_dma_mon -set_property -dict [list CONFIG.C_PROBE0_WIDTH {1}] $ila_dma_mon -set_property -dict [list CONFIG.C_PROBE1_WIDTH {1}] $ila_dma_mon -set_property -dict [list CONFIG.C_PROBE2_WIDTH {64}] $ila_dma_mon -set_property -dict [list CONFIG.C_PROBE3_WIDTH {5}] $ila_dma_mon - -connect_bd_net -net axi_ad9234_dma_clk [get_bd_pins ila_dma_mon/clk] -connect_bd_net -net axi_ad9234_dma_dwr [get_bd_pins ila_dma_mon/probe0] -connect_bd_net -net axi_ad9234_dma_xfer_req [get_bd_pins ila_dma_mon/probe1] -connect_bd_net -net axi_ad9234_dma_ddata [get_bd_pins ila_dma_mon/probe2] -connect_bd_net -net axi_xfer_status [get_bd_pins ila_dma_mon/probe3] [get_bd_pins plddr3_fifo/axi_xfer_status] - - -create_bd_addr_seg -range 0x40000000 -offset 0x80000000 [get_bd_addr_spaces plddr3_fifo/axi_fifo2s/axi] [get_bd_addr_segs plddr3_fifo/axi_ddr_cntrl/memmap/memaddr] SEG_axi_ddr_cntrl_memaddr - diff --git a/projects/fmcadc3/zc706/system_constr.xdc b/projects/fmcadc3/zc706/system_constr.xdc deleted file mode 100644 index 9b8b8a799..000000000 --- a/projects/fmcadc3/zc706/system_constr.xdc +++ /dev/null @@ -1,58 +0,0 @@ - -# fmcadc3 - -set_property -dict {PACKAGE_PIN AD10} [get_ports rx_ref_clk_p] ; ## D04 FMC_HPC_GBTCLK0_M2C_P -set_property -dict {PACKAGE_PIN AD9 } [get_ports rx_ref_clk_n] ; ## D05 FMC_HPC_GBTCLK0_M2C_N -set_property -dict {PACKAGE_PIN AH6 } [get_ports rx_data_p[0]] ; ## A14 FMC_HPC_DP4_M2C_P -set_property -dict {PACKAGE_PIN AH5 } [get_ports rx_data_n[0]] ; ## A15 FMC_HPC_DP4_M2C_N -set_property -dict {PACKAGE_PIN AG4 } [get_ports rx_data_p[1]] ; ## A18 FMC_HPC_DP5_M2C_P -set_property -dict {PACKAGE_PIN AG3 } [get_ports rx_data_n[1]] ; ## A19 FMC_HPC_DP5_M2C_N -set_property -dict {PACKAGE_PIN AF6 } [get_ports rx_data_p[2]] ; ## B16 FMC_HPC_DP6_M2C_P -set_property -dict {PACKAGE_PIN AF5 } [get_ports rx_data_n[2]] ; ## B17 FMC_HPC_DP6_M2C_N -set_property -dict {PACKAGE_PIN AD6 } [get_ports rx_data_p[3]] ; ## B12 FMC_HPC_DP7_M2C_P -set_property -dict {PACKAGE_PIN AD5 } [get_ports rx_data_n[3]] ; ## B13 FMC_HPC_DP7_M2C_N -set_property -dict {PACKAGE_PIN AE8 } [get_ports rx_data_p[4]] ; ## A10 FMC_HPC_DP3_M2C_P -set_property -dict {PACKAGE_PIN AE7 } [get_ports rx_data_n[4]] ; ## A11 FMC_HPC_DP3_M2C_N -set_property -dict {PACKAGE_PIN AH10} [get_ports rx_data_p[5]] ; ## C06 FMC_HPC_DP0_M2C_P -set_property -dict {PACKAGE_PIN AH9 } [get_ports rx_data_n[5]] ; ## C07 FMC_HPC_DP0_M2C_N -set_property -dict {PACKAGE_PIN AG8 } [get_ports rx_data_p[6]] ; ## A06 FMC_HPC_DP2_M2C_P -set_property -dict {PACKAGE_PIN AG7 } [get_ports rx_data_n[6]] ; ## A07 FMC_HPC_DP2_M2C_N -set_property -dict {PACKAGE_PIN AJ8 } [get_ports rx_data_p[7]] ; ## A02 FMC_HPC_DP1_M2C_P -set_property -dict {PACKAGE_PIN AJ7 } [get_ports rx_data_n[7]] ; ## A03 FMC_HPC_DP1_M2C_N -set_property -dict {PACKAGE_PIN AF23 IOSTANDARD LVDS_25} [get_ports rx_sync_0_p] ; ## G15 FMC_HPC_LA12_P -set_property -dict {PACKAGE_PIN AF24 IOSTANDARD LVDS_25} [get_ports rx_sync_0_n] ; ## G16 FMC_HPC_LA12_N -set_property -dict {PACKAGE_PIN AJ20 IOSTANDARD LVDS_25} [get_ports rx_sync_1_p] ; ## H10 FMC_HPC_LA04_P -set_property -dict {PACKAGE_PIN AK20 IOSTANDARD LVDS_25} [get_ports rx_sync_1_n] ; ## H11 FMC_HPC_LA04_N -set_property -dict {PACKAGE_PIN AG21 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_sysref_p] ; ## D08 FMC_HPC_LA01_CC_P -set_property -dict {PACKAGE_PIN AH21 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_sysref_n] ; ## D09 FMC_HPC_LA01_CC_N - -set_property -dict {PACKAGE_PIN AG19 IOSTANDARD LVCMOS25} [get_ports ad9528_csn] ; ## G13 FMC_HPC_LA08_N -set_property -dict {PACKAGE_PIN AH19 IOSTANDARD LVCMOS25} [get_ports ada4961_1a_csn] ; ## G09 FMC_HPC_LA03_P -set_property -dict {PACKAGE_PIN AJ19 IOSTANDARD LVCMOS25} [get_ports ada4961_1b_csn] ; ## G10 FMC_HPC_LA03_N -set_property -dict {PACKAGE_PIN AJ23 IOSTANDARD LVCMOS25} [get_ports ad9234_1_csn] ; ## H13 FMC_HPC_LA07_P -set_property -dict {PACKAGE_PIN AG22 IOSTANDARD LVCMOS25} [get_ports ada4961_2a_csn] ; ## C10 FMC_HPC_LA06_P -set_property -dict {PACKAGE_PIN AH22 IOSTANDARD LVCMOS25} [get_ports ada4961_2b_csn] ; ## C11 FMC_HPC_LA06_N -set_property -dict {PACKAGE_PIN AJ24 IOSTANDARD LVCMOS25} [get_ports ad9234_2_csn] ; ## H14 FMC_HPC_LA07_N -set_property -dict {PACKAGE_PIN AA23 IOSTANDARD LVCMOS25} [get_ports spi_sclk] ; ## D18 FMC_HPC_LA13_N -set_property -dict {PACKAGE_PIN AA22 IOSTANDARD LVCMOS25} [get_ports spi_sdio] ; ## D17 FMC_HPC_LA13_P - -set_property -dict {PACKAGE_PIN AE21 IOSTANDARD LVCMOS25} [get_ports ad9528_rstn] ; ## D15 FMC_HPC_LA09_N -set_property -dict {PACKAGE_PIN AD21 IOSTANDARD LVCMOS25} [get_ports ad9528_status] ; ## D14 FMC_HPC_LA09_P -set_property -dict {PACKAGE_PIN AG24 IOSTANDARD LVCMOS25} [get_ports ad9234_1_fda] ; ## C14 FMC_HPC_LA10_P -set_property -dict {PACKAGE_PIN AG25 IOSTANDARD LVCMOS25} [get_ports ad9234_1_fdb] ; ## C15 FMC_HPC_LA10_N -set_property -dict {PACKAGE_PIN AD23 IOSTANDARD LVCMOS25} [get_ports ad9234_2_fda] ; ## H16 FMC_HPC_LA11_P -set_property -dict {PACKAGE_PIN AE23 IOSTANDARD LVCMOS25} [get_ports ad9234_2_fdb] ; ## H17 FMC_HPC_LA11_N - -# clocks - -create_clock -name rx_ref_clk -period 2.00 [get_ports rx_ref_clk_p] -create_clock -name rx_div_clk -period 4.00 [get_nets i_system_wrapper/system_i/axi_fmcadc3_gt_rx_clk] -create_clock -name fmc_dma_clk -period 5.00 [get_pins i_system_wrapper/system_i/sys_ps7/FCLK_CLK2] -create_clock -name pl_ddr_clk -period 5.00 [get_pins i_system_wrapper/system_i/plddr3_fifo/axi_ddr_cntrl/ui_clk] -create_clock -name pl_dma_clk -period 15.62 [get_pins i_system_wrapper/system_i/plddr3_fifo/axi_ddr_cntrl/ui_addn_clk_0] - -set_clock_groups -asynchronous -group {rx_div_clk} -set_clock_groups -asynchronous -group {fmc_dma_clk} -set_clock_groups -asynchronous -group {pl_ddr_clk} -set_clock_groups -asynchronous -group {pl_dma_clk} - diff --git a/projects/fmcadc3/zc706/system_project.tcl b/projects/fmcadc3/zc706/system_project.tcl deleted file mode 100644 index 8df512560..000000000 --- a/projects/fmcadc3/zc706/system_project.tcl +++ /dev/null @@ -1,17 +0,0 @@ - - - -source ../../scripts/adi_env.tcl -source $ad_hdl_dir/projects/scripts/adi_project.tcl - -adi_project_create fmcadc3_zc706 -adi_project_files fmcadc3_zc706 [list \ - "../common/fmcadc3_spi.v" \ - "system_top.v" \ - "system_constr.xdc"\ - "$ad_hdl_dir/library/common/ad_iobuf.v" \ - "$ad_hdl_dir/projects/common/zc706/zc706_system_constr.xdc" ] - -adi_project_run fmcadc3_zc706 - - diff --git a/projects/fmcadc3/zc706/system_top.v b/projects/fmcadc3/zc706/system_top.v deleted file mode 100644 index 089932a70..000000000 --- a/projects/fmcadc3/zc706/system_top.v +++ /dev/null @@ -1,492 +0,0 @@ -// *************************************************************************** -// *************************************************************************** -// Copyright 2011(c) Analog Devices, Inc. -// -// All rights reserved. -// -// Redistribution and use in source and binary forms, with or without modification, -// are permitted provided that the following conditions are met: -// - Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// - Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in -// the documentation and/or other materials provided with the -// distribution. -// - Neither the name of Analog Devices, Inc. nor the names of its -// contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// - The use of this software may or may not infringe the patent rights -// of one or more patent holders. This license does not release you -// from the requirement that you obtain separate licenses from these -// patent holders to use this software. -// - Use of the software either in source or binary form, must be run -// on or directly connected to an Analog Devices Inc. component. -// -// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, -// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A -// PARTICULAR PURPOSE ARE DISCLAIMED. -// -// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, -// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY -// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR -// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, -// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF -// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// *************************************************************************** -// *************************************************************************** -// *************************************************************************** -// *************************************************************************** - -`timescale 1ns/100ps - -module system_top ( - - sys_clk_p, - sys_clk_n, - - DDR3_addr, - DDR3_ba, - DDR3_cas_n, - DDR3_ck_n, - DDR3_ck_p, - DDR3_cke, - DDR3_cs_n, - DDR3_dm, - DDR3_dq, - DDR3_dqs_n, - DDR3_dqs_p, - DDR3_odt, - DDR3_ras_n, - DDR3_reset_n, - DDR3_we_n, - - DDR_addr, - DDR_ba, - DDR_cas_n, - DDR_ck_n, - DDR_ck_p, - DDR_cke, - DDR_cs_n, - DDR_dm, - DDR_dq, - DDR_dqs_n, - DDR_dqs_p, - DDR_odt, - DDR_ras_n, - DDR_reset_n, - DDR_we_n, - - FIXED_IO_ddr_vrn, - FIXED_IO_ddr_vrp, - FIXED_IO_mio, - FIXED_IO_ps_clk, - FIXED_IO_ps_porb, - FIXED_IO_ps_srstb, - - gpio_bd, - - hdmi_out_clk, - hdmi_vsync, - hdmi_hsync, - hdmi_data_e, - hdmi_data, - - spdif, - - iic_scl, - iic_sda, - - rx_ref_clk_p, - rx_ref_clk_n, - rx_sysref_p, - rx_sysref_n, - rx_sync_0_p, - rx_sync_0_n, - rx_sync_1_p, - rx_sync_1_n, - rx_data_p, - rx_data_n, - - ad9528_rstn, - ad9528_status, - ad9234_1_fda; - ad9234_1_fdb; - ad9234_2_fda; - ad9234_2_fdb; - - ad9528_csn, - ada4961_1a_csn, - ada4961_1b_csn, - ad9234_1_csn, - ada4961_2a_csn, - ada4961_2b_csn, - ad9234_2_csn, - spi_clk, - spi_sdio); - - input sys_clk_p; - input sys_clk_n; - - output [13:0] DDR3_addr; - output [ 2:0] DDR3_ba; - output DDR3_cas_n; - output [ 0:0] DDR3_ck_n; - output [ 0:0] DDR3_ck_p; - output [ 0:0] DDR3_cke; - output [ 0:0] DDR3_cs_n; - output [ 7:0] DDR3_dm; - inout [63:0] DDR3_dq; - inout [ 7:0] DDR3_dqs_n; - inout [ 7:0] DDR3_dqs_p; - output [ 0:0] DDR3_odt; - output DDR3_ras_n; - output DDR3_reset_n; - output DDR3_we_n; - - inout [14:0] DDR_addr; - inout [ 2:0] DDR_ba; - inout DDR_cas_n; - inout DDR_ck_n; - inout DDR_ck_p; - inout DDR_cke; - inout DDR_cs_n; - inout [ 3:0] DDR_dm; - inout [31:0] DDR_dq; - inout [ 3:0] DDR_dqs_n; - inout [ 3:0] DDR_dqs_p; - inout DDR_odt; - inout DDR_ras_n; - inout DDR_reset_n; - inout DDR_we_n; - - inout FIXED_IO_ddr_vrn; - inout FIXED_IO_ddr_vrp; - inout [53:0] FIXED_IO_mio; - inout FIXED_IO_ps_clk; - inout FIXED_IO_ps_porb; - inout FIXED_IO_ps_srstb; - - inout [14:0] gpio_bd; - - output hdmi_out_clk; - output hdmi_vsync; - output hdmi_hsync; - output hdmi_data_e; - output [23:0] hdmi_data; - - output spdif; - - inout iic_scl; - inout iic_sda; - - input rx_ref_clk_p; - input rx_ref_clk_n; - input rx_sysref_p; - input rx_sysref_n; - output rx_sync_0_p; - output rx_sync_0_n; - output rx_sync_1_p; - output rx_sync_1_n; - input [ 7:0] rx_data_p; - input [ 7:0] rx_data_n; - - inout ad9528_rstn; - inout ad9528_status; - inout ad9234_1_fda; - inout ad9234_1_fdb; - inout ad9234_2_fda; - inout ad9234_2_fdb; - - output ad9528_csn; - output ada4961_1a_csn; - output ada4961_1b_csn; - output ad9234_1_csn; - output ada4961_2a_csn; - output ada4961_2b_csn; - output ad9234_2_csn; - output spi_clk; - inout spi_sdio; - - // internal registers - - reg [ 1:0] adc_dcnt = 'd0; - reg adc_dsync = 'd0; - reg adc_dwr = 'd0; - reg [255:0] adc_ddata = 'd0; - - // internal signals - - wire [37:0] gpio_i; - wire [37:0] gpio_o; - wire [37:0] gpio_t; - wire rx_ref_clk; - wire rx_sysref; - wire rx_sync; - wire spi_mosi; - wire spi_miso; - wire adc_clk; - wire [63:0] adc_data_0; - wire [63:0] adc_data_1; - wire [63:0] adc_data_2; - wire [63:0] adc_data_3; - wire adc_enable_0; - wire adc_enable_1; - wire adc_enable_2; - wire adc_enable_3; - wire adc_valid_0; - wire adc_valid_1; - wire adc_valid_2; - wire adc_valid_3; - wire [255:0] gt_data; - - // adc-pack place holder - - always @(posedge adc_clk) begin - adc_dcnt <= adc_dcnt + 1'b1; - case ({adc_enable_3, adc_enable_2, adc_enable_1, adc_enable_0}) - 4'b1111: begin - adc_dsync <= 1'b1; - adc_dwr <= adc_valid_3 & adc_valid_2 & adc_valid_1 & adc_valid_0; - adc_ddata[255:240] <= adc_data_3[63:48]; - adc_ddata[239:224] <= adc_data_2[63:48]; - adc_ddata[223:208] <= adc_data_1[63:48]; - adc_ddata[207:192] <= adc_data_0[63:48]; - adc_ddata[191:176] <= adc_data_3[47:32]; - adc_ddata[175:160] <= adc_data_2[47:32]; - adc_ddata[159:144] <= adc_data_1[47:32]; - adc_ddata[143:128] <= adc_data_0[47:32]; - adc_ddata[127:112] <= adc_data_3[31:16]; - adc_ddata[111: 96] <= adc_data_2[31:16]; - adc_ddata[ 95: 80] <= adc_data_1[31:16]; - adc_ddata[ 79: 64] <= adc_data_0[31:16]; - adc_ddata[ 63: 48] <= adc_data_3[15: 0]; - adc_ddata[ 47: 32] <= adc_data_2[15: 0]; - adc_ddata[ 31: 16] <= adc_data_1[15: 0]; - adc_ddata[ 15: 0] <= adc_data_0[15: 0]; - end - 4'b0001: begin - adc_dsync <= 1'b1; - adc_dwr <= adc_valid_0 & adc_dcnt[0] & adc_dcnt[1]; - adc_ddata[255:240] <= adc_data_0[63:48]; - adc_ddata[239:224] <= adc_data_0[47:32]; - adc_ddata[223:208] <= adc_data_0[31:16]; - adc_ddata[207:192] <= adc_data_0[15: 0]; - adc_ddata[191:176] <= adc_ddata[255:240]; - adc_ddata[175:160] <= adc_ddata[239:224]; - adc_ddata[159:144] <= adc_ddata[223:208]; - adc_ddata[143:128] <= adc_ddata[207:192]; - adc_ddata[127:112] <= adc_ddata[191:176]; - adc_ddata[111: 96] <= adc_ddata[175:160]; - adc_ddata[ 95: 80] <= adc_ddata[159:144]; - adc_ddata[ 79: 64] <= adc_ddata[143:128]; - adc_ddata[ 63: 48] <= adc_ddata[127:112]; - adc_ddata[ 47: 32] <= adc_ddata[111: 96]; - adc_ddata[ 31: 16] <= adc_ddata[ 95: 80]; - adc_ddata[ 15: 0] <= adc_ddata[ 79: 64]; - end - 4'b0010: begin - adc_dsync <= 1'b1; - adc_dwr <= adc_valid_1 & adc_dcnt[0] & adc_dcnt[1]; - adc_ddata[255:240] <= adc_data_1[63:48]; - adc_ddata[239:224] <= adc_data_1[47:32]; - adc_ddata[223:208] <= adc_data_1[31:16]; - adc_ddata[207:192] <= adc_data_1[15: 0]; - adc_ddata[191:176] <= adc_ddata[255:240]; - adc_ddata[175:160] <= adc_ddata[239:224]; - adc_ddata[159:144] <= adc_ddata[223:208]; - adc_ddata[143:128] <= adc_ddata[207:192]; - adc_ddata[127:112] <= adc_ddata[191:176]; - adc_ddata[111: 96] <= adc_ddata[175:160]; - adc_ddata[ 95: 80] <= adc_ddata[159:144]; - adc_ddata[ 79: 64] <= adc_ddata[143:128]; - adc_ddata[ 63: 48] <= adc_ddata[127:112]; - adc_ddata[ 47: 32] <= adc_ddata[111: 96]; - adc_ddata[ 31: 16] <= adc_ddata[ 95: 80]; - adc_ddata[ 15: 0] <= adc_ddata[ 79: 64]; - end - 4'b0100: begin - adc_dsync <= 1'b1; - adc_dwr <= adc_valid_2 & adc_dcnt[0] & adc_dcnt[1]; - adc_ddata[255:240] <= adc_data_2[63:48]; - adc_ddata[239:224] <= adc_data_2[47:32]; - adc_ddata[223:208] <= adc_data_2[31:16]; - adc_ddata[207:192] <= adc_data_2[15: 0]; - adc_ddata[191:176] <= adc_ddata[255:240]; - adc_ddata[175:160] <= adc_ddata[239:224]; - adc_ddata[159:144] <= adc_ddata[223:208]; - adc_ddata[143:128] <= adc_ddata[207:192]; - adc_ddata[127:112] <= adc_ddata[191:176]; - adc_ddata[111: 96] <= adc_ddata[175:160]; - adc_ddata[ 95: 80] <= adc_ddata[159:144]; - adc_ddata[ 79: 64] <= adc_ddata[143:128]; - adc_ddata[ 63: 48] <= adc_ddata[127:112]; - adc_ddata[ 47: 32] <= adc_ddata[111: 96]; - adc_ddata[ 31: 16] <= adc_ddata[ 95: 80]; - adc_ddata[ 15: 0] <= adc_ddata[ 79: 64]; - end - 4'b1000: begin - adc_dsync <= 1'b1; - adc_dwr <= adc_valid_3 & adc_dcnt[0] & adc_dcnt[1]; - adc_ddata[255:240] <= adc_data_3[63:48]; - adc_ddata[239:224] <= adc_data_3[47:32]; - adc_ddata[223:208] <= adc_data_3[31:16]; - adc_ddata[207:192] <= adc_data_3[15: 0]; - adc_ddata[191:176] <= adc_ddata[255:240]; - adc_ddata[175:160] <= adc_ddata[239:224]; - adc_ddata[159:144] <= adc_ddata[223:208]; - adc_ddata[143:128] <= adc_ddata[207:192]; - adc_ddata[127:112] <= adc_ddata[191:176]; - adc_ddata[111: 96] <= adc_ddata[175:160]; - adc_ddata[ 95: 80] <= adc_ddata[159:144]; - adc_ddata[ 79: 64] <= adc_ddata[143:128]; - adc_ddata[ 63: 48] <= adc_ddata[127:112]; - adc_ddata[ 47: 32] <= adc_ddata[111: 96]; - adc_ddata[ 31: 16] <= adc_ddata[ 95: 80]; - adc_ddata[ 15: 0] <= adc_ddata[ 79: 64]; - end - default: begin - adc_dsync <= 1'b0; - adc_dwr <= 1'b0; - adc_ddata <= 256'd0; - end - endcase - end - - // instantiations - - IBUFDS_GTE2 i_ibufds_rx_ref_clk ( - .CEB (1'd0), - .I (rx_ref_clk_p), - .IB (rx_ref_clk_n), - .O (rx_ref_clk), - .ODIV2 ()); - - IBUFDS i_ibufds_rx_sysref ( - .I (rx_sysref_p), - .IB (rx_sysref_n), - .O (rx_sysref)); - - OBUFDS i_obufds_rx_sync_0 ( - .I (rx_sync), - .O (rx_sync_0_p), - .OB (rx_sync_0_n)); - - OBUFDS i_obufds_rx_sync_1 ( - .I (rx_sync), - .O (rx_sync_1_p), - .OB (rx_sync_1_n)); - - assign ada4961_1a_csn = 1'b1; - assign ada4961_1b_csn = 1'b1; - assign ada4961_2a_csn = 1'b1; - assign ada4961_2b_csn = 1'b1; - - fmcadc3_spi i_spi ( - .ad9528_csn (ad9528_csn), - .ad9234_1_csn (ad9234_1_csn), - .ad9234_2_csn (ad9234_2_csn), - .spi_clk (spi_clk), - .spi_mosi (spi_mosi), - .spi_miso (spi_miso), - .spi_sdio (spi_sdio)); - - ad_iobuf #(.DATA_WIDTH(38)) i_iobuf ( - .dt ({gpio_t[37:32], gpio_t[14:0]}), - .di ({gpio_o[37:32], gpio_o[14:0]}), - .do ({gpio_i[37:32], gpio_i[14:0]}), - .dio ({ ad9234_2_fdb, // 37 - ad9234_2_fda, // 36 - ad9234_1_fdb, // 35 - ad9234_1_fda, // 34 - ad9528_status, // 33 - ad9528_rstn, // 32 - gpio_bd})); // 0 - - system_wrapper i_system_wrapper ( - .DDR3_addr (DDR3_addr), - .DDR3_ba (DDR3_ba), - .DDR3_cas_n (DDR3_cas_n), - .DDR3_ck_n (DDR3_ck_n), - .DDR3_ck_p (DDR3_ck_p), - .DDR3_cke (DDR3_cke), - .DDR3_cs_n (DDR3_cs_n), - .DDR3_dm (DDR3_dm), - .DDR3_dq (DDR3_dq), - .DDR3_dqs_n (DDR3_dqs_n), - .DDR3_dqs_p (DDR3_dqs_p), - .DDR3_odt (DDR3_odt), - .DDR3_ras_n (DDR3_ras_n), - .DDR3_reset_n (DDR3_reset_n), - .DDR3_we_n (DDR3_we_n), - .DDR_addr (DDR_addr), - .DDR_ba (DDR_ba), - .DDR_cas_n (DDR_cas_n), - .DDR_ck_n (DDR_ck_n), - .DDR_ck_p (DDR_ck_p), - .DDR_cke (DDR_cke), - .DDR_cs_n (DDR_cs_n), - .DDR_dm (DDR_dm), - .DDR_dq (DDR_dq), - .DDR_dqs_n (DDR_dqs_n), - .DDR_dqs_p (DDR_dqs_p), - .DDR_odt (DDR_odt), - .DDR_ras_n (DDR_ras_n), - .DDR_reset_n (DDR_reset_n), - .DDR_we_n (DDR_we_n), - .FIXED_IO_ddr_vrn (FIXED_IO_ddr_vrn), - .FIXED_IO_ddr_vrp (FIXED_IO_ddr_vrp), - .FIXED_IO_mio (FIXED_IO_mio), - .FIXED_IO_ps_clk (FIXED_IO_ps_clk), - .FIXED_IO_ps_porb (FIXED_IO_ps_porb), - .FIXED_IO_ps_srstb (FIXED_IO_ps_srstb), - .GPIO_I (gpio_i), - .GPIO_O (gpio_o), - .GPIO_T (gpio_t), - .adc_clk (adc_clk), - .adc_data_0 (adc_data_0), - .adc_data_1 (adc_data_1), - .adc_data_2 (adc_data_2), - .adc_data_3 (adc_data_3), - .adc_ddata (adc_ddata), - .adc_dsync (adc_dsync), - .adc_dwr (adc_dwr), - .adc_enable_0 (adc_enable_0), - .adc_enable_1 (adc_enable_1), - .adc_enable_2 (adc_enable_2), - .adc_enable_3 (adc_enable_3), - .adc_valid_0 (adc_valid_0), - .adc_valid_1 (adc_valid_1), - .adc_valid_2 (adc_valid_2), - .adc_valid_3 (adc_valid_3), - .gt_data (gt_data), - .gt_data_0 (gt_data[127:0]), - .gt_data_1 (gt_data[255:128]), - .hdmi_data (hdmi_data), - .hdmi_data_e (hdmi_data_e), - .hdmi_hsync (hdmi_hsync), - .hdmi_out_clk (hdmi_out_clk), - .hdmi_vsync (hdmi_vsync), - .iic_main_scl_io (iic_scl), - .iic_main_sda_io (iic_sda), - .rx_data_n (rx_data_n), - .rx_data_p (rx_data_p), - .rx_ref_clk (rx_ref_clk), - .rx_sync (rx_sync), - .rx_sysref (rx_sysref), - .spdif (spdif), - .spi_clk_i (spi_clk), - .spi_clk_o (spi_clk), - .spi_csn_0 (ad9528_csn), - .spi_csn_1 (ad9234_1_csn), - .spi_csn_2 (ad9234_2_csn), - .spi_csn_i (1'b1), - .spi_sdi_i (spi_miso), - .spi_sdo_i (spi_mosi), - .spi_sdo_o (spi_mosi), - .sys_clk_clk_n (sys_clk_n), - .sys_clk_clk_p (sys_clk_p)); - -endmodule - -// *************************************************************************** -// ***************************************************************************