zcy
/
pluto_hdl_adi
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Added axi_ad7768 IP Core (#989) 

* projects/ad7768evb: Initial commit with axi_ad7768 IP

* library/axi_ad7768: Initial commit for AD7768/AD7768-4
main
PopPaul2021 2022-08-24 16:57:14 +03:00 committed by GitHub
parent a824bbfdbe
commit cc18f90579
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
12 changed files with 1065 additions and 704 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
library/Makefile
View File

@ -16,6 +16,7 @@ clean:
$(MAKE) -C ad463x_data_capture clean
$(MAKE) -C axi_ad5766 clean
$(MAKE) -C axi_ad7616 clean
$(MAKE) -C axi_ad7768 clean
$(MAKE) -C axi_ad777x clean
$(MAKE) -C axi_ad9122 clean
$(MAKE) -C axi_ad9250 clean
@ -136,6 +137,7 @@ lib:
$(MAKE) -C ad463x_data_capture
$(MAKE) -C axi_ad5766
$(MAKE) -C axi_ad7616
$(MAKE) -C axi_ad7768
$(MAKE) -C axi_ad777x
$(MAKE) -C axi_ad9122
$(MAKE) -C axi_ad9250

32
library/axi_ad7768/Makefile Normal file
View File

@ -0,0 +1,32 @@
####################################################################################
## Copyright (c) 2018 - 2021 Analog Devices, Inc.
### SPDX short identifier: BSD-1-Clause
## Auto-generated, do not modify!
####################################################################################
LIBRARY_NAME := axi_ad7768
GENERIC_DEPS += ../common/ad_rst.v
GENERIC_DEPS += ../common/up_adc_channel.v
GENERIC_DEPS += ../common/up_adc_common.v
GENERIC_DEPS += ../common/up_axi.v
GENERIC_DEPS += ../common/up_clock_mon.v
GENERIC_DEPS += ../common/up_xfer_cntrl.v
GENERIC_DEPS += ../common/up_xfer_status.v
GENERIC_DEPS += axi_ad7768.v
GENERIC_DEPS += axi_ad7768_if.v
XILINX_DEPS += ../common/ad_datafmt.v
XILINX_DEPS += ../common/up_delay_cntrl.v
XILINX_DEPS += ../xilinx/common/ad_data_clk.v
XILINX_DEPS += ../xilinx/common/ad_data_in.v
XILINX_DEPS += ../xilinx/common/ad_dcfilter.v
XILINX_DEPS += ../xilinx/common/ad_rst_constr.xdc
XILINX_DEPS += ../xilinx/common/up_clock_mon_constr.xdc
XILINX_DEPS += ../xilinx/common/up_xfer_cntrl_constr.xdc
XILINX_DEPS += ../xilinx/common/up_xfer_status_constr.xdc
XILINX_DEPS += axi_ad7768_ip.tcl
INTEL_DEPS += axi_ad7768_hw.tcl
include ../scripts/library.mk

359
library/axi_ad7768/axi_ad7768.v Normal file
View File

@ -0,0 +1,359 @@
// ***************************************************************************
// ***************************************************************************
// Copyright 2022 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsabilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns / 1ps
module axi_ad7768 #(
parameter ID = 0,
parameter NUM_CHANNELS = 8
) (
input adc_dovf,
input clk_in,
input ready_in,
input [ 7:0] data_in,
input adc_sshot,
output adc_enable_0,
output adc_enable_1,
output adc_enable_2,
output adc_enable_3,
output adc_enable_4,
output adc_enable_5,
output adc_enable_6,
output adc_enable_7,
output adc_valid_0,
output adc_valid_1,
output adc_valid_2,
output adc_valid_3,
output adc_valid_4,
output adc_valid_5,
output adc_valid_6,
output adc_valid_7,
output [31:0] adc_data_0,
output [31:0] adc_data_1,
output [31:0] adc_data_2,
output [31:0] adc_data_3,
output [31:0] adc_data_4,
output [31:0] adc_data_5,
output [31:0] adc_data_6,
output [31:0] adc_data_7,
output [31:0] adc_data,
output adc_clk,
output adc_sync,
output adc_reset,
output adc_valid,
output [ 7:0] adc_crc_ch_mismatch,
input s_axi_aclk,
input s_axi_aresetn,
input s_axi_awvalid,
input [15:0] s_axi_awaddr,
input [ 2:0] s_axi_awprot,
output s_axi_awready,
input s_axi_wvalid,
input [31:0] s_axi_wdata,
input [ 3:0] s_axi_wstrb,
output s_axi_wready,
output s_axi_bvalid,
output [ 1:0] s_axi_bresp,
input s_axi_bready,
input s_axi_arvalid,
input [15:0] s_axi_araddr,
input [ 2:0] s_axi_arprot,
output s_axi_arready,
output s_axi_rvalid,
output [ 1:0] s_axi_rresp,
output [31:0] s_axi_rdata,
input s_axi_rready
);
// internal registers
reg [31:0] up_rdata = 'd0;
reg up_rack = 'd0;
reg up_wack = 'd0;
reg [31:0] up_rdata_r;
reg up_rack_r;
reg up_wack_r;
// internal signals
wire adc_rst_s;
wire up_rstn;
wire up_clk;
wire [13:0] up_waddr_s;
wire [13:0] up_raddr_s;
wire adc_clk_s;
wire up_wreq_s;
wire up_rreq_s;
wire [13:0] up_addr_s;
wire [31:0] up_wdata_s;
wire [31:0] up_rdata_s[0:8];
wire [8:0] up_rack_s;
wire [8:0] up_wack_s;
wire [7:0] adc_enable;
wire [4:0] adc_num_lanes;
wire adc_crc_enable;
wire [7:0] adc_status_header[0:7];
wire [7:0] adc_crc_err;
assign up_clk = s_axi_aclk;
assign up_rstn = s_axi_aresetn;
assign adc_clk = adc_clk_s;
assign adc_reset = adc_rst_s;
assign adc_enable_0 = adc_enable[0];
assign adc_enable_1 = adc_enable[1];
assign adc_enable_2 = adc_enable[2];
assign adc_enable_3 = adc_enable[3];
assign adc_enable_4 = adc_enable[4];
assign adc_enable_5 = adc_enable[5];
assign adc_enable_6 = adc_enable[6];
assign adc_enable_7 = adc_enable[7];
assign adc_valid_0 = adc_valid;
assign adc_valid_1 = adc_valid;
assign adc_valid_2 = adc_valid;
assign adc_valid_3 = adc_valid;
assign adc_valid_4 = adc_valid;
assign adc_valid_5 = adc_valid;
assign adc_valid_6 = adc_valid;
assign adc_valid_7 = adc_valid;
assign adc_crc_ch_mismatch = adc_crc_err;
integer j;
always @(*) begin
up_rdata_r = 'h00;
up_rack_r = 'h00;
up_wack_r = 'h00;
for (j = 0; j <= 8; j=j+1) begin
up_rack_r = up_rack_r | up_rack_s[j];
up_wack_r = up_wack_r | up_wack_s[j];
up_rdata_r = up_rdata_r | up_rdata_s[j];
end
end
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_rdata <= 'd0;
up_rack <= 'd0;
up_wack <= 'd0;
end else begin
up_rdata <= up_rdata_r;
up_rack <= up_rack_r;
up_wack <= up_wack_r;
end
end
// adc channels
generate
genvar i;
for (i = 0; i < NUM_CHANNELS; i=i+1) begin : ad7768_channels
up_adc_channel #(
.CHANNEL_ID(i)
) i_up_adc_channel (
.adc_clk (adc_clk_s),
.adc_rst (adc_rst_s),
.adc_enable (adc_enable[i]),
.adc_iqcor_enb (),
.adc_dcfilt_enb (),
.adc_dfmt_se (),
.adc_dfmt_type (),
.adc_dfmt_enable (),
.adc_dcfilt_offset (),
.adc_dcfilt_coeff (),
.adc_iqcor_coeff_1 (),
.adc_iqcor_coeff_2 (),
.adc_pnseq_sel (),
.adc_data_sel (),
.adc_pn_err (1'b0),
.adc_pn_oos (1'b0),
.adc_or (1'b0),
.adc_status_header(adc_status_header[i]),
.adc_crc_err(adc_crc_err[i]),
.up_adc_pn_err (),
.up_adc_pn_oos (),
.up_adc_or (),
.up_usr_datatype_be (),
.up_usr_datatype_signed (),
.up_usr_datatype_shift (),
.up_usr_datatype_total_bits (),
.up_usr_datatype_bits (),
.up_usr_decimation_m (),
.up_usr_decimation_n (),
.adc_usr_datatype_be (1'b0),
.adc_usr_datatype_signed (1'b1),
.adc_usr_datatype_shift (8'd0),
.adc_usr_datatype_total_bits (8'd32),
.adc_usr_datatype_bits (8'd32),
.adc_usr_decimation_m (16'd1),
.adc_usr_decimation_n (16'd1),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (up_wack_s[i]),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (up_rdata_s[i]),
.up_rack (up_rack_s[i]));
end
endgenerate
// adc interface
axi_ad7768_if #(
.NUM_CHANNELS(NUM_CHANNELS)
) i_ad7768_if (
.clk_in (clk_in),
.ready_in (ready_in),
.data_in (data_in),
.adc_clk (adc_clk_s),
.adc_valid (adc_valid),
.adc_data (adc_data),
.adc_sshot(adc_sshot),
.adc_format(adc_num_lanes),
.adc_crc_enable(adc_crc_enable),
.adc_sync(adc_sync),
.adc_data_0 (adc_data_0),
.adc_data_1 (adc_data_1),
.adc_data_2 (adc_data_2),
.adc_data_3 (adc_data_3),
.adc_data_4 (adc_data_4),
.adc_data_5 (adc_data_5),
.adc_data_6 (adc_data_6),
.adc_data_7 (adc_data_7),
.adc_crc_ch_mismatch(adc_crc_err),
.adc_status_0(adc_status_header[0]),
.adc_status_1(adc_status_header[1]),
.adc_status_2(adc_status_header[2]),
.adc_status_3(adc_status_header[3]),
.adc_status_4(adc_status_header[4]),
.adc_status_5(adc_status_header[5]),
.adc_status_6(adc_status_header[6]),
.adc_status_7(adc_status_header[7]));
// adc up common
up_adc_common #(
.ID(ID)
) i_up_adc_common (
.mmcm_rst (),
.adc_clk (adc_clk_s),
.adc_rst (adc_rst_s),
.adc_r1_mode (),
.adc_ddr_edgesel (),
.adc_pin_mode (),
.adc_status ('h00),
.adc_sync_status (1'b1),
.adc_status_ovf (adc_dovf),
.adc_clk_ratio (32'd1),
.adc_start_code (),
.adc_sref_sync (),
.adc_sync (),
.adc_ext_sync_arm(),
.adc_ext_sync_disarm(),
.adc_ext_sync_manual_req(),
.adc_custom_control(),
.adc_sdr_ddr_n(),
.adc_symb_op(),
.adc_symb_8_16b(),
.adc_num_lanes(adc_num_lanes),
.adc_crc_enable(adc_crc_enable),
.up_pps_rcounter (32'b0),
.up_pps_status (1'b0),
.up_pps_irq_mask (),
.up_adc_ce (),
.up_status_pn_err (1'b0),
.up_status_pn_oos (1'b0),
.up_status_or (1'b0),
.up_adc_r1_mode(),
.up_drp_sel (),
.up_drp_wr (),
.up_drp_addr (),
.up_drp_wdata (),
.up_drp_rdata (32'd0),
.up_drp_ready (1'd0),
.up_drp_locked (1'd1),
.up_usr_chanmax_out (),
.up_usr_chanmax_in (NUM_CHANNELS),
.up_adc_gpio_in (32'b0),
.up_adc_gpio_out (),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (up_wack_s[NUM_CHANNELS]),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (up_rdata_s[NUM_CHANNELS]),
.up_rack (up_rack_s[NUM_CHANNELS]));
// up bus interface
up_axi i_up_axi (
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_axi_awvalid (s_axi_awvalid),
.up_axi_awaddr (s_axi_awaddr),
.up_axi_awready (s_axi_awready),
.up_axi_wvalid (s_axi_wvalid),
.up_axi_wdata (s_axi_wdata),
.up_axi_wstrb (s_axi_wstrb),
.up_axi_wready (s_axi_wready),
.up_axi_bvalid (s_axi_bvalid),
.up_axi_bresp (s_axi_bresp),
.up_axi_bready (s_axi_bready),
.up_axi_arvalid (s_axi_arvalid),
.up_axi_araddr (s_axi_araddr),
.up_axi_arready (s_axi_arready),
.up_axi_rvalid (s_axi_rvalid),
.up_axi_rresp (s_axi_rresp),
.up_axi_rdata (s_axi_rdata),
.up_axi_rready (s_axi_rready),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (up_wack),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (up_rdata),
.up_rack (up_rack));
endmodule

78
library/axi_ad7768/axi_ad7768_hw.tcl Normal file
View File

@ -0,0 +1,78 @@
package require qsys
source ../../scripts/adi_env.tcl
source ../scripts/adi_ip_intel.tcl
set_module_property NAME axi_ad7768
set_module_property DESCRIPTION "AXI AD7768 IP core"
set_module_property VERSION 1.0
set_module_property GROUP "Analog Devices"
set_module_property DISPLAY_NAME axi_ad7768
set_module_property ELABORATION_CALLBACK create_ports
# source files
ad_ip_files axi_ad7768 [list \
"$ad_hdl_dir/library/common/ad_rst.v" \
"$ad_hdl_dir/library/common/up_adc_channel.v" \
"$ad_hdl_dir/library/common/up_adc_common.v" \
"$ad_hdl_dir/library/common/up_axi.v" \
"$ad_hdl_dir/library/common/up_clock_mon.v" \
"$ad_hdl_dir/library/common/up_xfer_cntrl.v" \
"$ad_hdl_dir/library/common/up_xfer_status.v" \
"axi_ad7768_if.v" \
"axi_ad7768.v"]
# IP parameters
add_parameter ID INTEGER 0
set_parameter_property ID DEFAULT_VALUE 0
set_parameter_property ID DISPLAY_NAME "ID"
set_parameter_property ID UNITS None
set_parameter_property ID HDL_PARAMETER true
set group "General Configuration"
ad_ip_parameter NUM_CHANNELS INTEGER 8 true [list \
DISPLAY_NAME "Number of channels" \
DISPLAY_UNITS "channels" \
ALLOWED_RANGES {4 8} \
GROUP $group \
]
# AXI4 Memory Mapped Interface
ad_ip_intf_s_axi s_axi_aclk s_axi_aresetn 15
# ad7768_if and axi_gpreg ports
ad_interface signal adc_dovf input 1 ovf
ad_interface signal clk_in input 1
ad_interface signal ready_in input 1
ad_interface signal data_in input 8
ad_interface reset adc_reset output 1
ad_interface clock adc_clk output 1
ad_interface signal adc_sync output 1 sync
ad_interface signal adc_valid output 1 valid
ad_interface signal adc_data output 32 data
set_interface_property if_adc_reset associatedClock if_adc_clk
proc create_ports {} {
set num_channels [get_parameter_value "NUM_CHANNELS"]
set samples_per_channel 1
set sample_data_width 32
set channel_data_width [expr $sample_data_width * $samples_per_channel]
for {set n 0} {$n < $num_channels} {incr n} {
add_interface adc_ch_$n conduit end
add_interface_port adc_ch_$n adc_enable_$n enable Output 1
add_interface_port adc_ch_$n adc_data_$n data Output $sample_data_width
add_interface_port adc_ch_$n adc_valid_$n valid Output 1
set_interface_property adc_ch_$n associatedClock if_adc_clk
set_interface_property adc_ch_$n associatedReset none
}
}

489
library/axi_ad7768/axi_ad7768_if.v Normal file
View File

@ -0,0 +1,489 @@
// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2022 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module axi_ad7768_if #(
parameter NUM_CHANNELS = 8
) (
// device-interface
input clk_in,
input ready_in,
input [ 7:0] data_in,
// data path interface
output adc_clk,
output adc_valid,
output [ 31:0] adc_data,
output adc_sync,
output [ 31:0] adc_data_0,
output [ 31:0] adc_data_1,
output [ 31:0] adc_data_2,
output [ 31:0] adc_data_3,
output [ 31:0] adc_data_4,
output [ 31:0] adc_data_5,
output [ 31:0] adc_data_6,
output [ 31:0] adc_data_7,
output [ 7:0] adc_status_0,
output [ 7:0] adc_status_1,
output [ 7:0] adc_status_2,
output [ 7:0] adc_status_3,
output [ 7:0] adc_status_4,
output [ 7:0] adc_status_5,
output [ 7:0] adc_status_6,
output [ 7:0] adc_status_7,
output [ 7:0] adc_crc_ch_mismatch,
// control interface
input adc_sshot,
input [ 4:0] adc_format,
input adc_crc_enable
);
// internal registers
reg [ 95:0] adc_crc_data_s [0:7];
reg [ 7:0] adc_crc_read_data [0:7];
reg [ 7:0] adc_crc_reg [0:7];
reg [ 31:0] adc_data_s_d [0:7];
reg [ 31:0] adc_data_s [0:7];
reg [ 31:0] adc_data_int = 'd0;
reg [ 3:0] adc_crc_cnt = 'd0;
reg [ 8:0] adc_cnt_p = 'd0;
reg [255:0] adc_data_p = 'd0;
reg [255:0] adc_ch_data_d0 = 'd0;
reg [255:0] adc_ch_data_d1 = 'd0;
reg [255:0] adc_ch_data_d2 = 'd0;
reg [255:0] adc_ch_data_d3 = 'd0;
reg [255:0] adc_ch_data_d4 = 'd0;
reg [255:0] adc_ch_data_d5 = 'd0;
reg [255:0] adc_ch_data_d6 = 'd0;
reg [255:0] adc_ch_data_d7 = 'd0;
reg [ 7:0] adc_status_0_s = 'd0;
reg [ 7:0] adc_status_1_s = 'd0;
reg [ 7:0] adc_status_2_s = 'd0;
reg [ 7:0] adc_status_3_s = 'd0;
reg [ 7:0] adc_status_4_s = 'd0;
reg [ 7:0] adc_status_5_s = 'd0;
reg [ 7:0] adc_status_6_s = 'd0;
reg [ 7:0] adc_status_7_s = 'd0;
reg [ 7:0] adc_crc_ch_mismatch_s = 'd0;
reg adc_valid_s = 'b0;
reg adc_valid_s_d = 'b0;
reg adc_crc_valid_p = 'b0;
reg sync_ss = 'd0;
reg adc_valid_p = 'd0;
reg adc_ready = 'd0;
// internal signals
wire [ 7:0] adc_crc_in_s [0:7];
wire [ 7:0] adc_crc_s [0:7];
wire [ 3:0] adc_crc_cnt_value;
wire [ 8:0] adc_cnt_value;
wire [ 7:0] adc_crc_mismatch_s;
wire adc_crc_cnt_enable_s;
wire adc_cnt_enable_s;
wire adc_ready_in_s;
wire crc_in_sync_n;
// function (crc8)
function [ 7:0] crc8;
input [95:0] din;
input [ 7:0] cin;
reg [ 7:0] cout;
begin
cout[0] = cin[0] ^ cin[2] ^ cin[4] ^ cin[5] ^ cin[6] ^ din[0] ^ din[6] ^ din[7] ^ din[8] ^ din[12] ^ din[14] ^ din[16] ^
din[18] ^ din[19] ^ din[21] ^ din[23] ^ din[28] ^ din[30] ^ din[31] ^ din[34] ^ din[35] ^ din[39] ^ din[40] ^ din[43] ^
din[45] ^ din[48] ^ din[49] ^ din[50] ^ din[52] ^ din[53] ^ din[54] ^ din[56] ^ din[60] ^ din[63] ^ din[64] ^ din[66] ^
din[67] ^ din[68] ^ din[69] ^ din[74] ^ din[75] ^ din[77] ^ din[80] ^ din[84] ^ din[85] ^ din[86] ^ din[87] ^ din[88] ^
din[90] ^ din[92] ^ din[93] ^ din[94];
cout[1] = cin[1] ^ cin[2] ^ cin[3] ^ cin[4] ^ cin[7] ^ din[0] ^ din[1] ^ din[6] ^ din[9] ^ din[12] ^ din[13] ^ din[14] ^
din[15] ^ din[16] ^ din[17] ^ din[18] ^ din[20] ^ din[21] ^ din[22] ^ din[23] ^ din[24] ^ din[28] ^ din[29] ^ din[30] ^
din[32] ^ din[34] ^ din[36] ^ din[39] ^ din[41] ^ din[43] ^ din[44] ^ din[45] ^ din[46] ^ din[48] ^ din[51] ^ din[52] ^
din[55] ^ din[56] ^ din[57] ^ din[60] ^ din[61] ^ din[63] ^ din[65] ^ din[66] ^ din[70] ^ din[74] ^ din[76] ^ din[77] ^
din[78] ^ din[80] ^ din[81] ^ din[84] ^ din[89] ^ din[90] ^ din[91] ^ din[92] ^ din[95];
cout[2] = cin[0] ^ cin[3] ^ cin[6] ^ din[0] ^ din[1] ^ din[2] ^ din[6] ^ din[8] ^ din[10] ^ din[12] ^ din[13] ^ din[15] ^
din[17] ^ din[22] ^ din[24] ^ din[25] ^ din[28] ^ din[29] ^ din[33] ^ din[34] ^ din[37] ^ din[39] ^ din[42] ^ din[43] ^
din[44] ^ din[46] ^ din[47] ^ din[48] ^ din[50] ^ din[54] ^ din[57] ^ din[58] ^ din[60] ^ din[61] ^ din[62] ^ din[63] ^
din[68] ^ din[69] ^ din[71] ^ din[74] ^ din[78] ^ din[79] ^ din[80] ^ din[81] ^ din[82] ^ din[84] ^ din[86] ^ din[87] ^
din[88] ^ din[91] ^ din[94];
cout[3] = cin[0] ^ cin[1] ^ cin[4] ^ cin[7] ^ din[1] ^ din[2] ^ din[3] ^ din[7] ^ din[9] ^ din[11] ^ din[13] ^ din[14] ^
din[16] ^ din[18] ^ din[23] ^ din[25] ^ din[26] ^ din[29] ^ din[30] ^ din[34] ^ din[35] ^ din[38] ^ din[40] ^ din[43] ^
din[44] ^ din[45] ^ din[47] ^ din[48] ^ din[49] ^ din[51] ^ din[55] ^ din[58] ^ din[59] ^ din[61] ^ din[62] ^ din[63] ^
din[64] ^ din[69] ^ din[70] ^ din[72] ^ din[75] ^ din[79] ^ din[80] ^ din[81] ^ din[82] ^ din[83] ^ din[85] ^ din[87] ^
din[88] ^ din[89] ^ din[92] ^ din[95];
cout[4] = cin[0] ^ cin[1] ^ cin[2] ^ cin[5] ^ din[2] ^ din[3] ^ din[4] ^ din[8] ^ din[10] ^ din[12] ^ din[14] ^ din[15] ^
din[17] ^ din[19] ^ din[24] ^ din[26] ^ din[27] ^ din[30] ^ din[31] ^ din[35] ^ din[36] ^ din[39] ^ din[41] ^ din[44] ^
din[45] ^ din[46] ^ din[48] ^ din[49] ^ din[50] ^ din[52] ^ din[56] ^ din[59] ^ din[60] ^ din[62] ^ din[63] ^ din[64] ^
din[65] ^ din[70] ^ din[71] ^ din[73] ^ din[76] ^ din[80] ^ din[81] ^ din[82] ^ din[83] ^ din[84] ^ din[86] ^ din[88] ^
din[89] ^ din[90] ^ din[93];
cout[5] = cin[1] ^ cin[2] ^ cin[3] ^ cin[6] ^ din[3] ^ din[4] ^ din[5] ^ din[9] ^ din[11] ^ din[13] ^ din[15] ^ din[16] ^
din[18] ^ din[20] ^ din[25] ^ din[27] ^ din[28] ^ din[31] ^ din[32] ^ din[36] ^ din[37] ^ din[40] ^ din[42] ^ din[45] ^
din[46] ^ din[47] ^ din[49] ^ din[50] ^ din[51] ^ din[53] ^ din[57] ^ din[60] ^ din[61] ^ din[63] ^ din[64] ^ din[65] ^
din[66] ^ din[71] ^ din[72] ^ din[74] ^ din[77] ^ din[81] ^ din[82] ^ din[83] ^ din[84] ^ din[85] ^ din[87] ^ din[89] ^
din[90] ^ din[91] ^ din[94];
cout[6] = cin[0] ^ cin[2] ^ cin[3] ^ cin[4] ^ cin[7] ^ din[4] ^ din[5] ^ din[6] ^ din[10] ^ din[12] ^ din[14] ^ din[16] ^
din[17] ^ din[19] ^ din[21] ^ din[26] ^ din[28] ^ din[29] ^ din[32] ^ din[33] ^ din[37] ^ din[38] ^ din[41] ^ din[43] ^
din[46] ^ din[47] ^ din[48] ^ din[50] ^ din[51] ^ din[52] ^ din[54] ^ din[58] ^ din[61] ^ din[62] ^ din[64] ^ din[65] ^
din[66] ^ din[67] ^ din[72] ^ din[73] ^ din[75] ^ din[78] ^ din[82] ^ din[83] ^ din[84] ^ din[85] ^ din[86] ^ din[88] ^
din[90] ^ din[91] ^ din[92] ^ din[95];
cout[7] = cin[1] ^ cin[3] ^ cin[4] ^ cin[5] ^ din[5] ^ din[6] ^ din[7] ^ din[11] ^ din[13] ^ din[15] ^ din[17] ^ din[18] ^
din[20] ^ din[22] ^ din[27] ^ din[29] ^ din[30] ^ din[33] ^ din[34] ^ din[38] ^ din[39] ^ din[42] ^ din[44] ^ din[47] ^
din[48] ^ din[49] ^ din[51] ^ din[52] ^ din[53] ^ din[55] ^ din[59] ^ din[62] ^ din[63] ^ din[65] ^ din[66] ^ din[67] ^
din[68] ^ din[73] ^ din[74] ^ din[76] ^ din[79] ^ din[83] ^ din[84] ^ din[85] ^ din[86] ^ din[87] ^ din[89] ^ din[91] ^
din[92] ^ din[93];
crc8 = cout;
end
endfunction
assign adc_ready_in_s = ready_in;
assign adc_clk = clk_in;
assign adc_valid = adc_valid_s_d;
assign adc_data= adc_data_int;
assign adc_data_0 = adc_data_s_d[0];
assign adc_data_1 = adc_data_s_d[1];
assign adc_data_2 = adc_data_s_d[2];
assign adc_data_3 = adc_data_s_d[3];
assign adc_data_4 = adc_data_s_d[4];
assign adc_data_5 = adc_data_s_d[5];
assign adc_data_6 = adc_data_s_d[6];
assign adc_data_7 = adc_data_s_d[7];
assign adc_status_0 = adc_status_0_s;
assign adc_status_1 = adc_status_1_s;
assign adc_status_2 = adc_status_2_s;
assign adc_status_3 = adc_status_3_s;
assign adc_status_4 = adc_status_4_s;
assign adc_status_5 = adc_status_5_s;
assign adc_status_6 = adc_status_6_s;
assign adc_status_7 = adc_status_7_s;
assign adc_crc_ch_mismatch = adc_crc_ch_mismatch_s;
assign crc_in_sync_n = |adc_crc_mismatch_s;
// CRC check
assign adc_crc_mismatch_s[0] = (adc_crc_read_data[0] == adc_crc_s[0]) ? 1'b0 : adc_crc_enable;
assign adc_crc_mismatch_s[1] = (adc_crc_read_data[1] == adc_crc_s[1]) ? 1'b0 : adc_crc_enable;
assign adc_crc_mismatch_s[2] = (adc_crc_read_data[2] == adc_crc_s[2]) ? 1'b0 : adc_crc_enable;
assign adc_crc_mismatch_s[3] = (adc_crc_read_data[3] == adc_crc_s[3]) ? 1'b0 : adc_crc_enable;
assign adc_crc_mismatch_s[4] = (adc_crc_read_data[4] == adc_crc_s[4] || NUM_CHANNELS == 4) ? 1'b0 : adc_crc_enable;
assign adc_crc_mismatch_s[5] = (adc_crc_read_data[5] == adc_crc_s[5] || NUM_CHANNELS == 4) ? 1'b0 : adc_crc_enable;
assign adc_crc_mismatch_s[6] = (adc_crc_read_data[6] == adc_crc_s[6] || NUM_CHANNELS == 4) ? 1'b0 : adc_crc_enable;
assign adc_crc_mismatch_s[7] = (adc_crc_read_data[7] == adc_crc_s[7] || NUM_CHANNELS == 4) ? 1'b0 : adc_crc_enable;
assign adc_crc_s[0] = crc8(adc_crc_data_s[0], adc_crc_in_s[0]);
assign adc_crc_s[1] = crc8(adc_crc_data_s[1], adc_crc_in_s[1]);
assign adc_crc_s[2] = crc8(adc_crc_data_s[2], adc_crc_in_s[2]);
assign adc_crc_s[3] = crc8(adc_crc_data_s[3], adc_crc_in_s[3]);
assign adc_crc_s[4] = crc8(adc_crc_data_s[4], adc_crc_in_s[4]);
assign adc_crc_s[5] = crc8(adc_crc_data_s[5], adc_crc_in_s[5]);
assign adc_crc_s[6] = crc8(adc_crc_data_s[6], adc_crc_in_s[6]);
assign adc_crc_s[7] = crc8(adc_crc_data_s[7], adc_crc_in_s[7]);
assign adc_crc_in_s[0] = (adc_crc_enable == 'd1) ? 8'hff : adc_crc_reg[0];
assign adc_crc_in_s[1] = (adc_crc_enable == 'd1) ? 8'hff : adc_crc_reg[1];
assign adc_crc_in_s[2] = (adc_crc_enable == 'd1) ? 8'hff : adc_crc_reg[2];
assign adc_crc_in_s[3] = (adc_crc_enable == 'd1) ? 8'hff : adc_crc_reg[3];
assign adc_crc_in_s[4] = (adc_crc_enable == 'd1) ? 8'hff : adc_crc_reg[4];
assign adc_crc_in_s[5] = (adc_crc_enable == 'd1) ? 8'hff : adc_crc_reg[5];
assign adc_crc_in_s[6] = (adc_crc_enable == 'd1) ? 8'hff : adc_crc_reg[6];
assign adc_crc_in_s[7] = (adc_crc_enable == 'd1) ? 8'hff : adc_crc_reg[7];
assign adc_sync = adc_valid_s & ~adc_valid_s_d & sync_ss;
// serial output data
always @(posedge adc_clk) begin
if (adc_valid_s) begin
sync_ss <= 1'h1;
end else if (adc_sync) begin
sync_ss <= 1'h0;
end
adc_data_int <= adc_ch_data_d0[((32*0)+31):(32*0)] | adc_ch_data_d1[((32*1)+31):(32*1)] | adc_ch_data_d2[((32*2)+31):(32*2)] |
adc_ch_data_d3[((32*3)+31):(32*3)] | adc_ch_data_d4[((32*4)+31):(32*4)] | adc_ch_data_d5[((32*5)+31):(32*5)] |
adc_ch_data_d6[((32*6)+31):(32*6)] | adc_ch_data_d7[((32*7)+31):(32*7)];
adc_ch_data_d0 <= {adc_ch_data_d0[((32*6)+31):(32*0)],adc_data_s[0]};
adc_ch_data_d1 <= {adc_ch_data_d1[((32*6)+31):(32*0)],adc_data_s[1]};
adc_ch_data_d2 <= {adc_ch_data_d2[((32*6)+31):(32*0)],adc_data_s[2]};
adc_ch_data_d3 <= {adc_ch_data_d3[((32*6)+31):(32*0)],adc_data_s[3]};
adc_ch_data_d4 <= {adc_ch_data_d4[((32*6)+31):(32*0)],adc_data_s[4]};
adc_ch_data_d5 <= {adc_ch_data_d5[((32*6)+31):(32*0)],adc_data_s[5]};
adc_ch_data_d6 <= {adc_ch_data_d6[((32*6)+31):(32*0)],adc_data_s[6]};
adc_ch_data_d7 <= {adc_ch_data_d7[((32*6)+31):(32*0)],adc_data_s[7]};
end
always @(posedge adc_clk) begin
adc_status_0_s <= (adc_valid_s == 1'b1 ) ? adc_data_s[0][31:24]: adc_status_0_s;
adc_status_1_s <= (adc_valid_s == 1'b1 ) ? adc_data_s[1][31:24]: adc_status_1_s;
adc_status_2_s <= (adc_valid_s == 1'b1 ) ? adc_data_s[2][31:24]: adc_status_2_s;
adc_status_3_s <= (adc_valid_s == 1'b1 ) ? adc_data_s[3][31:24]: adc_status_3_s;
adc_status_4_s <= (adc_valid_s == 1'b1 ) ? adc_data_s[4][31:24]: adc_status_4_s;
adc_status_5_s <= (adc_valid_s == 1'b1 ) ? adc_data_s[5][31:24]: adc_status_5_s;
adc_status_6_s <= (adc_valid_s == 1'b1 ) ? adc_data_s[6][31:24]: adc_status_6_s;
adc_status_7_s <= (adc_valid_s == 1'b1 ) ? adc_data_s[7][31:24]: adc_status_7_s;
adc_crc_ch_mismatch_s[0] <= (adc_crc_valid_p == 1'b1 ) ? adc_crc_mismatch_s[0] : adc_crc_ch_mismatch_s[0];
adc_crc_ch_mismatch_s[1] <= (adc_crc_valid_p == 1'b1 ) ? adc_crc_mismatch_s[1] : adc_crc_ch_mismatch_s[1];
adc_crc_ch_mismatch_s[2] <= (adc_crc_valid_p == 1'b1 ) ? adc_crc_mismatch_s[2] : adc_crc_ch_mismatch_s[2];
adc_crc_ch_mismatch_s[3] <= (adc_crc_valid_p == 1'b1 ) ? adc_crc_mismatch_s[3] : adc_crc_ch_mismatch_s[3];
adc_crc_ch_mismatch_s[4] <= (adc_crc_valid_p == 1'b1 ) ? adc_crc_mismatch_s[4] : adc_crc_ch_mismatch_s[4];
adc_crc_ch_mismatch_s[5] <= (adc_crc_valid_p == 1'b1 ) ? adc_crc_mismatch_s[5] : adc_crc_ch_mismatch_s[5];
adc_crc_ch_mismatch_s[6] <= (adc_crc_valid_p == 1'b1 ) ? adc_crc_mismatch_s[6] : adc_crc_ch_mismatch_s[6];
adc_crc_ch_mismatch_s[7] <= (adc_crc_valid_p == 1'b1 ) ? adc_crc_mismatch_s[7] : adc_crc_ch_mismatch_s[7];
end
// 4 samples counter for crc
assign adc_crc_cnt_value = 4'h4;
assign adc_crc_cnt_enable_s = (adc_crc_cnt < adc_crc_cnt_value) ? 1'b1 : 1'b0;
always @(posedge adc_clk) begin
if ( (crc_in_sync_n == 1'b0) || (adc_crc_enable == 1'b0) || (adc_crc_cnt_enable_s ==1'b0)) begin
adc_crc_cnt <= 4'd0;
end else if ( (adc_valid_p == 1'b1) && (adc_crc_enable == 1'b1)) begin
adc_crc_cnt <= adc_crc_cnt + 1'b1;
end
if (adc_crc_cnt == adc_crc_cnt_value ) begin
adc_crc_valid_p <= 1'b1;
end else begin
adc_crc_valid_p <= 1'b0;
end
end
// capturing crc data
always @(posedge adc_clk) begin
if(adc_valid_s == 1'b1 ) begin
adc_crc_data_s[0] <= {adc_crc_data_s[0][71:0],adc_data_s[0][23:0]};
adc_crc_data_s[1] <= {adc_crc_data_s[1][71:0],adc_data_s[1][23:0]};
adc_crc_data_s[2] <= {adc_crc_data_s[2][71:0],adc_data_s[2][23:0]};
adc_crc_data_s[3] <= {adc_crc_data_s[3][71:0],adc_data_s[3][23:0]};
adc_crc_data_s[4] <= {adc_crc_data_s[4][71:0],adc_data_s[4][23:0]};
adc_crc_data_s[5] <= {adc_crc_data_s[5][71:0],adc_data_s[5][23:0]};
adc_crc_data_s[6] <= {adc_crc_data_s[6][71:0],adc_data_s[6][23:0]};
adc_crc_data_s[7] <= {adc_crc_data_s[7][71:0],adc_data_s[7][23:0]};
adc_crc_read_data[0] <=adc_data_s[0][31:24];
adc_crc_read_data[1] <=adc_data_s[1][31:24];
adc_crc_read_data[2] <=adc_data_s[2][31:24];
adc_crc_read_data[3] <=adc_data_s[3][31:24];
adc_crc_read_data[4] <=adc_data_s[4][31:24];
adc_crc_read_data[5] <=adc_data_s[5][31:24];
adc_crc_read_data[6] <=adc_data_s[6][31:24];
adc_crc_read_data[7] <=adc_data_s[7][31:24];
adc_crc_reg[0] <= adc_crc_s[0];
adc_crc_reg[1] <= adc_crc_s[1];
adc_crc_reg[2] <= adc_crc_s[2];
adc_crc_reg[3] <= adc_crc_s[3];
adc_crc_reg[4] <= adc_crc_s[4];
adc_crc_reg[5] <= adc_crc_s[5];
adc_crc_reg[6] <= adc_crc_s[6];
adc_crc_reg[7] <= adc_crc_s[7];
end else begin
adc_crc_data_s[0] <= adc_crc_data_s[0];
adc_crc_data_s[1] <= adc_crc_data_s[1];
adc_crc_data_s[2] <= adc_crc_data_s[2];
adc_crc_data_s[3] <= adc_crc_data_s[3];
adc_crc_data_s[4] <= adc_crc_data_s[4];
adc_crc_data_s[5] <= adc_crc_data_s[5];
adc_crc_data_s[6] <= adc_crc_data_s[6];
adc_crc_data_s[7] <= adc_crc_data_s[7];
adc_crc_read_data[0] <= 8'b0;
adc_crc_read_data[1] <= 8'b0;
adc_crc_read_data[2] <= 8'b0;
adc_crc_read_data[3] <= 8'b0;
adc_crc_read_data[4] <= 8'b0;
adc_crc_read_data[5] <= 8'b0;
adc_crc_read_data[6] <= 8'b0;
adc_crc_read_data[7] <= 8'b0;
adc_crc_reg[0] <= 'b0;
adc_crc_reg[1] <= 'b0;
adc_crc_reg[2] <= 'b0;
adc_crc_reg[3] <= 'b0;
adc_crc_reg[4] <= 'b0;
adc_crc_reg[5] <= 'b0;
adc_crc_reg[6] <= 'b0;
adc_crc_reg[7] <= 'b0;
end
end
// data capturing counter
assign adc_cnt_value = (adc_format == 'h0 && NUM_CHANNELS == 8 ) ? 'hff :
(( adc_format == 'h1 || (adc_format == 'h0 && NUM_CHANNELS == 4 )) ? 'h7f : 'h1f );
assign adc_cnt_enable_s = (adc_cnt_p < adc_cnt_value) ? 1'b1 : 1'b0;
always @(negedge adc_clk) begin
if (adc_ready == 1'b0 || adc_cnt_enable_s ==1'b0 ) begin
adc_cnt_p <= 'h000;
end else if (adc_cnt_enable_s == 1'b1) begin
adc_cnt_p <= adc_cnt_p + 1'b1;
end
if (adc_cnt_p == adc_cnt_value) begin
adc_valid_p <= 1'b1;
end else begin
adc_valid_p <= 1'b0;
end
end
//delay data 1 clk for data, data_valid and crc mismatch for alignment
always @(posedge adc_clk) begin
if (adc_valid_s == 1'b1) begin
adc_data_s_d[0] <= adc_data_s[0];
adc_data_s_d[1] <= adc_data_s[1];
adc_data_s_d[2] <= adc_data_s[2];
adc_data_s_d[3] <= adc_data_s[3];
adc_data_s_d[4] <= adc_data_s[4];
adc_data_s_d[5] <= adc_data_s[5];
adc_data_s_d[6] <= adc_data_s[6];
adc_data_s_d[7] <= adc_data_s[7];
adc_valid_s_d <= adc_valid_s;
end else begin
adc_data_s_d[0] <= 32'b0;
adc_data_s_d[1] <= 32'b0;
adc_data_s_d[2] <= 32'b0;
adc_data_s_d[3] <= 32'b0;
adc_data_s_d[4] <= 32'b0;
adc_data_s_d[5] <= 32'b0;
adc_data_s_d[6] <= 32'b0;
adc_data_s_d[7] <= 32'b0;
adc_valid_s_d <= 1'b0;
end
end
always @(posedge adc_clk) begin
if (adc_valid_p == 1'b1) begin
if( adc_format == 'h0 && NUM_CHANNELS == 8 ) begin // 1 active line
adc_data_s[0] <= adc_data_p[((32*7)+31):(32*7)];
adc_data_s[1] <= adc_data_p[((32*6)+31):(32*6)];
adc_data_s[2] <= adc_data_p[((32*5)+31):(32*5)];
adc_data_s[3] <= adc_data_p[((32*4)+31):(32*4)];
adc_data_s[4] <= adc_data_p[((32*3)+31):(32*3)];
adc_data_s[5] <= adc_data_p[((32*2)+31):(32*2)];
adc_data_s[6] <= adc_data_p[((32*1)+31):(32*1)];
adc_data_s[7] <= adc_data_p[((32*0)+31):(32*0)];
end else if( adc_format == 'h1 || (adc_format == 'h0 && NUM_CHANNELS == 4 )) begin // 2 active lines or 1 for ad7768-4
adc_data_s[0] <= adc_data_p[((32*3)+31):(32*3)];
adc_data_s[1] <= adc_data_p[((32*2)+31):(32*2)];
adc_data_s[2] <= adc_data_p[((32*1)+31):(32*1)];
adc_data_s[3] <= adc_data_p[((32*0)+31):(32*0)];
adc_data_s[4] <= adc_data_p[((32*7)+31):(32*7)];
adc_data_s[5] <= adc_data_p[((32*6)+31):(32*6)];
adc_data_s[6] <= adc_data_p[((32*5)+31):(32*5)];
adc_data_s[7] <= adc_data_p[((32*4)+31):(32*4)];
end else begin // 8 active lines
adc_data_s[0] <= adc_data_p[((32*0)+31):(32*0)];
adc_data_s[1] <= adc_data_p[((32*1)+31):(32*1)];
adc_data_s[2] <= adc_data_p[((32*2)+31):(32*2)];
adc_data_s[3] <= adc_data_p[((32*3)+31):(32*3)];
adc_data_s[4] <= adc_data_p[((32*4)+31):(32*4)];
adc_data_s[5] <= adc_data_p[((32*5)+31):(32*5)];
adc_data_s[6] <= adc_data_p[((32*6)+31):(32*6)];
adc_data_s[7] <= adc_data_p[((32*7)+31):(32*7)];
end
adc_valid_s <= adc_valid_p;
end else begin
adc_data_s[0] <= 32'b0;
adc_data_s[1] <= 32'b0;
adc_data_s[2] <= 32'b0;
adc_data_s[3] <= 32'b0;
adc_data_s[4] <= 32'b0;
adc_data_s[5] <= 32'b0;
adc_data_s[6] <= 32'b0;
adc_data_s[7] <= 32'b0;
adc_valid_s <= 1'b0;
end
end
// data (individual lanes)
always @(negedge adc_clk) begin
if( adc_format == 'h0 && NUM_CHANNELS == 8 ) begin // 1 active line for ad7768
if (adc_cnt_p == 'h0 ) begin
adc_data_p[((256*0)+255):(256*0)] <= {255'd0, data_in[0]};
end else begin
adc_data_p[((256*0)+255):(255*0)] <= {adc_data_p[((256*0)+254):(256*0)], data_in[0]};
end
end else if( adc_format == 'h1 || (adc_format == 'h0 && NUM_CHANNELS == 4 )) begin // 2 active lines or 1 active lane for ad7768-4
if (adc_cnt_p == 'h0 ) begin
adc_data_p[((128*0)+127):(128*0)] <= {127'd0, data_in[0]};
adc_data_p[((128*1)+127):(128*1)] <= {127'd0, data_in[1]};
end else begin
adc_data_p[((128*0)+127):(128*0)] <= {adc_data_p[((128*0)+126):(128*0)], data_in[0]};
adc_data_p[((128*1)+127):(128*1)] <= {adc_data_p[((128*1)+126):(128*1)], data_in[1]};
end
end else if( adc_format == 'h2 ) begin // 8 active lines or 4 active lane for ad7768-4
if (adc_cnt_p == 'h0 ) begin
adc_data_p[((32*0)+31):(32*0)] <= {31'd0, data_in[0]};
adc_data_p[((32*1)+31):(32*1)] <= {31'd0, data_in[1]};
adc_data_p[((32*2)+31):(32*2)] <= {31'd0, data_in[2]};
adc_data_p[((32*3)+31):(32*3)] <= {31'd0, data_in[3]};
adc_data_p[((32*4)+31):(32*4)] <= {31'd0, data_in[4]};
adc_data_p[((32*5)+31):(32*5)] <= {31'd0, data_in[5]};
adc_data_p[((32*6)+31):(32*6)] <= {31'd0, data_in[6]};
adc_data_p[((32*7)+31):(32*7)] <= {31'd0, data_in[7]};
end else begin
adc_data_p[((32*0)+31):(32*0)] <= {adc_data_p[((32*0)+30):(32*0)], data_in[0]};
adc_data_p[((32*1)+31):(32*1)] <= {adc_data_p[((32*1)+30):(32*1)], data_in[1]};
adc_data_p[((32*2)+31):(32*2)] <= {adc_data_p[((32*2)+30):(32*2)], data_in[2]};
adc_data_p[((32*3)+31):(32*3)] <= {adc_data_p[((32*3)+30):(32*3)], data_in[3]};
adc_data_p[((32*4)+31):(32*4)] <= {adc_data_p[((32*4)+30):(32*4)], data_in[4]};
adc_data_p[((32*5)+31):(32*5)] <= {adc_data_p[((32*5)+30):(32*5)], data_in[5]};
adc_data_p[((32*6)+31):(32*6)] <= {adc_data_p[((32*6)+30):(32*6)], data_in[6]};
adc_data_p[((32*7)+31):(32*7)] <= {adc_data_p[((32*7)+30):(32*7)], data_in[7]};
end
end
end
// ready (single shot or continous)
always @(posedge adc_clk) begin
adc_ready <= adc_sshot ~^ adc_ready_in_s;
end
endmodule

62
library/axi_ad7768/axi_ad7768_ip.tcl Normal file
View File

@ -0,0 +1,62 @@
# ip
source ../../scripts/adi_env.tcl
source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl
adi_ip_create axi_ad7768
adi_ip_files axi_ad7768 [list \
"$ad_hdl_dir/library/common/ad_rst.v" \
"$ad_hdl_dir/library/xilinx/common/ad_data_clk.v" \
"$ad_hdl_dir/library/xilinx/common/ad_data_in.v" \
"$ad_hdl_dir/library/xilinx/common/ad_dcfilter.v" \
"$ad_hdl_dir/library/common/ad_datafmt.v" \
"$ad_hdl_dir/library/common/up_xfer_status.v" \
"$ad_hdl_dir/library/common/up_xfer_cntrl.v" \
"$ad_hdl_dir/library/common/up_clock_mon.v" \
"$ad_hdl_dir/library/common/up_delay_cntrl.v" \
"$ad_hdl_dir/library/common/up_adc_common.v" \
"$ad_hdl_dir/library/common/up_adc_channel.v" \
"$ad_hdl_dir/library/common/up_axi.v" \
"$ad_hdl_dir/library/xilinx/common/up_xfer_cntrl_constr.xdc" \
"$ad_hdl_dir/library/xilinx/common/ad_rst_constr.xdc" \
"$ad_hdl_dir/library/xilinx/common/up_xfer_status_constr.xdc" \
"$ad_hdl_dir/library/xilinx/common/up_clock_mon_constr.xdc" \
"axi_ad7768_if.v" \
"axi_ad7768.v" ]
adi_ip_properties axi_ad7768
adi_init_bd_tcl
adi_ip_bd axi_ad7768 "bd/bd.tcl"
set cc [ipx::current_core]
set_property company_url {https://wiki.analog.com/resources/fpga/docs/ad7768} $cc
set_property driver_value 0 [ipx::get_ports *dovf* -of_objects $cc]
set_property driver_value 0 [ipx::get_ports *adc* -of_objects $cc]
set_property -dict [list \
value_validation_type list \
value_validation_list {4 8} \
] [ipx::get_user_parameters NUM_CHANNELS -of_objects $cc]
set_property enablement_dependency { $NUM_CHANNELS == 8 } \
[ipx::get_ports *_4 -of_objects $cc] \
[ipx::get_ports *_5 -of_objects $cc] \
[ipx::get_ports *_6 -of_objects $cc] \
[ipx::get_ports *_7 -of_objects $cc]
ipx::infer_bus_interface adc_clk xilinx.com:signal:clock_rtl:1.0 $cc
ipx::infer_bus_interface clk_in xilinx.com:signal:clock_rtl:1.0 $cc
set reset_intf [ipx::infer_bus_interface adc_reset xilinx.com:signal:reset_rtl:1.0 $cc ]
set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_intf]
set_property value "ACTIVE_HIGH" $reset_polarity
adi_add_auto_fpga_spec_params
ipx::create_xgui_files $cc
ipx::save_core $cc

571
projects/ad7768evb/common/ad7768_if.v
View File

@ -1,571 +0,0 @@
// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module ad7768_if (
// device-interface
input clk_in,
input ready_in,
input [ 7:0] data_in,
// data path interface
output adc_clk,
output reg adc_valid,
output reg adc_valid_0,
output reg adc_valid_1,
output reg adc_valid_2,
output reg adc_valid_3,
output reg adc_valid_4,
output reg adc_valid_5,
output reg adc_valid_6,
output reg adc_valid_7,
output reg adc_valid_pp,
output reg [ 31:0] adc_data,
output reg [ 31:0] adc_data_0,
output reg [ 31:0] adc_data_1,
output reg [ 31:0] adc_data_2,
output reg [ 31:0] adc_data_3,
output reg [ 31:0] adc_data_4,
output reg [ 31:0] adc_data_5,
output reg [ 31:0] adc_data_6,
output reg [ 31:0] adc_data_7,
output adc_sync,
// control interface
input up_sshot,
input [ 1:0] up_format,
input up_crc_enable,
input up_crc_4_or_16_n,
input [ 35:0] up_status_clr,
output [ 35:0] up_status
);
// internal registers
reg [ 1:0] adc_status_8 = 'd0;
reg [ 2:0] adc_status_7 = 'd0;
reg [ 2:0] adc_status_6 = 'd0;
reg [ 2:0] adc_status_5 = 'd0;
reg [ 2:0] adc_status_4 = 'd0;
reg [ 2:0] adc_status_3 = 'd0;
reg [ 2:0] adc_status_2 = 'd0;
reg [ 2:0] adc_status_1 = 'd0;
reg [ 2:0] adc_status_0 = 'd0;
reg [ 2:0] adc_seq = 'd0;
reg [ 4:0] adc_status = 'd0;
reg [ 63:0] adc_crc_8 = 'd0;
reg [ 7:0] adc_crc_mismatch_int = 'd0;
reg adc_crc_valid = 'd0;
reg [ 7:0] adc_crc_data = 'd0;
reg [ 7:0] adc_crc_mismatch_8 = 'd0;
reg adc_valid_int = 'd0;
reg [ 31:0] adc_data_int = 'd0;
reg [ 2:0] adc_seq_int = 'd0;
reg adc_enable_int = 'd0;
reg [ 3:0] adc_crc_scnt_int = 'd0;
reg [ 3:0] adc_crc_scnt_8 = 'd0;
reg [ 23:0] adc_seq_data = 'd0;
reg adc_seq_fmatch = 'd0;
reg [ 23:0] adc_seq_fdata = 'd0;
reg adc_seq_foos = 'd0;
reg [ 7:0] adc_enable_8 = 'd0;
reg [ 23:0] adc_seq_8 = 'd0;
reg adc_valid_8 = 'd0;
reg [ 31:0] adc_data_8 = 'd0;
reg [ 7:0] adc_ch_valid_d = 'd0;
reg [255:0] adc_ch_data_d0 = 'd0;
reg [255:0] adc_ch_data_d1 = 'd0;
reg [255:0] adc_ch_data_d2 = 'd0;
reg [255:0] adc_ch_data_d3 = 'd0;
reg [255:0] adc_ch_data_d4 = 'd0;
reg [255:0] adc_ch_data_d5 = 'd0;
reg [255:0] adc_ch_data_d6 = 'd0;
reg [255:0] adc_ch_data_d7 = 'd0;
reg adc_ch_valid_0 = 'd0;
reg adc_ch_valid_1 = 'd0;
reg adc_ch_valid_2 = 'd0;
reg adc_ch_valid_3 = 'd0;
reg adc_ch_valid_4 = 'd0;
reg adc_ch_valid_5 = 'd0;
reg adc_ch_valid_6 = 'd0;
reg adc_ch_valid_7 = 'd0;
reg [ 31:0] adc_ch_data_0 = 'd0;
reg [ 31:0] adc_ch_data_1 = 'd0;
reg [ 31:0] adc_ch_data_2 = 'd0;
reg [ 31:0] adc_ch_data_3 = 'd0;
reg [ 31:0] adc_ch_data_4 = 'd0;
reg [ 31:0] adc_ch_data_5 = 'd0;
reg [ 31:0] adc_ch_data_6 = 'd0;
reg [ 31:0] adc_ch_data_7 = 'd0;
reg adc_ch_valid = 'd0;
reg [255:0] adc_ch_data = 'd0;
reg [ 8:0] adc_cnt_p = 'd0;
reg adc_valid_p = 'd0;
reg [255:0] adc_data_p = 'd0;
reg [ 7:0] adc_data_d1 = 'd0;
reg [ 7:0] adc_data_d2 = 'd0;
reg adc_ready_d1 = 'd0;
reg adc_ready = 'd0;
reg adc_ready_d = 'd0;
reg adc_sshot_m1 = 'd0;
reg adc_sshot = 'd0;
reg [ 1:0] adc_format_m1 = 'd0;
reg [ 1:0] adc_format = 'd0;
reg adc_crc_enable_m1 = 'd0;
reg adc_crc_enable = 'd0;
reg adc_crc_4_or_16_n_m1 = 'd0;
reg adc_crc_4_or_16_n = 'd0;
reg [ 35:0] adc_status_clr_m1 = 'd0;
reg [ 35:0] adc_status_clr = 'd0;
reg [ 35:0] adc_status_clr_d = 'd0;
reg adc_valid_d = 'd0;
// internal signals
wire [ 7:0] adc_crc_in_s;
wire [ 7:0] adc_crc_s;
wire adc_crc_mismatch_s;
wire adc_seq_fmatch_s;
wire adc_seq_fupdate_s;
wire [ 7:0] adc_enable_8_s;
wire [ 23:0] adc_seq_8_s;
wire adc_cnt_enable_1_s;
wire adc_cnt_enable_4_s;
wire adc_cnt_enable_8_s;
wire adc_cnt_enable_s;
wire [ 7:0] adc_data_in_s;
wire adc_ready_in_s;
wire adc_clk_in_s;
wire [ 35:0] adc_status_clr_s;
// function (crc)
function [ 7:0] crc8;
input [23:0] din;
input [ 7:0] cin;
reg [ 7:0] cout;
begin
cout[ 7] = cin[ 1] ^ cin[ 2] ^ cin[ 4] ^ cin[ 6] ^ din[ 5] ^ din[ 6] ^ din[ 7] ^ din[11] ^
din[13] ^ din[15] ^ din[17] ^ din[18] ^ din[20] ^ din[22];
cout[ 6] = cin[ 0] ^ cin[ 1] ^ cin[ 3] ^ cin[ 5] ^ din[ 4] ^ din[ 5] ^ din[ 6] ^ din[10] ^
din[12] ^ din[14] ^ din[16] ^ din[17] ^ din[19] ^ din[21];
cout[ 5] = cin[ 0] ^ cin[ 2] ^ cin[ 4] ^ din[ 3] ^ din[ 4] ^ din[ 5] ^ din[ 9] ^ din[11] ^
din[13] ^ din[15] ^ din[16] ^ din[18] ^ din[20];
cout[ 4] = cin[ 1] ^ cin[ 3] ^ din[ 2] ^ din[ 3] ^ din[ 4] ^ din[ 8] ^ din[10] ^ din[12] ^
din[14] ^ din[15] ^ din[17] ^ din[19];
cout[ 3] = cin[ 0] ^ cin[ 2] ^ cin[ 7] ^ din[ 1] ^ din[ 2] ^ din[ 3] ^ din[ 7] ^ din[ 9] ^
din[11] ^ din[13] ^ din[14] ^ din[16] ^ din[18] ^ din[23];
cout[ 2] = cin[ 1] ^ cin[ 6] ^ din[ 0] ^ din[ 1] ^ din[ 2] ^ din[ 6] ^ din[ 8] ^ din[10] ^
din[12] ^ din[13] ^ din[15] ^ din[17] ^ din[22];
cout[ 1] = cin[ 0] ^ cin[ 1] ^ cin[ 2] ^ cin[ 4] ^ cin[ 5] ^ cin[ 6] ^ cin[ 7] ^ din[ 0] ^
din[ 1] ^ din[ 6] ^ din[ 9] ^ din[12] ^ din[13] ^ din[14] ^ din[15] ^ din[16] ^
din[17] ^ din[18] ^ din[20] ^ din[21] ^ din[22] ^ din[23];
cout[ 0] = cin[ 0] ^ cin[ 2] ^ cin[ 3] ^ cin[ 5] ^ cin[ 7] ^ din[ 0] ^ din[ 6] ^ din[ 7] ^
din[ 8] ^ din[12] ^ din[14] ^ din[16] ^ din[18] ^ din[19] ^ din[21] ^ din[23];
crc8 = cout;
end
endfunction
// status
assign up_status[35:32] = {2'd0, adc_status_8};
assign up_status[31:28] = {1'd0, adc_status_7};
assign up_status[27:24] = {1'd0, adc_status_6};
assign up_status[23:20] = {1'd0, adc_status_5};
assign up_status[19:16] = {1'd0, adc_status_4};
assign up_status[15:12] = {1'd0, adc_status_3};
assign up_status[11: 8] = {1'd0, adc_status_2};
assign up_status[ 7: 4] = {1'd0, adc_status_1};
assign up_status[ 3: 0] = {1'd0, adc_status_0};
assign adc_ready_in_s = ready_in;
assign adc_clk = clk_in;
always @(posedge adc_clk) begin
if (adc_valid == 1'b1) begin
adc_status_8 <= adc_status_8 | adc_status[1:0];
end else begin
adc_status_8 <= adc_status_8 & ~adc_status_clr_s[33:32];
end
if ((adc_valid == 1'b1) && (adc_seq[2:0] == 3'd7)) begin
adc_status_7 <= adc_status_7 | adc_status[4:2];
end else begin
adc_status_7 <= adc_status_7 & ~adc_status_clr_s[30:28];
end
if ((adc_valid == 1'b1) && (adc_seq[2:0] == 3'd6)) begin
adc_status_6 <= adc_status_6 | adc_status[4:2];
end else begin
adc_status_6 <= adc_status_6 & ~adc_status_clr_s[26:24];
end
if ((adc_valid == 1'b1) && (adc_seq[2:0] == 3'd5)) begin
adc_status_5 <= adc_status_5 | adc_status[4:2];
end else begin
adc_status_5 <= adc_status_5 & ~adc_status_clr_s[22:20];
end
if ((adc_valid == 1'b1) && (adc_seq[2:0] == 3'd4)) begin
adc_status_4 <= adc_status_4 | adc_status[4:2];
end else begin
adc_status_4 <= adc_status_4 & ~adc_status_clr_s[18:16];
end
if ((adc_valid == 1'b1) && (adc_seq[2:0] == 3'd3)) begin
adc_status_3 <= adc_status_3 | adc_status[4:2];
end else begin
adc_status_3 <= adc_status_3 & ~adc_status_clr_s[14:12];
end
if ((adc_valid == 1'b1) && (adc_seq[2:0] == 3'd2)) begin
adc_status_2 <= adc_status_2 | adc_status[4:2];
end else begin
adc_status_2 <= adc_status_2 & ~adc_status_clr_s[10: 8];
end
if ((adc_valid == 1'b1) && (adc_seq[2:0] == 3'd1)) begin
adc_status_1 <= adc_status_1 | adc_status[4:2];
end else begin
adc_status_1 <= adc_status_1 & ~adc_status_clr_s[ 6: 4];
end
if ((adc_valid == 1'b1) && (adc_seq[2:0] == 3'd0)) begin
adc_status_0 <= adc_status_0 | adc_status[4:2];
end else begin
adc_status_0 <= adc_status_0 & ~adc_status_clr_s[ 2: 0];
end
end
// data & status
always @(posedge adc_clk) begin
adc_valid_d <= adc_valid;
end
assign adc_sync = adc_valid & ~adc_valid_d;
always @(posedge adc_clk) begin
adc_valid <= adc_valid_int & adc_enable_int;
adc_data <= {{8{adc_data_int[23]}}, adc_data_int[23:0]};
if (adc_ch_valid_0 == 1'b1) begin
adc_data_0 <= adc_ch_data_0;
end
if (adc_ch_valid_1 == 1'b1) begin
adc_data_1 <= adc_ch_data_1;
end
if (adc_ch_valid_2 == 1'b1) begin
adc_data_2 <= adc_ch_data_2;
end
if (adc_ch_valid_3 == 1'b1) begin
adc_data_3 <= adc_ch_data_3;
end
if (adc_ch_valid_4 == 1'b1) begin
adc_data_4 <= adc_ch_data_4;
end
if (adc_ch_valid_5 == 1'b1) begin
adc_data_5 <= adc_ch_data_5;
end
if (adc_ch_valid_6 == 1'b1) begin
adc_data_6 <= adc_ch_data_6;
end
if (adc_ch_valid_7 == 1'b1) begin
adc_data_7 <= adc_ch_data_7;
end
adc_seq <= adc_seq_int;
adc_valid_0 <= adc_ch_valid_7;
adc_valid_1 <= adc_ch_valid_7;
adc_valid_2 <= adc_ch_valid_7;
adc_valid_3 <= adc_ch_valid_7;
adc_valid_4 <= adc_ch_valid_7;
adc_valid_5 <= adc_ch_valid_7;
adc_valid_6 <= adc_ch_valid_7;
adc_valid_7 <= adc_ch_valid_7;
adc_valid_pp <= adc_valid_0 | adc_valid_1 | adc_valid_2 | adc_valid_3 |
adc_valid_4 | adc_valid_5 | adc_valid_6 | adc_valid_7;
if ((adc_crc_enable == 1'b1) && (adc_crc_scnt_int == 4'd0)) begin
adc_status[4] <= adc_crc_mismatch_8[7] & adc_enable_int;
adc_status[3] <= 1'b0;
adc_status[2] <= 1'b0;
adc_status[1] <= 1'b0;
adc_status[0] <= adc_seq_foos;
end else begin
adc_status[4] <= adc_crc_mismatch_8[7] & adc_enable_int;
adc_status[3] <= adc_data_int[30] & adc_enable_int;
adc_status[2] <= adc_data_int[27] & adc_enable_int;
adc_status[1] <= adc_data_int[31] & adc_enable_int;
adc_status[0] <= adc_seq_foos;
end
end
// crc- not much useful at the interface, since it is post-framing
assign adc_crc_in_s = (adc_crc_scnt_int == 4'd1) ? 8'hff : adc_crc_8[63:56];
assign adc_crc_s = crc8(adc_data_int[23:0], adc_crc_in_s);
assign adc_crc_mismatch_s = (adc_crc_data == adc_crc_8[7:0]) ? 1'b0 : adc_crc_enable;
always @(posedge adc_clk) begin
if (adc_valid_int == 1'b1) begin
adc_crc_8 <= {adc_crc_8[55:0], adc_crc_s};
end
if (adc_valid_int == 1'b1) begin
adc_crc_mismatch_int <= {adc_crc_mismatch_int[6:0], 1'd0};
end else begin
adc_crc_mismatch_int <= adc_crc_mismatch_8;
end
if (adc_crc_scnt_int == 4'd0) begin
adc_crc_valid <= adc_valid_int;
end else begin
adc_crc_valid <= 1'd0;
end
adc_crc_data <= adc_data_int[31:24];
if (adc_crc_valid == 1'b1) begin
adc_crc_mismatch_8 <= {adc_crc_mismatch_8[6:0], adc_crc_mismatch_s};
end
end
// data interleaved & all-aligned
always @(posedge adc_clk) begin
adc_valid_int <= adc_valid_8;
adc_data_int <= adc_data_8;
adc_seq_int <= adc_seq_8[23:21];
adc_enable_int <= adc_enable_8[7] & adc_valid_8;
adc_crc_scnt_int <= adc_crc_scnt_8;
end
// crc- count
always @(posedge adc_clk) begin
if ((adc_ready == 1'b0) && (adc_ready_d == 1'b1)) begin
if (adc_seq_fmatch_s == 1'b0) begin
adc_crc_scnt_8 <= 4'd1;
end else if ((adc_crc_4_or_16_n == 1'b1) && (adc_crc_scnt_8 == 4'h3)) begin
adc_crc_scnt_8 <= 4'd0;
end else begin
adc_crc_scnt_8 <= adc_crc_scnt_8 + 1'b1;
end
end
end
// three sample framing logic
always @(posedge adc_clk) begin
if (adc_ready == 1'b0) begin
adc_seq_data <= 24'd0;
end else if (adc_valid_8 == 1'b1) begin
adc_seq_data <= {adc_seq_data[20:0], adc_data_8[26:24]};
end
end
assign adc_seq_fmatch_s = (adc_seq_data == adc_seq_fdata) ? 1'b1 : 1'b0;
assign adc_seq_fupdate_s = adc_seq_fmatch_s ^ adc_seq_fmatch;
always @(posedge adc_clk) begin
if ((adc_ready == 1'b0) && (adc_ready_d == 1'b1)) begin
adc_seq_fmatch <= adc_seq_fmatch_s;
if (adc_seq_foos == 1'b1) begin
adc_seq_fdata <= adc_seq_data;
end
if (adc_seq_fupdate_s == 1'b0) begin
adc_seq_foos <= ~adc_seq_fmatch_s;
end
end
end
// we are cluless on 0 -- safe to compare all 32bits against 0x0?
assign adc_enable_8_s[7] = (adc_seq_8[23:21] == adc_seq_fdata[23:21]) ? 1'b1 : 1'b0;
assign adc_enable_8_s[6] = (adc_seq_8[20:18] == adc_seq_fdata[20:18]) ? 1'b1 : 1'b0;
assign adc_enable_8_s[5] = (adc_seq_8[17:15] == adc_seq_fdata[17:15]) ? 1'b1 : 1'b0;
assign adc_enable_8_s[4] = (adc_seq_8[14:12] == adc_seq_fdata[14:12]) ? 1'b1 : 1'b0;
assign adc_enable_8_s[3] = (adc_seq_8[11: 9] == adc_seq_fdata[11: 9]) ? 1'b1 : 1'b0;
assign adc_enable_8_s[2] = (adc_seq_8[ 8: 6] == adc_seq_fdata[ 8: 6]) ? 1'b1 : 1'b0;
assign adc_enable_8_s[1] = (adc_seq_8[ 5: 3] == adc_seq_fdata[ 5: 3]) ? 1'b1 : 1'b0;
assign adc_enable_8_s[0] = (adc_seq_8[ 2: 0] == adc_seq_fdata[ 2: 0]) ? 1'b1 : 1'b0;
always @(posedge adc_clk) begin
if (adc_ready_d == 1'b0) begin
adc_enable_8 <= adc_enable_8_s;
end else if (adc_valid_8 == 1'b1) begin
adc_enable_8 <= {adc_enable_8[6:0], 1'd0};
end
end
// channel-sequence
assign adc_seq_8_s[23:21] = (adc_format == 2'b01) ? 3'd0 : 3'd0;
assign adc_seq_8_s[20:18] = (adc_format == 2'b01) ? 3'd4 : 3'd1;
assign adc_seq_8_s[17:15] = (adc_format == 2'b01) ? 3'd1 : 3'd2;
assign adc_seq_8_s[14:12] = (adc_format == 2'b01) ? 3'd5 : 3'd3;
assign adc_seq_8_s[11: 9] = (adc_format == 2'b01) ? 3'd2 : 3'd4;
assign adc_seq_8_s[ 8: 6] = (adc_format == 2'b01) ? 3'd6 : 3'd5;
assign adc_seq_8_s[ 5: 3] = (adc_format == 2'b01) ? 3'd3 : 3'd6;
assign adc_seq_8_s[ 2: 0] = (adc_format == 2'b01) ? 3'd7 : 3'd7;
always @(posedge adc_clk) begin
if ((adc_ready == 1'b0) && (adc_ready_d == 1'b1)) begin
adc_seq_8 <= adc_seq_8_s;
end else if (adc_valid_8 == 1'b1) begin
adc_seq_8 <= {adc_seq_8[20:0], 3'd0};
end
end
// data (interleaving)
always @(posedge adc_clk) begin
adc_valid_8 <= adc_ch_valid_0 | adc_ch_valid_1 | adc_ch_valid_2 | adc_ch_valid_3 |
adc_ch_valid_4 | adc_ch_valid_5 | adc_ch_valid_6 | adc_ch_valid_7;
adc_data_8 <= adc_ch_data_0 | adc_ch_data_1 | adc_ch_data_2 | adc_ch_data_3 |
adc_ch_data_4 | adc_ch_data_5 | adc_ch_data_6 | adc_ch_data_7;
end
always @(posedge adc_clk) begin
adc_ch_valid_d <= {adc_ch_valid_d[6:0], adc_ch_valid};
adc_ch_data_d0[((32*0)+31):(32*0)] <= adc_ch_data[((32*0)+31):(32*0)];
adc_ch_data_d0[((32*7)+31):(32*1)] <= adc_ch_data_d0[((32*6)+31):(32*0)];
adc_ch_data_d1[((32*0)+31):(32*0)] <= adc_ch_data[((32*1)+31):(32*1)];
adc_ch_data_d1[((32*7)+31):(32*1)] <= adc_ch_data_d1[((32*6)+31):(32*0)];
adc_ch_data_d2[((32*0)+31):(32*0)] <= adc_ch_data[((32*2)+31):(32*2)];
adc_ch_data_d2[((32*7)+31):(32*1)] <= adc_ch_data_d2[((32*6)+31):(32*0)];
adc_ch_data_d3[((32*0)+31):(32*0)] <= adc_ch_data[((32*3)+31):(32*3)];
adc_ch_data_d3[((32*7)+31):(32*1)] <= adc_ch_data_d3[((32*6)+31):(32*0)];
adc_ch_data_d4[((32*0)+31):(32*0)] <= adc_ch_data[((32*4)+31):(32*4)];
adc_ch_data_d4[((32*7)+31):(32*1)] <= adc_ch_data_d4[((32*6)+31):(32*0)];
adc_ch_data_d5[((32*0)+31):(32*0)] <= adc_ch_data[((32*5)+31):(32*5)];
adc_ch_data_d5[((32*7)+31):(32*1)] <= adc_ch_data_d5[((32*6)+31):(32*0)];
adc_ch_data_d6[((32*0)+31):(32*0)] <= adc_ch_data[((32*6)+31):(32*6)];
adc_ch_data_d6[((32*7)+31):(32*1)] <= adc_ch_data_d6[((32*6)+31):(32*0)];
adc_ch_data_d7[((32*0)+31):(32*0)] <= adc_ch_data[((32*7)+31):(32*7)];
adc_ch_data_d7[((32*7)+31):(32*1)] <= adc_ch_data_d7[((32*6)+31):(32*0)];
end
always @(posedge adc_clk) begin
adc_ch_valid_0 <= adc_ch_valid_d[0];
adc_ch_valid_1 <= adc_ch_valid_d[1] & ~adc_format[1];
adc_ch_valid_2 <= adc_ch_valid_d[2] & ~adc_format[1] & ~adc_format[0];
adc_ch_valid_3 <= adc_ch_valid_d[3] & ~adc_format[1] & ~adc_format[0];
adc_ch_valid_4 <= adc_ch_valid_d[4] & ~adc_format[1] & ~adc_format[0];
adc_ch_valid_5 <= adc_ch_valid_d[5] & ~adc_format[1] & ~adc_format[0];
adc_ch_valid_6 <= adc_ch_valid_d[6] & ~adc_format[1] & ~adc_format[0];
adc_ch_valid_7 <= adc_ch_valid_d[7] & ~adc_format[1] & ~adc_format[0];
adc_ch_data_0 <= adc_ch_data_d0[((32*0)+31):(32*0)];
adc_ch_data_1 <= adc_ch_data_d1[((32*1)+31):(32*1)];
adc_ch_data_2 <= adc_ch_data_d2[((32*2)+31):(32*2)];
adc_ch_data_3 <= adc_ch_data_d3[((32*3)+31):(32*3)];
adc_ch_data_4 <= adc_ch_data_d4[((32*4)+31):(32*4)];
adc_ch_data_5 <= adc_ch_data_d5[((32*5)+31):(32*5)];
adc_ch_data_6 <= adc_ch_data_d6[((32*6)+31):(32*6)];
adc_ch_data_7 <= adc_ch_data_d7[((32*7)+31):(32*7)];
end
always @(posedge adc_clk) begin
adc_ch_valid <= adc_valid_p;
if (adc_valid_p == 1'b1) begin
adc_ch_data <= adc_data_p;
end else begin
adc_ch_data <= 256'd0;
end
end
// data (common)
assign adc_cnt_enable_1_s = (adc_cnt_p <= 9'h01f) ? 1'b1 : 1'b0;
assign adc_cnt_enable_4_s = (adc_cnt_p <= 9'h07f) ? 1'b1 : 1'b0;
assign adc_cnt_enable_8_s = (adc_cnt_p <= 9'h0ff) ? 1'b1 : 1'b0;
assign adc_cnt_enable_s = (adc_format == 2'b00) ? adc_cnt_enable_1_s :
((adc_format == 2'b01) ? adc_cnt_enable_4_s : adc_cnt_enable_8_s);
always @(posedge adc_clk) begin
if (adc_ready == 1'b0) begin
adc_cnt_p <= 9'h000;
end else if (adc_cnt_enable_s == 1'b1) begin
adc_cnt_p <= adc_cnt_p + 1'b1;
end
if (adc_cnt_p[4:0] == 5'h1f) begin
adc_valid_p <= 1'b1;
end else begin
adc_valid_p <= 1'b0;
end
end
// data (individual lanes)
genvar n;
generate
for (n = 0; n < 8; n = n + 1) begin: g_data
always @(posedge adc_clk) begin
if (adc_cnt_p[4:0] == 5'h00) begin
adc_data_p[((32*n)+31):(32*n)] <= {31'd0, adc_data_d2[n]};
end else begin
adc_data_p[((32*n)+31):(32*n)] <= {adc_data_p[((32*n)+30):(32*n)], adc_data_d2[n]};
end
end
always @(posedge adc_clk) begin
adc_data_d1[n] <= adc_data_in_s[n];
adc_data_d2[n] <= adc_data_d1[n];
end
assign adc_data_in_s[n] = data_in[n];
end
endgenerate
// ready (single shot or continous)
always @(posedge adc_clk) begin
adc_ready_d1 <= adc_ready_in_s;
adc_ready <= adc_sshot ~^ adc_ready_d1;
adc_ready_d <= adc_ready;
end
// control signals
assign adc_status_clr_s = adc_status_clr & ~adc_status_clr_d;
always @(posedge adc_clk) begin
adc_sshot_m1 <= up_sshot;
adc_sshot <= adc_sshot_m1;
adc_format_m1 <= up_format;
adc_format <= adc_format_m1;
adc_crc_enable_m1 <= up_crc_enable;
adc_crc_enable <= adc_crc_enable_m1;
adc_crc_4_or_16_n_m1 <= up_crc_4_or_16_n;
adc_crc_4_or_16_n <= adc_crc_4_or_16_n_m1;
adc_status_clr_m1 <= up_status_clr;
adc_status_clr <= adc_status_clr_m1;
adc_status_clr_d <= adc_status_clr;
end
endmodule

90
projects/ad7768evb/common/ad7768evb_bd.tcl
View File

@ -1,25 +1,9 @@
# ad7768 interface
create_bd_port -dir I adc_clk
create_bd_port -dir I adc_valid
create_bd_port -dir I adc_valid_pp
create_bd_port -dir I adc_sync
create_bd_port -dir I -from 31 -to 0 adc_data
create_bd_port -dir I -from 31 -to 0 adc_data_0
create_bd_port -dir I -from 31 -to 0 adc_data_1
create_bd_port -dir I -from 31 -to 0 adc_data_2
create_bd_port -dir I -from 31 -to 0 adc_data_3
create_bd_port -dir I -from 31 -to 0 adc_data_4
create_bd_port -dir I -from 31 -to 0 adc_data_5
create_bd_port -dir I -from 31 -to 0 adc_data_6
create_bd_port -dir I -from 31 -to 0 adc_data_7
create_bd_port -dir I -from 31 -to 0 adc_gpio_0_i
create_bd_port -dir O -from 31 -to 0 adc_gpio_0_o
create_bd_port -dir O -from 31 -to 0 adc_gpio_0_t
create_bd_port -dir I -from 31 -to 0 adc_gpio_1_i
create_bd_port -dir O -from 31 -to 0 adc_gpio_1_o
create_bd_port -dir O -from 31 -to 0 adc_gpio_1_t
create_bd_port -dir I clk_in
create_bd_port -dir I ready_in
create_bd_port -dir I -from 7 -to 0 data_in
# instances
@ -47,74 +31,56 @@ ad_ip_parameter ad7768_dma_2 CONFIG.DMA_DATA_WIDTH_SRC 256
ad_ip_parameter sys_ps7 CONFIG.PCW_USE_S_AXI_HP1 1
# gpio
ad_ip_instance axi_gpio ad7768_gpio
ad_ip_parameter ad7768_gpio CONFIG.C_IS_DUAL 1
ad_ip_parameter ad7768_gpio CONFIG.C_GPIO_WIDTH 32
ad_ip_parameter ad7768_gpio CONFIG.C_GPIO2_WIDTH 32
ad_ip_parameter ad7768_gpio CONFIG.C_INTERRUPT_PRESENT 1
# adc-path channel pack
# parallel path channel pack
ad_ip_instance util_cpack2 util_ad7768_adc_pack
ad_ip_parameter util_ad7768_adc_pack CONFIG.NUM_OF_CHANNELS 8
ad_ip_parameter util_ad7768_adc_pack CONFIG.SAMPLE_DATA_WIDTH 32
ad_connect adc_clk util_ad7768_adc_pack/clk
ad_connect sys_rstgen/peripheral_reset util_ad7768_adc_pack/reset
ad_connect adc_valid_pp util_ad7768_adc_pack/fifo_wr_en
# axi_ad7768
ad_ip_instance axi_ad7768 axi_ad7768_adc
ad_ip_parameter axi_ad7768_adc CONFIG.NUM_CHANNELS 8
for {set i 0} {$i < 8} {incr i} {
ad_connect adc_data_$i util_ad7768_adc_pack/fifo_wr_data_$i
ad_connect axi_ad7768_adc/adc_enable_$i util_ad7768_adc_pack/enable_$i
ad_connect axi_ad7768_adc/adc_data_$i util_ad7768_adc_pack/fifo_wr_data_$i
}
# axi_generic_adc
ad_connect axi_ad7768_adc/s_axi_aclk sys_ps7/FCLK_CLK0
ad_connect axi_ad7768_adc/clk_in clk_in
ad_connect axi_ad7768_adc/ready_in ready_in
ad_connect axi_ad7768_adc/data_in data_in
ad_connect axi_ad7768_adc/adc_valid util_ad7768_adc_pack/fifo_wr_en
ad_connect axi_ad7768_adc/adc_clk util_ad7768_adc_pack/clk
ad_connect axi_ad7768_adc/adc_reset util_ad7768_adc_pack/reset
ad_connect axi_ad7768_adc/adc_dovf util_ad7768_adc_pack/fifo_wr_overflow
ad_ip_instance axi_generic_adc axi_ad7768_adc
ad_ip_parameter axi_ad7768_adc CONFIG.NUM_OF_CHANNELS 8
#serial DMA
for {set i 0} {$i < 8} {incr i} {
ad_ip_instance xlslice xlslice_$i
set_property -dict [list CONFIG.DIN_FROM $i CONFIG.DIN_WIDTH {8} CONFIG.DOUT_WIDTH {1} CONFIG.DIN_TO $i] [get_bd_cells xlslice_$i]
ad_connect axi_ad7768_adc/adc_enable xlslice_$i/Din
ad_connect xlslice_$i/Dout util_ad7768_adc_pack/enable_$i
}
ad_connect ad7768_dma/m_dest_axi_aresetn sys_cpu_resetn
ad_connect ad7768_dma/fifo_wr_clk axi_ad7768_adc/adc_clk
ad_connect ad7768_dma/fifo_wr_en axi_ad7768_adc/adc_valid
ad_connect ad7768_dma/fifo_wr_din axi_ad7768_adc/adc_data
ad_connect ad7768_dma/fifo_wr_sync axi_ad7768_adc/adc_sync
# interconnects
#parallel DMA
ad_connect sys_cpu_resetn ad7768_dma/m_dest_axi_aresetn
ad_connect sys_cpu_resetn ad7768_dma_2/m_dest_axi_aresetn
ad_connect adc_clk ad7768_dma/fifo_wr_clk
ad_connect adc_valid ad7768_dma/fifo_wr_en
ad_connect adc_sync ad7768_dma/fifo_wr_sync
ad_connect adc_data ad7768_dma/fifo_wr_din
ad_connect adc_clk ad7768_dma_2/fifo_wr_clk
ad_connect util_ad7768_adc_pack/packed_fifo_wr ad7768_dma_2/fifo_wr
ad_connect util_ad7768_adc_pack/fifo_wr_overflow axi_ad7768_adc/adc_dovf
ad_connect adc_clk axi_ad7768_adc/adc_clk
ad_connect sys_ps7/FCLK_CLK0 axi_ad7768_adc/s_axi_aclk
ad_connect adc_gpio_0_i ad7768_gpio/gpio_io_i
ad_connect adc_gpio_0_o ad7768_gpio/gpio_io_o
ad_connect adc_gpio_0_t ad7768_gpio/gpio_io_t
ad_connect adc_gpio_1_i ad7768_gpio/gpio2_io_i
ad_connect adc_gpio_1_o ad7768_gpio/gpio2_io_o
ad_connect adc_gpio_1_t ad7768_gpio/gpio2_io_t
ad_connect ad7768_dma_2/m_dest_axi_aresetn sys_cpu_resetn
ad_connect ad7768_dma_2/fifo_wr_clk axi_ad7768_adc/adc_clk
ad_connect ad7768_dma_2/fifo_wr util_ad7768_adc_pack/packed_fifo_wr
# interrupts
ad_cpu_interrupt ps-13 mb-13 ad7768_dma/irq
ad_cpu_interrupt ps-12 mb-12 ad7768_gpio/ip2intc_irpt
ad_cpu_interrupt ps-10 mb-10 ad7768_dma_2/irq
# cpu / memory interconnects
ad_cpu_interconnect 0x7C400000 ad7768_dma
ad_cpu_interconnect 0x7C420000 ad7768_gpio
ad_cpu_interconnect 0x7C480000 ad7768_dma_2
ad_cpu_interconnect 0x43c00000 axi_ad7768_adc
ad_mem_hp1_interconnect sys_cpu_clk sys_ps7/S_AXI_HP1
ad_mem_hp1_interconnect sys_cpu_clk ad7768_dma/m_dest_axi
ad_mem_hp1_interconnect sys_cpu_clk ad7768_dma_2/m_dest_axi

3
projects/ad7768evb/zed/Makefile
View File

@ -7,15 +7,14 @@
PROJECT_NAME := ad7768evb_zed
M_DEPS += ../common/ad7768evb_bd.tcl
M_DEPS += ../common/ad7768_if.v
M_DEPS += ../../scripts/adi_pd.tcl
M_DEPS += ../../common/zed/zed_system_constr.xdc
M_DEPS += ../../common/zed/zed_system_bd.tcl
M_DEPS += ../../../library/common/ad_iobuf.v
LIB_DEPS += axi_ad7768
LIB_DEPS += axi_clkgen
LIB_DEPS += axi_dmac
LIB_DEPS += axi_generic_adc
LIB_DEPS += axi_hdmi_tx
LIB_DEPS += axi_i2s_adi
LIB_DEPS += axi_spdif_tx

2
projects/ad7768evb/zed/system_constr.xdc
View File

@ -21,8 +21,6 @@ set_property -dict {PACKAGE_PIN N17 IOSTANDARD LVCMOS25} [get_ports gpio_3_mo
set_property -dict {PACKAGE_PIN R19 IOSTANDARD LVCMOS25} [get_ports gpio_4_filter] ; ## C14 FMC_LPC_LA10_P IO_L22P_T3_34
set_property -dict {PACKAGE_PIN L21 IOSTANDARD LVCMOS25} [get_ports reset_n] ; ## C10 FMC_LPC_LA06_P IO_L10P_T1_34
set_property -dict {PACKAGE_PIN P22 IOSTANDARD LVCMOS25} [get_ports start_n] ; ## G10 FMC_LPC_LA03_N IO_L16N_T2_34
set_property -dict {PACKAGE_PIN M21 IOSTANDARD LVCMOS25} [get_ports sync_n] ; ## H10 FMC_LPC_LA04_P IO_L15P_T2_DQS_34
set_property -dict {PACKAGE_PIN K18 IOSTANDARD LVCMOS25} [get_ports sync_in_n] ; ## D12 FMC_LPC_LA05_N IO_L7N_T1_34
set_property -dict {PACKAGE_PIN N20 IOSTANDARD LVCMOS25} [get_ports mclk] ; ## D09 FMC_LPC_LA01_CC_N IO_L14N_T2_SRCC_34
create_clock -name adc_clk -period 20 [get_ports clk_in]

1
projects/ad7768evb/zed/system_project.tcl
View File

@ -5,7 +5,6 @@ source $ad_hdl_dir/projects/scripts/adi_board.tcl
adi_project ad7768evb_zed
adi_project_files ad7768evb_zed [list \
"../common/ad7768_if.v" \
"system_top.v" \
"system_constr.xdc" \
"$ad_hdl_dir/projects/common/zed/zed_system_constr.xdc" \

80
projects/ad7768evb/zed/system_top.v
View File

@ -1,6 +1,6 @@
// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
// Copyright 2014 - 2022 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
@ -97,10 +97,8 @@ module system_top (
inout gpio_2_mode_2,
inout gpio_3_mode_3,
inout gpio_4_filter,
inout reset_n,
inout start_n,
inout sync_n,
inout sync_in_n,
output reset_n,
output start_n,
output mclk
);
@ -119,10 +117,6 @@ module system_top (
wire [31:0] adc_data_5;
wire [31:0] adc_data_6;
wire [31:0] adc_data_7;
wire up_sshot;
wire [ 1:0] up_format;
wire up_crc_enable;
wire up_crc_4_or_16_n;
wire [63:0] adc_gpio_i;
wire [63:0] adc_gpio_o;
wire [63:0] adc_gpio_t;
@ -139,28 +133,23 @@ module system_top (
// use crystal
assign mclk = 1'b0;
assign up_sshot = gpio_o[36];
assign up_format = gpio_o[35:34];
assign up_crc_enable = gpio_o[33];
assign up_crc_4_or_16_n = gpio_o[32];
assign start_n = gpio_o[33];
assign reset_n = gpio_o[32];
// instantiations
ad_iobuf #(
.DATA_WIDTH(9)
.DATA_WIDTH(5)
) i_iobuf (
.dio_t ({gpio_t[52:48], gpio_t[43:40]}),
.dio_i ({gpio_o[52:48], gpio_o[43:40]}),
.dio_o ({gpio_i[52:48], gpio_i[43:40]}),
.dio_t (gpio_t[52:48]),
.dio_i (gpio_o[52:48]),
.dio_o (gpio_i[52:48]),
.dio_p ({ gpio_4_filter, // 52
gpio_3_mode_3, // 51
gpio_2_mode_2, // 50
gpio_1_mode_1, // 49
gpio_0_mode_0, // 48
sync_in_n, // 43
sync_n, // 42
start_n, // 41
reset_n})); // 40
gpio_0_mode_0 // 48
}));
ad_iobuf #(
.DATA_WIDTH(32)
@ -170,9 +159,8 @@ module system_top (
.dio_o (gpio_i[31:0]),
.dio_p (gpio_bd));
assign gpio_i[36:32] = 5'b0;
assign gpio_i[39:37] = gpio_o[39:37];
assign gpio_i[47:44] = gpio_o[47:44];
assign gpio_i[33:32] = 2'b0;
assign gpio_i[47:34] = gpio_o[47:34];
assign gpio_i[63:53] = gpio_o[63:53];
ad_iobuf #(
@ -191,50 +179,10 @@ module system_top (
.dio_o (iic_mux_sda_i_s),
.dio_p (iic_mux_sda));
ad7768_if i_ad7768_if (
system_wrapper i_system_wrapper (
.clk_in (clk_in),
.ready_in (ready_in),
.data_in (data_in),
.adc_clk (adc_clk),
.adc_valid (adc_valid),
.adc_valid_pp (adc_valid_pp),
.adc_sync (adc_sync),
.adc_data (adc_data),
.adc_data_0 (adc_data_0),
.adc_data_1 (adc_data_1),
.adc_data_2 (adc_data_2),
.adc_data_3 (adc_data_3),
.adc_data_4 (adc_data_4),
.adc_data_5 (adc_data_5),
.adc_data_6 (adc_data_6),
.adc_data_7 (adc_data_7),
.up_sshot (up_sshot),
.up_format (up_format),
.up_crc_enable (up_crc_enable),
.up_crc_4_or_16_n (up_crc_4_or_16_n),
.up_status_clr (adc_gpio_o[32:0]),
.up_status (adc_gpio_i[32:0]));
system_wrapper i_system_wrapper (
.adc_clk (adc_clk),
.adc_data (adc_data),
.adc_data_0 (adc_data_0),
.adc_data_1 (adc_data_1),
.adc_data_2 (adc_data_2),
.adc_data_3 (adc_data_3),
.adc_data_4 (adc_data_4),
.adc_data_5 (adc_data_5),
.adc_data_6 (adc_data_6),
.adc_data_7 (adc_data_7),
.adc_gpio_0_i (adc_gpio_i[31:0]),
.adc_gpio_0_o (adc_gpio_o[31:0]),
.adc_gpio_0_t (adc_gpio_t[31:0]),
.adc_gpio_1_i (adc_gpio_i[63:32]),
.adc_gpio_1_o (adc_gpio_o[63:32]),
.adc_gpio_1_t (adc_gpio_t[63:32]),
.adc_valid (adc_valid),
.adc_valid_pp (adc_valid_pp),
.adc_sync (adc_sync),
.ddr_addr (ddr_addr),
.ddr_ba (ddr_ba),
.ddr_cas_n (ddr_cas_n),