From cc6ca4f0f200e5fc7a7ac27fd5be48c4b26e6eda Mon Sep 17 00:00:00 2001 From: Rejeesh Kutty Date: Mon, 10 Oct 2016 10:39:35 -0400 Subject: [PATCH] ad_lvds_in- ultrascale sim device --- library/xilinx/common/ad_lvds_in.v | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/library/xilinx/common/ad_lvds_in.v b/library/xilinx/common/ad_lvds_in.v index 38d804ca2..b6f6ef257 100644 --- a/library/xilinx/common/ad_lvds_in.v +++ b/library/xilinx/common/ad_lvds_in.v @@ -108,11 +108,19 @@ module ad_lvds_in ( generate if (IODELAY_CTRL == 1) begin + if (DEVICE_TYPE == ULTRASCALE) begin + (* IODELAY_GROUP = IODELAY_GROUP *) + IDELAYCTRL #(.SIM_DEVICE ("ULTRASCALE")) i_delay_ctrl ( + .RST (delay_rst), + .REFCLK (delay_clk), + .RDY (delay_locked)); + end else begin (* IODELAY_GROUP = IODELAY_GROUP *) IDELAYCTRL i_delay_ctrl ( .RST (delay_rst), .REFCLK (delay_clk), .RDY (delay_locked)); + end end else begin assign delay_locked = 1'b1; end @@ -196,6 +204,7 @@ module ad_lvds_in ( assign up_drdata = up_drdata_s[8:4]; (* IODELAY_GROUP = IODELAY_GROUP *) IDELAYE3 #( + .SIM_DEVICE ("ULTRASCALE_PLUS_ES1"), .DELAY_SRC ("IDATAIN"), .DELAY_TYPE ("VAR_LOAD"), .REFCLK_FREQUENCY (200.0),