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ad_lvds_in- ultrascale sim device

main
Rejeesh Kutty 2016-10-10 10:39:35 -04:00
parent b3d3876dc5
commit cc6ca4f0f2
1 changed files with 9 additions and 0 deletions
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9
library/xilinx/common/ad_lvds_in.v
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@ -108,11 +108,19 @@ module ad_lvds_in (
generate generate
if (IODELAY_CTRL == 1) begin if (IODELAY_CTRL == 1) begin
if (DEVICE_TYPE == ULTRASCALE) begin
(* IODELAY_GROUP = IODELAY_GROUP *)
IDELAYCTRL #(.SIM_DEVICE ("ULTRASCALE")) i_delay_ctrl (
.RST (delay_rst),
.REFCLK (delay_clk),
.RDY (delay_locked));
end else begin
(* IODELAY_GROUP = IODELAY_GROUP *) (* IODELAY_GROUP = IODELAY_GROUP *)
IDELAYCTRL i_delay_ctrl ( IDELAYCTRL i_delay_ctrl (
.RST (delay_rst), .RST (delay_rst),
.REFCLK (delay_clk), .REFCLK (delay_clk),
.RDY (delay_locked)); .RDY (delay_locked));
end
end else begin end else begin
assign delay_locked = 1'b1; assign delay_locked = 1'b1;
end end
@ -196,6 +204,7 @@ module ad_lvds_in (
assign up_drdata = up_drdata_s[8:4]; assign up_drdata = up_drdata_s[8:4];
(* IODELAY_GROUP = IODELAY_GROUP *) (* IODELAY_GROUP = IODELAY_GROUP *)
IDELAYE3 #( IDELAYE3 #(
.SIM_DEVICE ("ULTRASCALE_PLUS_ES1"),
.DELAY_SRC ("IDATAIN"), .DELAY_SRC ("IDATAIN"),
.DELAY_TYPE ("VAR_LOAD"), .DELAY_TYPE ("VAR_LOAD"),
.REFCLK_FREQUENCY (200.0), .REFCLK_FREQUENCY (200.0),