altera- java/tcl mess handling
Rejeesh Kutty
parent
a9d03af771
commit
cc75fa3dfe
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@ -191,7 +191,7 @@ module __ad_serdes_clk__ #(
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.pll_reconfig_read (up_drp_rd_int),
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.pll_reconfig_write (up_drp_wr_int),
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.pll_reconfig_readdata (up_drp_rdata_int_s),
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.pll_reconfig_address (up_drp_addr_int),
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.pll_reconfig_address (up_drp_addr_int[5:0]),
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.pll_reconfig_writedata (up_drp_wdata_int));
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cyclonev_pll_lvds_output #(
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@ -136,89 +136,17 @@ module __ad_serdes_in__ #(
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for (n = 0; n < DATA_WIDTH; n = n + 1) begin: g_data
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if (DEVICE_TYPE == CYCLONE5) begin
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altlvds_rx #(
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.buffer_implementation ("RAM"),
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.cds_mode ("UNUSED"),
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.common_rx_tx_pll ("ON"),
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.data_align_rollover (4),
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.data_rate ("500.0 Mbps"),
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.deserialization_factor (4),
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.dpa_initial_phase_value (0),
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.dpll_lock_count (0),
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.dpll_lock_window (0),
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.enable_clock_pin_mode ("UNUSED"),
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.enable_dpa_align_to_rising_edge_only ("OFF"),
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.enable_dpa_calibration ("ON"),
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.enable_dpa_fifo ("UNUSED"),
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.enable_dpa_initial_phase_selection ("OFF"),
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.enable_dpa_mode ("OFF"),
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.enable_dpa_pll_calibration ("OFF"),
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.enable_soft_cdr_mode ("OFF"),
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.implement_in_les ("OFF"),
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.inclock_boost (0),
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.inclock_data_alignment ("EDGE_ALIGNED"),
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.inclock_period (4000),
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.inclock_phase_shift (0),
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.input_data_rate (500),
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.intended_device_family ("Cyclone V"),
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.lose_lock_on_one_change ("UNUSED"),
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.lpm_hint ("CBX_MODULE_PREFIX=ad_serdes_in"),
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.lpm_type ("altlvds_rx"),
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.number_of_channels (DATA_WIDTH),
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.outclock_resource ("Regional clock"),
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.pll_operation_mode ("NORMAL"),
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.pll_self_reset_on_loss_lock ("UNUSED"),
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.port_rx_channel_data_align ("PORT_UNUSED"),
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.port_rx_data_align ("PORT_UNUSED"),
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.refclk_frequency ("250.000000 MHz"),
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.registered_data_align_input ("UNUSED"),
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.registered_output ("ON"),
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.reset_fifo_at_first_lock ("UNUSED"),
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.rx_align_data_reg ("RISING_EDGE"),
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.sim_dpa_is_negative_ppm_drift ("OFF"),
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.sim_dpa_net_ppm_variation (0),
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.sim_dpa_output_clock_phase_shift (0),
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.use_coreclock_input ("OFF"),
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.use_dpll_rawperror ("OFF"),
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.use_external_pll ("ON"),
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.use_no_phase_shift ("ON"),
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.x_on_bitslip ("ON"),
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.clk_src_is_pll ("off"))
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i_altlvds_rx (
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.rx_inclock (clk),
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.rx_in (data_in_p[n]),
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.rx_outclock (),
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.rx_out (data_out_s[n]),
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.rx_locked (),
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.dpa_pll_cal_busy (),
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.dpa_pll_recal (1'b0),
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.pll_areset (~locked),
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.pll_phasecounterselect (),
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.pll_phasedone (1'b1),
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.pll_phasestep (),
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.pll_phaseupdown (),
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.pll_scanclk (),
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.rx_cda_max (),
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.rx_cda_reset ({7{1'b0}}),
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.rx_channel_data_align ({7{1'b0}}),
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.rx_coreclk (1'b1),
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.rx_data_align (1'b0),
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.rx_data_align_reset (1'b0),
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.rx_data_reset (1'b0),
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.rx_deskew (1'b0),
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.rx_divfwdclk (),
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.rx_dpa_lock_reset ({7{1'b0}}),
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.rx_dpa_locked (),
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.rx_dpaclock (1'b0),
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.rx_dpll_enable ({7{1'b1}}),
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.rx_dpll_hold ({7{1'b0}}),
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.rx_dpll_reset ({7{1'b0}}),
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.rx_enable (loaden),
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.rx_fifo_reset ({7{1'b0}}),
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.rx_pll_enable (1'b1),
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.rx_readclock (1'b0),
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.rx_reset ({7{1'b0}}),
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.rx_syncclock (1'b0));
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assign delay_locked_s[n] = 1'b1;
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ad_serdes_in_core_c5 #(
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.SERDES_FACTOR (SERDES_FACTOR))
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i_core (
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.clk (clk),
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.div_clk (div_clk),
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.enable (loaden),
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.data_in (data_in_p[n]),
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.data (data_out_s[n]));
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end
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if (DEVICE_TYPE == ARRIA10) begin
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@ -109,53 +109,14 @@ module __ad_serdes_out__ #(
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for (n = 0; n < DATA_WIDTH; n = n + 1) begin: g_data
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if (DEVICE_TYPE == CYCLONE5) begin
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altlvds_tx #(
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.center_align_msb ("UNUSED"),
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.common_rx_tx_pll ("ON"),
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.coreclock_divide_by (1),
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.data_rate ("500.0 Mbps"),
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.deserialization_factor (4),
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.differential_drive (0),
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.enable_clock_pin_mode ("UNUSED"),
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.implement_in_les ("OFF"),
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.inclock_boost (0),
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.inclock_data_alignment ("EDGE_ALIGNED"),
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.inclock_period (4000),
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.inclock_phase_shift (0),
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.intended_device_family ("Cyclone V"),
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.lpm_hint ("CBX_MODULE_PREFIX=ad_serdes_out"),
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.lpm_type ("altlvds_tx"),
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.multi_clock ("OFF"),
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.number_of_channels (DATA_WIDTH),
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.outclock_alignment ("EDGE_ALIGNED"),
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.outclock_divide_by (2),
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.outclock_duty_cycle (50),
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.outclock_multiply_by (1),
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.outclock_phase_shift (0),
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.outclock_resource ("Regional clock"),
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.output_data_rate (500),
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.pll_compensation_mode ("AUTO"),
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.pll_self_reset_on_loss_lock ("OFF"),
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.preemphasis_setting (0),
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.refclk_frequency ("250.000000 MHz"),
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.registered_input ("TX_CORECLK"),
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.use_external_pll ("ON"),
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.use_no_phase_shift ("ON"),
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.vod_setting (0),
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.clk_src_is_pll ("off"))
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i_altlvds_tx (
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.tx_inclock (clk),
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.tx_coreclock (div_clk),
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.tx_in (data_in_s[n]),
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.tx_outclock (),
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.tx_out (data_out_p[n]),
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.tx_locked (),
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.pll_areset (1'b0),
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.sync_inclock (1'b0),
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.tx_data_reset (1'b0),
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.tx_enable (loaden),
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.tx_pll_enable (1'b1),
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.tx_syncclock (1'b0));
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ad_serdes_out_core_c5 #(
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.SERDES_FACTOR (SERDES_FACTOR))
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i_core (
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.clk (clk),
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.div_clk (div_clk),
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.enable (loaden),
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.data_out (data_out_p[n]),
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.data (data_in_s[n]));
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end
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if (DEVICE_TYPE == ARRIA10) begin
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@ -436,8 +436,8 @@ module axi_ad9361_lvds_if #(
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.data_in_p (rx_frame_in_p),
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.data_in_n (rx_frame_in_n),
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.up_clk (1'd0),
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.up_dld (6'd0),
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.up_dwdata (30'd0),
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.up_dld (1'd0),
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.up_dwdata (5'd0),
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.up_drdata (),
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.delay_clk (1'd0),
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.delay_rst (1'd0),
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@ -89,6 +89,41 @@ proc ad_generate_module_inst { inst_name mark source_file target_file } {
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close $fp_target
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}
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proc ad_ip_parameter {pname ptype pdefault} {
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add_parameter $pname $ptype $pdefault
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set_parameter_property $pname HDL_PARAMETER true
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set_parameter_property $pname ENABLED true
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}
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proc ad_ip_files {pname pfiles {pfunction ""}} {
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set ftopfile [lindex $pfiles end]
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set pfiles [lreplace $pfiles end end]
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add_fileset quartus_synth QUARTUS_SYNTH $pfunction ""
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set_fileset_property quartus_synth TOP_LEVEL $pname
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foreach pfile $pfiles {
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set pmodule [file tail $pfile]
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add_fileset_file $pmodule VERILOG PATH $pfile
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}
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set pfile $ftopfile
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set pmodule [file tail $pfile]
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add_fileset_file $pmodule VERILOG PATH $pfile TOP_LEVEL_FILE
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add_fileset quartus_sim SIM_VERILOG $pfunction ""
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set_fileset_property quartus_sim TOP_LEVEL $pname
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foreach pfile $pfiles {
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set pmodule [file tail $pfile]
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add_fileset_file $pmodule VERILOG PATH $pfile
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}
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set pfile $ftopfile
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set pmodule [file tail $pfile]
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add_fileset_file $pmodule VERILOG PATH $pfile TOP_LEVEL_FILE
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}
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proc ad_ip_intf_s_axi {aclk arstn} {
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add_interface s_axi_clock clock end
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