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axi_logic_analyzer: Added an additional delay to the trigger, to be similar with the analog path

main
Adrian Costina 2017-03-14 18:00:42 +02:00
parent 3c7f73a880
commit cd0701513a
1 changed files with 4 additions and 2 deletions
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6
library/axi_logic_analyzer/axi_logic_analyzer_trigger.v
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@ -54,7 +54,7 @@ module axi_logic_analyzer_trigger (
input trigger_logic,
output trigger_out);
output reg trigger_out);
reg [ 17:0] data_m1 = 'd0;
reg [ 17:0] low_level = 'd0;
@ -66,7 +66,9 @@ module axi_logic_analyzer_trigger (
reg trigger_active;
assign trigger_out = trigger_active;
always @(posedge clk) begin
trigger_out <= trigger_active;
end
// trigger logic:
// 0 OR