From cd0701513ad94f1ba9ae75b37e37f33536d80a3e Mon Sep 17 00:00:00 2001 From: Adrian Costina Date: Tue, 14 Mar 2017 18:00:42 +0200 Subject: [PATCH] axi_logic_analyzer: Added an additional delay to the trigger, to be similar with the analog path --- library/axi_logic_analyzer/axi_logic_analyzer_trigger.v | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/library/axi_logic_analyzer/axi_logic_analyzer_trigger.v b/library/axi_logic_analyzer/axi_logic_analyzer_trigger.v index 7b15f83da..35dfab879 100644 --- a/library/axi_logic_analyzer/axi_logic_analyzer_trigger.v +++ b/library/axi_logic_analyzer/axi_logic_analyzer_trigger.v @@ -54,7 +54,7 @@ module axi_logic_analyzer_trigger ( input trigger_logic, - output trigger_out); + output reg trigger_out); reg [ 17:0] data_m1 = 'd0; reg [ 17:0] low_level = 'd0; @@ -66,7 +66,9 @@ module axi_logic_analyzer_trigger ( reg trigger_active; - assign trigger_out = trigger_active; + always @(posedge clk) begin + trigger_out <= trigger_active; + end // trigger logic: // 0 OR